mb/google/brya: Add PCIe RTD3 for NVMe root port where missing

Attach the PCIe RTD3 driver to the M.2 NVMe root port on each variant,
with board-specific enable and reset GPIOs (EN_PP3300_SSD /
SSD_PERST_L). Enables proper runtime D3 handling and power sequencing
for the NVMe SSD, matching the pattern used for other variants/storage
types.

TEST=build/boot google/taeko, verify S0ix functional

Change-Id: I956b5cb8fd01ca70596ec682646cbe5fadb844e2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>

Author: MrChromebox

src/mainboard/google/brya/variants/aurash/overridetree.cb

@@ -123,6 +123,13 @@ chip soc/intel/alderlake
 				.clk_src = 0,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F14)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
+				register "srcclk_pin" = "0"
+				device generic 0 on end
+			end
 			probe STORAGE STORAGE_NVME
 			probe STORAGE STORAGE_UNKNOWN
 		end # SSD

src/mainboard/google/brya/variants/banshee/overridetree.cb

@@ -223,6 +223,13 @@ chip soc/intel/alderlake
 				.clk_src = 0,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A12)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
+				register "srcclk_pin" = "0"
+				device generic 0 on end
+			end
 		end
 		device ref tbt_pcie_rp3 on end
 		device ref cnvi_wifi on

src/mainboard/google/brya/variants/brask/overridetree.cb

@@ -88,6 +88,13 @@ chip soc/intel/alderlake
 				.clk_src = 0,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F14)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
+				register "srcclk_pin" = "0"
+				device generic 0 on end
+			end
 		end
 		device ref tcss_dma0 on
 			chip drivers/intel/usb4/retimer

src/mainboard/google/brya/variants/crota/overridetree.cb

@@ -237,6 +237,13 @@ chip soc/intel/alderlake
 				.clk_src = 0,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
+				register "srcclk_pin" = "0"
+				device generic 0 on end
+			end
 		end
 		device ref i2c0 on
 			chip drivers/i2c/cs42l42

src/mainboard/google/brya/variants/dochi/overridetree.cb

@@ -216,6 +216,13 @@ chip soc/intel/alderlake
 				.clk_src = 0,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
+				register "srcclk_pin" = "0"
+				device generic 0 on end
+			end
 			probe STORAGE STORAGE_UNKNOWN
 			probe STORAGE STORAGE_NVME
 		end

src/mainboard/google/brya/variants/kano/overridetree.cb

@@ -246,6 +246,13 @@ chip soc/intel/alderlake
 				.clk_src = 0,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
+				register "srcclk_pin" = "0"
+				device generic 0 on end
+			end
 		end
 		device ref tcss_dma0 on
 			chip drivers/intel/usb4/retimer

src/mainboard/google/brya/variants/kinox/overridetree.cb

@@ -285,12 +285,19 @@ chip soc/intel/alderlake
 		device ref pcie_rp9 off end
 
 		device ref pcie4_0 on
-		# Enable CPU PCIE RP 1 using CLK 0
+			# Enable CPU PCIE RP 1 using CLK 0
 			register "cpu_pcie_rp[CPU_RP(1)]" = "{
 				.clk_req = 0,
 				.clk_src = 0,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F14)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
+				register "srcclk_pin" = "0"
+				device generic 0 on end
+			end
 		end
 
 		device ref cnvi_wifi on

src/mainboard/google/brya/variants/kuldax/overridetree.cb

@@ -148,6 +148,13 @@ chip soc/intel/alderlake
 				.clk_src = 0,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F14)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
+				register "srcclk_pin" = "0"
+				device generic 0 on end
+			end
 		end
 		device ref tbt_pcie_rp0 on
 			probe MB_USBC TC_USB4

src/mainboard/google/brya/variants/moli/overridetree.cb

@@ -124,6 +124,13 @@ chip soc/intel/alderlake
 				.clk_src = 0,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F14)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
+				register "srcclk_pin" = "0"
+				device generic 0 on end
+			end
 			probe STORAGE STORAGE_NVME
 			probe STORAGE STORAGE_UNKNOWN
 		end # SSD

src/mainboard/google/brya/variants/osiris/overridetree.cb

@@ -210,6 +210,13 @@ chip soc/intel/alderlake
 				.clk_src = 0,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
+				register "srcclk_pin" = "0"
+				device generic 0 on end
+			end
 		end
 		device ref cnvi_wifi on
 			chip drivers/wifi/generic