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moore1.map.rpt
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Analysis & Synthesis report for moore1
Tue Mar 01 14:43:13 2022
Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Messages
6. Analysis & Synthesis Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+-----------------------------------------+
; Analysis & Synthesis Status ; Failed - Tue Mar 01 14:43:13 2022 ;
; Quartus II Version ; 8.1 Build 163 10/28/2008 SJ Web Edition ;
; Revision Name ; moore1 ;
; Top-level Entity Name ; moore1 ;
; Family ; FLEX10KE ;
+-----------------------------+-----------------------------------------+
+-----------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------+--------------+---------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------+--------------+---------------+
; Top-level entity name ; moore1 ; moore1 ;
; Family name ; FLEX10KE ; Stratix II ;
; Type of Retiming Performed During Resynthesis ; Full ; ;
; Resynthesis Optimization Effort ; Normal ; ;
; Physical Synthesis Level for Resynthesis ; Normal ; ;
; Use Generated Physical Constraints File ; On ; ;
; Use smart compilation ; Off ; Off ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Parallel Synthesis ; Off ; Off ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Auto Implement in ROM ; Off ; Off ;
; Optimization Technique ; Area ; Area ;
; Carry Chain Length ; 32 ; 32 ;
; Cascade Chain Length ; 2 ; 2 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Block Design Naming ; Auto ; Auto ;
; Synthesis Effort ; Auto ; Auto ;
; Allows Asynchronous Clear Usage For Shift Register Replacement ; On ; On ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
+----------------------------------------------------------------+--------------+---------------+
+-----------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+-----------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------+------------------------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 8.1 Build 163 10/28/2008 SJ Web Edition
Info: Processing started: Tue Mar 01 14:43:12 2022
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off moore1 -c moore1
Error (10500): VHDL syntax error at moore1.vhd(1) near text "module"; expecting "entity", or "architecture", or "use", or "library", or "package", or "configuration" File: c:/altera/81/quartus/moore1.vhd Line: 1
Error (10500): VHDL syntax error at moore1.vhd(8) near text @ File: c:/altera/81/quartus/moore1.vhd Line: 8
Error (10500): VHDL syntax error at moore1.vhd(19) near text @ File: c:/altera/81/quartus/moore1.vhd Line: 19
Info: Found 0 design units, including 0 entities, in source file moore1.vhd
Info: Found 1 design units, including 1 entities, in source file Verilog1.v
Info: Found entity 1: moore1
Error (10228): Verilog HDL error at moore1.v(1): module "moore1" cannot be declared more than once File: c:/altera/81/quartus/moore1.v Line: 1
Info (10151): Verilog HDL Declaration information at Verilog1.v(1): "moore1" is declared here
Info: Found 0 design units, including 0 entities, in source file moore1.v
Info: Generated suppressed messages file c:/altera/81/quartus/moore1.map.smsg
Error: Quartus II Analysis & Synthesis was unsuccessful. 4 errors, 0 warnings
Error: Peak virtual memory: 234 megabytes
Error: Processing ended: Tue Mar 01 14:43:13 2022
Error: Elapsed time: 00:00:01
Error: Total CPU time (on all processors): 00:00:00
+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in c:/altera/81/quartus/moore1.map.smsg.