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ci: replace heavy OpenLane CI with lightweight RTL simulation checks #6

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ci: replace heavy OpenLane CI with lightweight RTL simulation checks

ci: replace heavy OpenLane CI with lightweight RTL simulation checks #6

Workflow file for this run

.github/workflows/user_project_ci.yml at 80416b3
name: CI
on:
push:
branches: [ main ]
pull_request:
branches: [ main ]
jobs:
rtl_sim:
name: RTL Simulation
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v3
- name: Install Icarus Verilog
run: sudo apt-get install -y iverilog
- name: Simulate PWM DAC
run: |
iverilog -o /tmp/pwm_dac_sim \
rtl/digital/pwm_dac/pwm_dac.v \
sim/digital/tb_pwm_dac.v
vvp /tmp/pwm_dac_sim
- name: Simulate CIC Decimator
run: |
iverilog -o /tmp/cic_sim \
rtl/digital/cic/cic_decimator.v \
sim/digital/tb_cic.v
vvp /tmp/cic_sim
- name: Simulate FIR Filter
run: |
iverilog -o /tmp/fir_sim \
rtl/digital/fir/fir_filter.v \
sim/digital/tb_fir.v
vvp /tmp/fir_sim
- name: Simulate Wishbone CSR
run: |
iverilog -o /tmp/wb_csr_sim \
rtl/digital/wishbone_csr/wb_csr.v \
sim/digital/tb_wb_csr.v
vvp /tmp/wb_csr_sim
- name: Integration Smoke Test
run: |
iverilog -o /tmp/top_sim \
verilog/rtl/user_project_wrapper.v \
rtl/digital/wishbone_csr/wb_csr.v \
rtl/digital/cic/cic_decimator.v \
rtl/digital/fir/fir_filter.v \
rtl/digital/pwm_dac/pwm_dac.v \
rtl/digital/lfsr/lfsr.v \
sim/digital/tb_top.v
vvp /tmp/top_sim