fix: add SPDX headers, remove inclusive language, cleanup binaries

Author: Mummanajagadeesh

.gitignore

@@ -29,3 +29,6 @@ sim/gl/gl_sim
 sim/gl/*.vcd
 verilog/gl/user_project_wrapper.v
 verilog/gl/user_project_wrapper.v
+*.vcd
+sim/digital/*_sim
+sim/gl/*_sim

.readthedocs.yaml

@@ -1,3 +1,6 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+# SPDX-License-Identifier: Apache-2.0
+
 # .readthedocs.yaml
 # Read the Docs configuration file
 # See https://docs.readthedocs.io/en/stable/config-file/v2.html for details

docs/README.md

@@ -201,7 +201,7 @@ LFSR ---------+          |             |        |
 
 | Block | File | Description |
 |---|---|---|
-| `wb_csr` | `rtl/digital/wishbone_csr/wb_csr.v` | Wishbone B4 slave CSR. Decodes address offsets, drives all control signals, captures status. Single-cycle ACK. |
+| `wb_csr` | `rtl/digital/wishbone_csr/wb_csr.v` | Wishbone B4 peripheral CSR. Decodes address offsets, drives all control signals, captures status. Single-cycle ACK. |
 | `cic_decimator` | `rtl/digital/cic/cic_decimator.v` | 3-stage CIC filter. Integrators run at full clock rate. Comb sections triggered by decimation pulse at `clk / OSR`. 16-bit internal word width. |
 | `fir_filter` | `rtl/digital/fir/fir_filter.v` | 8-tap direct-form I FIR. Combinational MAC with registered output. Q1.15 coefficients. Initialized to identity (passthrough) on reset. Runtime-loadable via CSR. |
 | `pwm_dac` | `rtl/digital/pwm_dac/pwm_dac.v` | First-order delta-sigma PWM modulator. 8-bit accumulator, carry-out is the output bit. |

rtl/digital/cic/cic_decimator.v

@@ -1,3 +1,9 @@
+// SPDX-FileCopyrightText: 2026 Mummana Jagadeesh
+// SPDX-License-Identifier: Apache-2.0
+
+
+// SPDX-License-Identifier: Apache-2.0
+
 module cic_decimator #(
     parameter N_STAGES  = 3,
     parameter WIDTH     = 16,

rtl/digital/fir/fir_filter.v

@@ -1,3 +1,9 @@
+// SPDX-FileCopyrightText: 2026 Mummana Jagadeesh
+// SPDX-License-Identifier: Apache-2.0
+
+
+// SPDX-License-Identifier: Apache-2.0
+
 module fir_filter #(
     parameter N_TAPS  = 8,
     parameter WIDTH   = 16

rtl/digital/lfsr/lfsr.v

@@ -1,3 +1,9 @@
+// SPDX-FileCopyrightText: 2026 Mummana Jagadeesh
+// SPDX-License-Identifier: Apache-2.0
+
+
+// SPDX-License-Identifier: Apache-2.0
+
 module lfsr (
     input  wire clk,
     input  wire rst_n,

rtl/digital/pwm_dac/pwm_dac.v

@@ -1,3 +1,9 @@
+// SPDX-FileCopyrightText: 2026 Mummana Jagadeesh
+// SPDX-License-Identifier: Apache-2.0
+
+
+// SPDX-License-Identifier: Apache-2.0
+
 // PWM DAC - 8-bit, first-order delta-sigma style
 // Input: 8-bit parallel data from Wishbone CSR
 // Output: 1-bit PWM on GPIO

rtl/digital/wishbone_csr/wb_csr.v

@@ -1,3 +1,9 @@
+// SPDX-FileCopyrightText: 2026 Mummana Jagadeesh
+// SPDX-License-Identifier: Apache-2.0
+
+
+// SPDX-License-Identifier: Apache-2.0
+
 // Wishbone CSR Block
 // Register map (32-bit word addresses):
 // 0x00 - CTRL      [0]=enable, [1]=bypass_fir, [2]=bypass_cic,