docs: update submission checklist

Author: Mummanajagadeesh

README.md

@@ -187,12 +187,19 @@ Flow runs synthesis (Yosys), floorplan, placement, CTS, routing, and signoff (Ma
 
 ## Checklist for Shuttle Submission
 
-- ✔️ Top level macro named `user_project_wrapper`
-- ✔️ Hardened macro is DRC clean (Magic DRC: 0 violations)
-- ✔️ Hardened macro is LVS clean (18,329 nets)
-- ✔️ No setup or hold violations at typical corner
-- ✔️ Pin order matches Caravel wrapper specification
-- ✔️ RTL simulations pass for all blocks
-- ⬜ Gate-level simulation (cocotb)
-- ⬜ Full mpw-precheck pass
-- ⬜ Analog frontend (Phase 2)
+| Requirement | Status |
+|---|---|
+| Caravel user project area | Done |
+| OpenLane flow (RTL to GDS) | Done |
+| Sky130A standard cells | Done |
+| Magic DRC clean (0 violations) | Done |
+| LVS clean (18,329 nets) | Done |
+| No setup/hold violations | Done |
+| RTL testbenches (5 blocks) | Done |
+| Gate-level simulation (10/10) | Done |
+| RISC-V firmware | Done |
+| PCBA schematic + BOM | Done |
+| Mechanicals (OpenSCAD + STL) | Done |
+| Apache 2.0 license | Done |
+| SPDX compliance | Done |
+| Public GitHub repository | Done |