595.45.04

Author: aritger

README.md

@@ -1,7 +1,7 @@
 # NVIDIA Linux Open GPU Kernel Module Source
 
 This is the source release of the NVIDIA Linux open GPU kernel modules,
-version 590.48.01.
+version 595.45.04.
 
 
 ## How to Build
@@ -17,7 +17,7 @@ as root:
 
 Note that the kernel modules built here must be used with GSP
 firmware and user-space NVIDIA GPU driver components from a corresponding
-590.48.01 driver release.  This can be achieved by installing
+595.45.04 driver release.  This can be achieved by installing
 the NVIDIA GPU driver from the .run file using the `--no-kernel-modules`
 option.  E.g.,
 
@@ -185,7 +185,7 @@ table below).
 For details on feature support and limitations, see the NVIDIA GPU driver
 end user README here:
 
-https://us.download.nvidia.com/XFree86/Linux-x86_64/590.48.01/README/kernel_open.html
+https://us.download.nvidia.com/XFree86/Linux-x86_64/595.45.04/README/kernel_open.html
 
 For vGPU support, please refer to the README.vgpu packaged in the vGPU Host
 Package for more details.
@@ -845,6 +845,7 @@ Subsystem Device ID.
 | NVIDIA RTX A400                                         | 25B2 1028 1879 |
 | NVIDIA RTX A400                                         | 25B2 103C 1879 |
 | NVIDIA RTX A400                                         | 25B2 103C 8D95 |
+| NVIDIA RTX A400                                         | 25B2 103C 8F5B |
 | NVIDIA RTX A400                                         | 25B2 10DE 1879 |
 | NVIDIA RTX A400                                         | 25B2 17AA 1879 |
 | NVIDIA A16                                              | 25B6 10DE 14A9 |
@@ -971,6 +972,7 @@ Subsystem Device ID.
 | NVIDIA RTX PRO 6000 Blackwell Max-Q Workstation Edition | 2BB4 10DE 204C |
 | NVIDIA RTX PRO 6000 Blackwell Max-Q Workstation Edition | 2BB4 17AA 204C |
 | NVIDIA RTX PRO 6000 Blackwell Server Edition            | 2BB5 10DE 204E |
+| NVIDIA RTX PRO 6000 Blackwell Server Edition            | 2BB5 10DE 220B |
 | NVIDIA RTX 6000D                                        | 2BB9 10DE 2091 |
 | NVIDIA GeForce RTX 5080                                 | 2C02           |
 | NVIDIA GeForce RTX 5070 Ti                              | 2C05           |

kernel-open/Kbuild

@@ -79,11 +79,11 @@ ccflags-y += -I$(src)/common/inc
 ccflags-y += -I$(src)
 ccflags-y += -Wall $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-format-extra-args
 ccflags-y += -D__KERNEL__ -DMODULE -DNVRM
-ccflags-y += -DNV_VERSION_STRING=\"590.48.01\"
+ccflags-y += -DNV_VERSION_STRING=\"595.45.04\"
 
 # Include and link Tegra out-of-tree modules.
-ifneq ($(wildcard /usr/src/nvidia/nvidia-oot),)
- SYSSRCNVOOT ?= /usr/src/nvidia/nvidia-oot
+ifneq ($(wildcard /usr/src/nvidia/nvidia-public),)
+ SYSSRCNVOOT ?= /usr/src/nvidia/nvidia-public
 endif
 
 ifneq ($(SYSSRCHOST1X),)

kernel-open/common/inc/cpuopsys.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2018-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2018-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -28,7 +28,7 @@
  *
  * cpuopsys.h
  *
- * Copyright (c) 2001, Nvidia Corporation.  All rights reserved.
+ * Copyright (c) 2001-2025, Nvidia Corporation.  All rights reserved.
  */
 
 /*!
@@ -134,7 +134,6 @@
 #endif
 
 /* ***** Processor type variations */
-/* Note: The prefix NV_CPU_* is taken by Nvcm.h */
 
 #if ((defined(_M_IX86) || defined(__i386__) || defined(__i386)) && !defined(NVCPU_X86)) /* XXX until removed from Makefiles */
 /* _M_IX86 for windows, __i386__ for Linux (or any x86 using gcc) */

kernel-open/common/inc/nv-firmware-registry.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -59,8 +59,9 @@
 #define NV_REG_ENABLE_GPU_FIRMWARE_MODE_ENABLED           0x00000001
 #define NV_REG_ENABLE_GPU_FIRMWARE_MODE_DEFAULT           0x00000002
 
-#define NV_REG_ENABLE_GPU_FIRMWARE_POLICY_MASK            0x000000F0
-#define NV_REG_ENABLE_GPU_FIRMWARE_POLICY_ALLOW_FALLBACK  0x00000010
+#define NV_REG_ENABLE_GPU_FIRMWARE_POLICY_MASK                  0x000000F0
+#define NV_REG_ENABLE_GPU_FIRMWARE_POLICY_ALLOW_FALLBACK        0x00000010
+#define NV_REG_ENABLE_GPU_FIRMWARE_POLICY_DEFAULT_ON_WS_SERVER  0x00000020
 
 #define NV_REG_ENABLE_GPU_FIRMWARE_DEFAULT_VALUE          0x00000012
 

kernel-open/common/inc/nv-gpu-info.h

@@ -33,6 +33,7 @@ typedef struct {
     } pci_info;
 
     NvBool needs_numa_setup;
+    NvBool is_soc_disp;
 
     /*
      * opaque OS-specific pointer; on Linux, this is a pointer to the

kernel-open/common/inc/nv-ioctl-numbers.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2020-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -26,6 +26,10 @@
 #define NV_IOCTL_NUMBERS_H
 
 /* NOTE: using an ioctl() number > 55 will overflow! */
+/* 
+ * NOTE: Any new ioctls added here should also be added to nv_validate_ioctls() in nv.c or
+ * rm_validate_ioctls() in osapi.c
+ */
 #define NV_IOCTL_MAGIC      'F'
 #define NV_IOCTL_BASE       200
 #define NV_ESC_CARD_INFO             (NV_IOCTL_BASE + 0)

kernel-open/common/inc/nv-linux.h

@@ -129,6 +129,7 @@
 #include <asm/pgtable.h>            /* pte bit definitions              */
 #include <asm/bitops.h>             /* __set_bit()                      */
 #include <linux/time.h>             /* FD_SET()                         */
+#include <linux/memremap.h>
 
 /*
  * Use current->cred->euid, instead of calling current_euid().
@@ -503,7 +504,7 @@ static inline pgprot_t nv_adjust_pgprot(pgprot_t vm_prot)
 
 #define NV_HAVE_MEMORY_ENCRYPT_DECRYPT 0
 
-#if defined(NVCPU_X86_64) && \
+#if (defined(NVCPU_X86_64) || defined(NVCPU_AARCH64)) && \
     NV_IS_EXPORT_SYMBOL_GPL_set_memory_encrypted && \
     NV_IS_EXPORT_SYMBOL_GPL_set_memory_decrypted
 #undef NV_HAVE_MEMORY_ENCRYPT_DECRYPT
@@ -553,7 +554,7 @@ static inline dma_addr_t nv_phys_to_dma(struct device *dev, NvU64 pa)
 #endif
 }
 
-#define NV_GET_PAGE_STRUCT(phys_page) virt_to_page(__va(phys_page))
+#define NV_GET_PAGE_STRUCT(phys_page) pfn_to_page(phys_page >> PAGE_SHIFT)
 #define NV_VMA_PGOFF(vma)             ((vma)->vm_pgoff)
 #define NV_VMA_SIZE(vma)              ((vma)->vm_end - (vma)->vm_start)
 #define NV_VMA_OFFSET(vma)            (((NvU64)(vma)->vm_pgoff) << PAGE_SHIFT)
@@ -562,6 +563,12 @@ static inline dma_addr_t nv_phys_to_dma(struct device *dev, NvU64 pa)
 
 #define NV_DEVICE_MINOR_NUMBER(x)     minor((x)->i_rdev)
 
+#if defined(NV_GET_DEV_PAGEMAP_HAS_PGMAP_ARG)
+#define NV_GET_DEV_PAGEMAP(pfn) get_dev_pagemap(pfn, NULL)
+#else
+#define NV_GET_DEV_PAGEMAP get_dev_pagemap
+#endif
+
 #define NV_PCI_DISABLE_DEVICE(pci_dev)                           \
     {                                                            \
         NvU16 __cmd[2];                                          \
@@ -671,18 +678,6 @@ static inline dma_addr_t nv_phys_to_dma(struct device *dev, NvU64 pa)
 #define PCI_CAP_ID_EXP 0x10
 #endif
 
-/*
- * If the host OS has page sizes larger than 4KB, we may have a security
- * problem. Registers are typically grouped in 4KB pages, but if there are
- * larger pages, then the smallest userspace mapping possible (e.g., a page)
- * may give more access than intended to the user.
- */
-#define NV_4K_PAGE_ISOLATION_REQUIRED(addr, size)                       \
-    ((PAGE_SIZE > NV_RM_PAGE_SIZE) &&                                   \
-     ((size) <= NV_RM_PAGE_SIZE) &&                                     \
-     (((addr) >> NV_RM_PAGE_SHIFT) ==                                   \
-        (((addr) + (size) - 1) >> NV_RM_PAGE_SHIFT)))
-
 static inline int nv_remap_page_range(struct vm_area_struct *vma,
     unsigned long virt_addr, NvU64 phys_addr, NvU64 size, pgprot_t prot)
 {
@@ -1212,6 +1207,10 @@ typedef struct coherent_link_info_s {
      * of virutalized OS environment it is Intermediate Physical Address(IPA) */
     NvU64 gpu_mem_pa;
 
+    /* Size of the GPU memory mappable through coherent link. It is possible
+       that less than whole FB is mapped to CPU. */
+    NvU64 gpu_mem_size;
+
     /* Physical address of the reserved portion of the GPU memory, applicable
      * only in Grace Hopper self hosted passthrough virtualizatioan platform. */
     NvU64 rsvd_mem_pa;
@@ -1374,6 +1373,13 @@ typedef struct nv_linux_state_s {
 
     /* Lock serializing ISRs for different SOC vectors */
     nv_spinlock_t soc_isr_lock;
+
+    /*
+     * Lock serializing access to the soc_isr_info struct across top and
+     * bottom halves for SOC vectors.
+     */
+    nv_spinlock_t soc_isr_info_lock;
+
     void *soc_bh_mutex;
 
     struct nv_timer snapshot_timer;
@@ -1428,6 +1434,9 @@ typedef struct nv_linux_state_s {
     int (*devfreq_enable_boost)(struct device *dev, unsigned int duration);
     int (*devfreq_disable_boost)(struct device *dev);
 #endif
+
+    /* Per-device GPU init on probe setting, initialized from global NVreg_GpuInitOnProbe */
+    NvBool init_on_probe;
 } nv_linux_state_t;
 
 extern nv_linux_state_t *nv_linux_devices;
@@ -1485,9 +1494,11 @@ typedef struct
     nv_kthread_q_item_t deferred_close_q_item;
     NvU32 *attached_gpus;
     size_t num_attached_gpus;
-    nv_alloc_mapping_context_t mmap_context;
     struct address_space mapping;
 
+    struct rw_semaphore fileVaLock;
+    nv_alloc_mapping_list_node_t *file_mapping_list;
+
     nv_kthread_q_item_t open_q_item;
     struct completion open_complete;
     nv_linux_state_t *deferred_open_nvl;
@@ -1599,6 +1610,8 @@ extern NvU32 NVreg_RegisterPlatformDeviceDriver;
 extern NvU32 NVreg_EnableResizableBar;
 extern NvU32 NVreg_TegraGpuPgMask;
 extern NvU32 NVreg_EnableNonblockingOpen;
+extern NvU32 NVreg_UseKernelSuspendNotifiers;
+extern NvU32 NVreg_GpuInitOnProbe;
 
 extern NvU32 num_probed_nv_devices;
 extern NvU32 num_nv_devices;

kernel-open/common/inc/nv-modeset-interface.h

@@ -114,8 +114,8 @@ typedef struct {
      * specified GPU.  This is equivalent to opening and closing a
      * /dev/nvidiaN device file from user-space.
      */
-    int (*open_gpu)(NvU32 gpu_id, nvidia_modeset_stack_ptr sp);
-    void (*close_gpu)(NvU32 gpu_id, nvidia_modeset_stack_ptr sp);
+    int (*open_gpu)(NvU32 gpu_id, nvidia_modeset_stack_ptr sp, NvBool reset_aware);
+    void (*close_gpu)(NvU32 gpu_id, nvidia_modeset_stack_ptr sp, NvBool reset_aware);
 
     void (*op)(nvidia_modeset_stack_ptr sp, void *ops_cmd);
 

kernel-open/common/inc/nv-pci.h

@@ -38,4 +38,5 @@ int nvidia_dev_get_pci_info(const NvU8 *, struct pci_dev **, NvU64 *, NvU64 *);
 nv_linux_state_t * find_pci(NvU32, NvU8, NvU8, NvU8);
 NvBool nv_pci_is_valid_topology_for_direct_pci(nv_state_t *, struct pci_dev *);
 NvBool nv_pci_has_common_pci_switch(nv_state_t *nv, struct pci_dev *);
+void nv_pci_tegra_boost_clocks(struct device *dev);
 #endif

kernel-open/common/inc/nv-platform.h

@@ -45,4 +45,16 @@ void      nv_soc_free_irqs(nv_state_t *nv);
 
 #define NV_SUPPORTS_PLATFORM_DISPLAY_DEVICE (NV_SUPPORTS_PLATFORM_DEVICE && NV_SUPPORTS_DCE_CLIENT_IPC)
 
+#if defined(CONFIG_OF)
+NV_STATUS   nv_platform_get_screen_info_dt(
+    NvU64 *pPhysicalAddress,
+    NvU32 *pFbWidth,
+    NvU32 *pFbHeight,
+    NvU32 *pFbDepth,
+    NvU32 *pFbPitch,
+    NvU64 *pFbSize
+);
+
+#endif // CONFIG_OF
+
 #endif