Documentation on SLA fields

[Lancelotbronner]

I'm trying to understand the structure of an SLA file and I was wondering if there was any documentation on the individual fields.
My goal is to generate the code for a decompiler given an SLA file.

I'm currently trying to understand how decision trees are iterated and select constructors to run.

[Lancelotbronner]

Here's my decision tree pretty print for instruction in the x86_64 sla file.

Decision nodes are marked instruction, context or terminal and have startbit..(startbit + size) in brackets.

Constructors decisions within those nodes are marked as either context or instruction based on their disjoint pattern.
They have nonzero@off [mask] beside them with mask simply being the pattern's bytes separated by :.

What does nonzero and off mean? How can I determine where in the instruction the mask applies?

The actual constructor they refer to is inlined with pseudo code.
The important info is on the comments, // length@first and // source:line parent.

What do length and first refer to?

instruction[0..4]
├ instruction[4..8]
│ ├ context[20..22]
│ │ ├ terminal
│ │ │ ├ context 4@0 [0xxx10xx:xxxxxxxx:xxxxxxxx:xxxxxx0x]
│ │ │ │ // 0@1
│ │ │ │ // ia.sinc:2383 0
│ │ │ │ case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(1)], i: 0, mask: 201326592, shift: 26)) && instruction:
│ │ │ │ build 0i4
│ │ │ │ assembly += "\(instruction)"
│ │ │ │ 
│ │ │ ├ context 2@2 [xxxx00xx:xxxxxxx0:xxxxxxxx:xxxxxxxx] instruction 2@0 [00000000:11xxxxxx:xxxxxxxx:xxxxxxxx]
│ │ │ │ // 2@1
│ │ │ │ // ia.sinc:2580 0
│ │ │ │ case Rmr8 && Reg8:
│ │ │ │ build 1i4
│ │ │ │ build 0i4
│ │ │ │ intCarry register[512]i1 handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0) handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0)
│ │ │ │ intScarry register[523]i1 handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0) handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0)
│ │ │ │ intAdd handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0) handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0) handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0)
│ │ │ │ intSless register[519]i1 handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0) 0ihandle(i:0,select:v_size,offset:0)
│ │ │ │ intEqual register[518]i1 handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0) 0ihandle(i:0,select:v_size,offset:0)
│ │ │ │ intAnd unique[361216]ihandle(i:0,select:v_size,offset:0) handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0) 255ihandle(i:0,select:v_size,offset:0)
│ │ │ │ popcount unique[361472]i1 unique[361216]ihandle(i:0,select:v_size,offset:0)
│ │ │ │ intAnd unique[361728]i1 unique[361472]i1 1i1
│ │ │ │ intEqual register[514]i1 unique[361728]i1 0i1
│ │ │ │ assembly += "ADD \(Rmr8),\(Reg8)"
│ │ │ │ 
│ │ │ └ context 1@2 [xxxx00xx:xxxxxxxx:xxxxxxxx:xxxxxxxx] instruction 1@0 [00000000:xxxxxxxx:xxxxxxxx:xxxxxxxx]
│ │ │   // 2@2
│ │ │   // lockable.sinc:186 0
│ │ │   case lockx && unlock && m8 && Reg8:
│ │ │   build 3i4
│ │ │   build 0i4
│ │ │   build 2i4
│ │ │   intCarry register[512]i1 handle(i:2,select:space,offset:0)[handle(i:2,select:v_offset,offset:0)]ihandle(i:2,select:v_size,offset:0) handle(i:3,select:space,offset:0)[handle(i:3,select:v_offset,offset:0)]ihandle(i:3,select:v_size,offset:0)
│ │ │   intScarry register[523]i1 handle(i:2,select:space,offset:0)[handle(i:2,select:v_offset,offset:0)]ihandle(i:2,select:v_size,offset:0) handle(i:3,select:space,offset:0)[handle(i:3,select:v_offset,offset:0)]ihandle(i:3,select:v_size,offset:0)
│ │ │   intAdd handle(i:2,select:space,offset:0)[handle(i:2,select:v_offset,offset:0)]ihandle(i:2,select:v_size,offset:0) handle(i:2,select:space,offset:0)[handle(i:2,select:v_offset,offset:0)]ihandle(i:2,select:v_size,offset:0) handle(i:3,select:space,offset:0)[handle(i:3,select:v_offset,offset:0)]ihandle(i:3,select:v_size,offset:0)
│ │ │   intSless register[519]i1 handle(i:2,select:space,offset:0)[handle(i:2,select:v_offset,offset:0)]ihandle(i:2,select:v_size,offset:0) 0ihandle(i:2,select:v_size,offset:0)
│ │ │   intEqual register[518]i1 handle(i:2,select:space,offset:0)[handle(i:2,select:v_offset,offset:0)]ihandle(i:2,select:v_size,offset:0) 0ihandle(i:2,select:v_size,offset:0)
│ │ │   intAnd unique[361216]ihandle(i:2,select:v_size,offset:0) handle(i:2,select:space,offset:0)[handle(i:2,select:v_offset,offset:0)]ihandle(i:2,select:v_size,offset:0) 255ihandle(i:2,select:v_size,offset:0)
│ │ │   popcount unique[361472]i1 unique[361216]ihandle(i:2,select:v_size,offset:0)
│ │ │   intAnd unique[361728]i1 unique[361472]i1 1i1
│ │ │   intEqual register[514]i1 unique[361728]i1 0i1
│ │ │   build 1i4
│ │ │   assembly += "ADD\(lockx) \(m8),\(Reg8)"
│ │ │   
│ │ │ 
│ │ ├ context[23..24]
│ │ │ ├ terminal
│ │ │ │ ├ context 4@0 [0xxx10xx:xxxxxxxx:xxxxxxxx:xxxxxx0x]
│ │ │ │ │ // 0@1
│ │ │ │ │ // ia.sinc:2383 0
│ │ │ │ │ case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(1)], i: 0, mask: 201326592, shift: 26)) && instruction:
│ │ │ │ │ build 0i4
│ │ │ │ │ assembly += "\(instruction)"
│ │ │ │ │ 
│ │ │ │ └ context 4@1 [xxxx001x:xxxx01x0:xxxxxxx0:00010xxx] instruction 1@0 [00000000:xxxxxxxx:xxxxxxxx:xxxxxxxx]
│ │ │ │   // 2@1
│ │ │ │   // avx.sinc:2196 0
│ │ │ │   case rexWprefix && vexVVVV_XmmReg && XmmReg1 && ZmmReg1 && XmmReg2_m128:
│ │ │ │   build 3i4
│ │ │ │   build 4i4
│ │ │ │   build 2i4
│ │ │ │   callother unique[1915392]i16 396i4 handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0) handle(i:4,select:space,offset:0)[handle(i:4,select:v_offset,offset:0)]ihandle(i:4,select:v_size,offset:0)
│ │ │ │   intZext handle(i:3,select:space,offset:0)[handle(i:3,select:v_offset,offset:0)]ihandle(i:3,select:v_size,offset:0) unique[1915392]i16
│ │ │ │   assembly += "VPSHUFB \(XmmReg1), \(vexVVVV_XmmReg), \(XmmReg2_m128)"
│ │ │ │   
│ │ │ │ 
│ │ │ └ context[36..37]
│ │ │   ├ terminal
│ │ │   │ ├ context 4@0 [0xxx10xx:xxxxxxxx:xxxxxxxx:xxxxxx0x]
│ │ │   │ │ // 0@1
│ │ │   │ │ // ia.sinc:2383 0
│ │ │   │ │ case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(1)], i: 0, mask: 201326592, shift: 26)) && instruction:
│ │ │   │ │ build 0i4
│ │ │   │ │ assembly += "\(instruction)"
│ │ │   │ │ 
│ │ │   │ └ context 4@1 [xxxx001x:xxxx01x1:xxxxxxx0:00010xxx] instruction 1@0 [00000000:xxxxxxxx:xxxxxxxx:xxxxxxxx]
│ │ │   │   // 2@1
│ │ │   │   // avx2.sinc:583 0
│ │ │   │   case rexWprefix && vexVVVV_YmmReg && YmmReg1 && ZmmReg1 && YmmReg2_m256:
│ │ │   │   build 3i4
│ │ │   │   build 4i4
│ │ │   │   build 2i4
│ │ │   │   callother unique[2131968]i32 532i4 handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0) handle(i:4,select:space,offset:0)[handle(i:4,select:v_offset,offset:0)]ihandle(i:4,select:v_size,offset:0)
│ │ │   │   intZext handle(i:3,select:space,offset:0)[handle(i:3,select:v_offset,offset:0)]ihandle(i:3,select:v_size,offset:0) unique[2131968]i32
│ │ │   │   assembly += "VPSHUFB \(YmmReg1), \(vexVVVV_YmmReg), \(YmmReg2_m256)"
│ │ │   │   
│ │ │   │ 
│ │ │   └ terminal
│ │ │     ├ context 4@0 [0xxx10xx:xxxxxxxx:xxxxxxxx:xxxxxx0x]
│ │ │     │ // 0@1
│ │ │     │ // ia.sinc:2383 0
│ │ │     │ case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(1)], i: 0, mask: 201326592, shift: 26)) && instruction:
│ │ │     │ build 0i4
│ │ │     │ assembly += "\(instruction)"
│ │ │     │ 
│ │ │     └ context 4@1 [xxxx0011:xxxx01x1:xxxxxxx0:00011xxx] instruction 1@0 [00000000:xxxxxxxx:xxxxxxxx:xxxxxxxx]
│ │ │       // 2@1
│ │ │       // avx2.sinc:1123 0
│ │ │       case YmmReg1 && ZmmReg1 && YmmReg2_m256 && imm8:
│ │ │       build 1i4
│ │ │       build 2i4
│ │ │       build 0i4
│ │ │       callother unique[2169600]i32 570i4 handle(i:2,select:space,offset:0)[handle(i:2,select:v_offset,offset:0)]ihandle(i:2,select:v_size,offset:0) handle(i:3,select:space,offset:0)[handle(i:3,select:v_offset,offset:0)]i1
│ │ │       intZext handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0) unique[2169600]i32
│ │ │       assembly += "VPERMQ \(YmmReg1), \(YmmReg2_m256), \(imm8)"
│ │ │       
│ │ │     
│ │ │   
│ │ │ 
│ │ ├ context[23..24]
│ │ │ ├ context[36..37]
│ │ │ │ ├ terminal
│ │ │ │ │ ├ context 4@0 [0xxx10xx:xxxxxxxx:xxxxxxxx:xxxxxx0x]
│ │ │ │ │ │ // 0@1
│ │ │ │ │ │ // ia.sinc:2383 0
│ │ │ │ │ │ case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(1)], i: 0, mask: 201326592, shift: 26)) && instruction:
│ │ │ │ │ │ build 0i4
│ │ │ │ │ │ assembly += "\(instruction)"
│ │ │ │ │ │ 
│ │ │ │ │ ├ context 4@1 [xxxx001x:xxxx1010:xxxxxxx0:00010xxx] instruction 1@0 [00000000:xxxxxxxx:xxxxxxxx:xxxxxxxx]
│ │ │ │ │ │ // 2@1
│ │ │ │ │ │ // avx512.sinc:4594 0
│ │ │ │ │ │ case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(1)], i: 1, mask: 1048576, shift: 20)) && context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(0)], i: 1, mask: 983040, shift: 16)) && rexWprefix && evexV5_ZmmReg && ZmmReg1 && ZmmOpMask8 && ZmmReg2_m512:
│ │ │ │ │ │ build 4i4
│ │ │ │ │ │ build 2i4
│ │ │ │ │ │ callother register[2300]i64 846i4 handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0) handle(i:4,select:space,offset:0)[handle(i:4,select:v_offset,offset:0)]ihandle(i:4,select:v_size,offset:0)
│ │ │ │ │ │ copy register[2364]i64 handle(i:2,select:space,offset:0)[handle(i:2,select:v_offset,offset:0)]ihandle(i:2,select:v_size,offset:0)
│ │ │ │ │ │ build 3i4
│ │ │ │ │ │ copy handle(i:2,select:space,offset:0)[handle(i:2,select:v_offset,offset:0)]ihandle(i:2,select:v_size,offset:0) register[2300]i64
│ │ │ │ │ │ assembly += "VPSHUFB \(ZmmReg1)\(ZmmOpMask8), \(evexV5_ZmmReg), \(ZmmReg2_m512)"
│ │ │ │ │ │ 
│ │ │ │ │ └ context 4@1 [xxxx001x:xxxx10x0:xxxxxxx0:00010xxx] instruction 1@0 [00000000:xxxxxxxx:xxxxxxxx:xxxxxxxx]
│ │ │ │ │   // 2@1
│ │ │ │ │   // avx512.sinc:4573 0
│ │ │ │ │   case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(1)], i: 1, mask: 1048576, shift: 20)) && context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(0)], i: 1, mask: 983040, shift: 16)) && rexWprefix && evexV5_XmmReg && XmmReg1 && ZmmReg1 && XmmOpMask8 && XmmReg2_m128:
│ │ │ │ │   build 3i4
│ │ │ │ │   build 5i4
│ │ │ │ │   build 2i4
│ │ │ │ │   callother register[2300]i16 845i4 handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0) handle(i:5,select:space,offset:0)[handle(i:5,select:v_offset,offset:0)]ihandle(i:5,select:v_size,offset:0)
│ │ │ │ │   copy register[2364]i16 handle(i:2,select:space,offset:0)[handle(i:2,select:v_offset,offset:0)]ihandle(i:2,select:v_size,offset:0)
│ │ │ │ │   build 4i4
│ │ │ │ │   intZext handle(i:3,select:space,offset:0)[handle(i:3,select:v_offset,offset:0)]ihandle(i:3,select:v_size,offset:0) register[2300]i16
│ │ │ │ │   assembly += "VPSHUFB \(XmmReg1)\(XmmOpMask8), \(evexV5_XmmReg), \(XmmReg2_m128)"
│ │ │ │ │   
│ │ │ │ │ 
│ │ │ │ └ terminal
│ │ │ │   ├ context 4@0 [0xxx10xx:xxxxxxxx:xxxxxxxx:xxxxxx0x]
│ │ │ │   │ // 0@1
│ │ │ │   │ // ia.sinc:2383 0
│ │ │ │   │ case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(1)], i: 0, mask: 201326592, shift: 26)) && instruction:
│ │ │ │   │ build 0i4
│ │ │ │   │ assembly += "\(instruction)"
│ │ │ │   │ 
│ │ │ │   └ context 4@1 [xxxx0011:xxxx1010:xxxxxxx0:00011xxx] instruction 1@0 [00000000:xxxxxxxx:xxxxxxxx:xxxxxxxx]
│ │ │ │     // 2@1
│ │ │ │     // avx512.sinc:11429 0
│ │ │ │     case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(0)], i: 1, mask: 1048576, shift: 20)) && context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(0)], i: 1, mask: 983040, shift: 16)) && ZmmReg1 && ZmmOpMask64 && ZmmReg2_m512_m64bcst && imm8:
│ │ │ │     build 2i4
│ │ │ │     build 0i4
│ │ │ │     callother register[2300]i64 1255i4 handle(i:2,select:space,offset:0)[handle(i:2,select:v_offset,offset:0)]ihandle(i:2,select:v_size,offset:0) handle(i:3,select:space,offset:0)[handle(i:3,select:v_offset,offset:0)]i1
│ │ │ │     copy register[2364]i64 handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0)
│ │ │ │     build 1i4
│ │ │ │     copy handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0) register[2300]i64
│ │ │ │     assembly += "VPERMQ \(ZmmReg1)\(ZmmOpMask64), \(ZmmReg2_m512_m64bcst), \(imm8)"
│ │ │ │     
│ │ │ │   
│ │ │ │ 
│ │ │ └ context[36..37]
│ │ │   ├ terminal
│ │ │   │ ├ context 4@0 [0xxx10xx:xxxxxxxx:xxxxxxxx:xxxxxx0x]
│ │ │   │ │ // 0@1
│ │ │   │ │ // ia.sinc:2383 0
│ │ │   │ │ case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(1)], i: 0, mask: 201326592, shift: 26)) && instruction:
│ │ │   │ │ build 0i4
│ │ │   │ │ assembly += "\(instruction)"
│ │ │   │ │ 
│ │ │   │ └ context 4@1 [xxxx001x:xxxx10x1:xxxxxxx0:00010xxx] instruction 1@0 [00000000:xxxxxxxx:xxxxxxxx:xxxxxxxx]
│ │ │   │   // 2@1
│ │ │   │   // avx512.sinc:4583 0
│ │ │   │   case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(1)], i: 1, mask: 1048576, shift: 20)) && context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(0)], i: 1, mask: 983040, shift: 16)) && rexWprefix && evexV5_YmmReg && YmmReg1 && ZmmReg1 && YmmOpMask8 && YmmReg2_m256:
│ │ │   │   build 3i4
│ │ │   │   build 5i4
│ │ │   │   build 2i4
│ │ │   │   callother register[2300]i32 845i4 handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0) handle(i:5,select:space,offset:0)[handle(i:5,select:v_offset,offset:0)]ihandle(i:5,select:v_size,offset:0)
│ │ │   │   copy register[2364]i32 handle(i:2,select:space,offset:0)[handle(i:2,select:v_offset,offset:0)]ihandle(i:2,select:v_size,offset:0)
│ │ │   │   build 4i4
│ │ │   │   intZext handle(i:3,select:space,offset:0)[handle(i:3,select:v_offset,offset:0)]ihandle(i:3,select:v_size,offset:0) register[2300]i32
│ │ │   │   assembly += "VPSHUFB \(YmmReg1)\(YmmOpMask8), \(evexV5_YmmReg), \(YmmReg2_m256)"
│ │ │   │   
│ │ │   │ 
│ │ │   └ terminal
│ │ │     ├ context 4@0 [0xxx10xx:xxxxxxxx:xxxxxxxx:xxxxxx0x]
│ │ │     │ // 0@1
│ │ │     │ // ia.sinc:2383 0
│ │ │     │ case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(1)], i: 0, mask: 201326592, shift: 26)) && instruction:
│ │ │     │ build 0i4
│ │ │     │ assembly += "\(instruction)"
│ │ │     │ 
│ │ │     └ context 4@1 [xxxx0011:xxxx10x1:xxxxxxx0:00011xxx] instruction 1@0 [00000000:xxxxxxxx:xxxxxxxx:xxxxxxxx]
│ │ │       // 2@1
│ │ │       // avx512.sinc:11418 0
│ │ │       case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(0)], i: 1, mask: 1048576, shift: 20)) && context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(0)], i: 1, mask: 983040, shift: 16)) && YmmReg1 && ZmmReg1 && YmmOpMask64 && YmmReg2_m256_m64bcst && imm8:
│ │ │       build 1i4
│ │ │       build 3i4
│ │ │       build 0i4
│ │ │       callother register[2300]i32 1254i4 handle(i:3,select:space,offset:0)[handle(i:3,select:v_offset,offset:0)]ihandle(i:3,select:v_size,offset:0) handle(i:4,select:space,offset:0)[handle(i:4,select:v_offset,offset:0)]i1
│ │ │       copy register[2364]i32 handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0)
│ │ │       build 2i4
│ │ │       intZext handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0) register[2300]i32
│ │ │       assembly += "VPERMQ \(YmmReg1)\(YmmOpMask64), \(YmmReg2_m256_m64bcst), \(imm8)"
│ │ │       
│ │ │     
│ │ │   
│ │ │ 
│ │ └ terminal
│ │   └ context 4@0 [0xxx10xx:xxxxxxxx:xxxxxxxx:xxxxxx0x]
│ │     // 0@1
│ │     // ia.sinc:2383 0
│ │     case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(1)], i: 0, mask: 201326592, shift: 26)) && instruction:
│ │     build 0i4
│ │     assembly += "\(instruction)"
│ │     
│ │   
│ │ 
│ ├ context[20..22]
│ │ ├ context[6..8]
│ │ │ ├ terminal
│ │ │ │ ├ context 4@0 [0xxx10xx:xxxxxxxx:xxxxxxxx:xxxxxx0x]
│ │ │ │ │ // 0@1
│ │ │ │ │ // ia.sinc:2383 0
│ │ │ │ │ case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(1)], i: 0, mask: 201326592, shift: 26)) && instruction:
│ │ │ │ │ build 0i4
│ │ │ │ │ assembly += "\(instruction)"
│ │ │ │ │ 
│ │ │ │ ├ context 4@0 [xxxxxx00:xxxxxxxx:xxxx00xx:xxxxxxx0] instruction 2@0 [00000001:11xxxxxx:xxxxxxxx:xxxxxxxx]
│ │ │ │ │ // 2@1
│ │ │ │ │ // ia.sinc:2581 0
│ │ │ │ │ case Rmr16 && Reg16:
│ │ │ │ │ build 1i4
│ │ │ │ │ build 0i4
│ │ │ │ │ intCarry register[512]i1 handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0) handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0)
│ │ │ │ │ intScarry register[523]i1 handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0) handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0)
│ │ │ │ │ intAdd handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0) handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0) handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0)
│ │ │ │ │ intSless register[519]i1 handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0) 0ihandle(i:0,select:v_size,offset:0)
│ │ │ │ │ intEqual register[518]i1 handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0) 0ihandle(i:0,select:v_size,offset:0)
│ │ │ │ │ intAnd unique[361216]ihandle(i:0,select:v_size,offset:0) handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0) 255ihandle(i:0,select:v_size,offset:0)
│ │ │ │ │ popcount unique[361472]i1 unique[361216]ihandle(i:0,select:v_size,offset:0)
│ │ │ │ │ intAnd unique[361728]i1 unique[361472]i1 1i1
│ │ │ │ │ intEqual register[514]i1 unique[361728]i1 0i1
│ │ │ │ │ assembly += "ADD \(Rmr16),\(Reg16)"
│ │ │ │ │ 
│ │ │ │ └ context 3@0 [xxxxxx00:xxxxxxxx:xxxx00xx:xxxxxxxx] instruction 1@0 [00000001:xxxxxxxx:xxxxxxxx:xxxxxxxx]
│ │ │ │   // 2@2
│ │ │ │   // lockable.sinc:196 0
│ │ │ │   case lockx && unlock && m16 && Reg16:
│ │ │ │   build 3i4
│ │ │ │   build 0i4
│ │ │ │   build 2i4
│ │ │ │   intCarry register[512]i1 handle(i:2,select:space,offset:0)[handle(i:2,select:v_offset,offset:0)]ihandle(i:2,select:v_size,offset:0) handle(i:3,select:space,offset:0)[handle(i:3,select:v_offset,offset:0)]ihandle(i:3,select:v_size,offset:0)
│ │ │ │   intScarry register[523]i1 handle(i:2,select:space,offset:0)[handle(i:2,select:v_offset,offset:0)]ihandle(i:2,select:v_size,offset:0) handle(i:3,select:space,offset:0)[handle(i:3,select:v_offset,offset:0)]ihandle(i:3,select:v_size,offset:0)
│ │ │ │   intAdd handle(i:2,select:space,offset:0)[handle(i:2,select:v_offset,offset:0)]ihandle(i:2,select:v_size,offset:0) handle(i:2,select:space,offset:0)[handle(i:2,select:v_offset,offset:0)]ihandle(i:2,select:v_size,offset:0) handle(i:3,select:space,offset:0)[handle(i:3,select:v_offset,offset:0)]ihandle(i:3,select:v_size,offset:0)
│ │ │ │   intSless register[519]i1 handle(i:2,select:space,offset:0)[handle(i:2,select:v_offset,offset:0)]ihandle(i:2,select:v_size,offset:0) 0ihandle(i:2,select:v_size,offset:0)
│ │ │ │   intEqual register[518]i1 handle(i:2,select:space,offset:0)[handle(i:2,select:v_offset,offset:0)]ihandle(i:2,select:v_size,offset:0) 0ihandle(i:2,select:v_size,offset:0)
│ │ │ │   intAnd unique[361216]ihandle(i:2,select:v_size,offset:0) handle(i:2,select:space,offset:0)[handle(i:2,select:v_offset,offset:0)]ihandle(i:2,select:v_size,offset:0) 255ihandle(i:2,select:v_size,offset:0)
│ │ │ │   popcount unique[361472]i1 unique[361216]ihandle(i:2,select:v_size,offset:0)
│ │ │ │   intAnd unique[361728]i1 unique[361472]i1 1i1
│ │ │ │   intEqual register[514]i1 unique[361728]i1 0i1
│ │ │ │   build 1i4
│ │ │ │   assembly += "ADD\(lockx) \(m16),\(Reg16)"
│ │ │ │   
│ │ │ │ 
│ │ │ ├ terminal
│ │ │ │ ├ context 4@0 [0xxx10xx:xxxxxxxx:xxxxxxxx:xxxxxx0x]
│ │ │ │ │ // 0@1
│ │ │ │ │ // ia.sinc:2383 0
│ │ │ │ │ case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(1)], i: 0, mask: 201326592, shift: 26)) && instruction:
│ │ │ │ │ build 0i4
│ │ │ │ │ assembly += "\(instruction)"
│ │ │ │ │ 
│ │ │ │ ├ context 4@0 [xxxxxx01:xxxxxxxx:xxxx00xx:xxxxxxx0] instruction 2@0 [00000001:11xxxxxx:xxxxxxxx:xxxxxxxx]
│ │ │ │ │ // 2@1
│ │ │ │ │ // ia.sinc:2582 0
│ │ │ │ │ case Rmr32 && check_Rmr32_dest && Reg32:
│ │ │ │ │ build 2i4
│ │ │ │ │ build 0i4
│ │ │ │ │ intCarry register[512]i1 handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0) handle(i:2,select:space,offset:0)[handle(i:2,select:v_offset,offset:0)]ihandle(i:2,select:v_size,offset:0)
│ │ │ │ │ intScarry register[523]i1 handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0) handle(i:2,select:space,offset:0)[handle(i:2,select:v_offset,offset:0)]ihandle(i:2,select:v_size,offset:0)
│ │ │ │ │ intAdd handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0) handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0) handle(i:2,select:space,offset:0)[handle(i:2,select:v_offset,offset:0)]ihandle(i:2,select:v_size,offset:0)
│ │ │ │ │ build 1i4
│ │ │ │ │ intSless register[519]i1 handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0) 0ihandle(i:0,select:v_size,offset:0)
│ │ │ │ │ intEqual register[518]i1 handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0) 0ihandle(i:0,select:v_size,offset:0)
│ │ │ │ │ intAnd unique[361216]ihandle(i:0,select:v_size,offset:0) handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0) 255ihandle(i:0,select:v_size,offset:0)
│ │ │ │ │ popcount unique[361472]i1 unique[361216]ihandle(i:0,select:v_size,offset:0)
│ │ │ │ │ intAnd unique[361728]i1 unique[361472]i1 1i1
│ │ │ │ │ intEqual register[514]i1 unique[361728]i1 0i1
│ │ │ │ │ assembly += "ADD \(Rmr32),\(Reg32)"
│ │ │ │ │ 
│ │ │ │ └ context 3@0 [xxxxxx01:xxxxxxxx:xxxx00xx:xxxxxxxx] instruction 1@0 [00000001:xxxxxxxx:xxxxxxxx:xxxxxxxx]
│ │ │ │   // 2@2
│ │ │ │   // lockable.sinc:206 0
│ │ │ │   case lockx && unlock && m32 && Reg32:
│ │ │ │   build 3i4
│ │ │ │   build 0i4
│ │ │ │   build 2i4
│ │ │ │   intCarry register[512]i1 handle(i:2,select:space,offset:0)[handle(i:2,select:v_offset,offset:0)]ihandle(i:2,select:v_size,offset:0) handle(i:3,select:space,offset:0)[handle(i:3,select:v_offset,offset:0)]ihandle(i:3,select:v_size,offset:0)
│ │ │ │   intScarry register[523]i1 handle(i:2,select:space,offset:0)[handle(i:2,select:v_offset,offset:0)]ihandle(i:2,select:v_size,offset:0) handle(i:3,select:space,offset:0)[handle(i:3,select:v_offset,offset:0)]ihandle(i:3,select:v_size,offset:0)
│ │ │ │   intAdd handle(i:2,select:space,offset:0)[handle(i:2,select:v_offset,offset:0)]ihandle(i:2,select:v_size,offset:0) handle(i:2,select:space,offset:0)[handle(i:2,select:v_offset,offset:0)]ihandle(i:2,select:v_size,offset:0) handle(i:3,select:space,offset:0)[handle(i:3,select:v_offset,offset:0)]ihandle(i:3,select:v_size,offset:0)
│ │ │ │   intSless register[519]i1 handle(i:2,select:space,offset:0)[handle(i:2,select:v_offset,offset:0)]ihandle(i:2,select:v_size,offset:0) 0ihandle(i:2,select:v_size,offset:0)
│ │ │ │   intEqual register[518]i1 handle(i:2,select:space,offset:0)[handle(i:2,select:v_offset,offset:0)]ihandle(i:2,select:v_size,offset:0) 0ihandle(i:2,select:v_size,offset:0)
│ │ │ │   intAnd unique[361216]ihandle(i:2,select:v_size,offset:0) handle(i:2,select:space,offset:0)[handle(i:2,select:v_offset,offset:0)]ihandle(i:2,select:v_size,offset:0) 255ihandle(i:2,select:v_size,offset:0)
│ │ │ │   popcount unique[361472]i1 unique[361216]ihandle(i:2,select:v_size,offset:0)
│ │ │ │   intAnd unique[361728]i1 unique[361472]i1 1i1
│ │ │ │   intEqual register[514]i1 unique[361728]i1 0i1
│ │ │ │   build 1i4
│ │ │ │   assembly += "ADD\(lockx) \(m32),\(Reg32)"
│ │ │ │   
│ │ │ │ 
│ │ │ ├ context[0..1]
│ │ │ │ ├ terminal
│ │ │ │ │ └ context 4@0 [0xxx10xx:xxxxxxxx:xxxxxxxx:xxxxxx0x]
│ │ │ │ │   // 0@1
│ │ │ │ │   // ia.sinc:2383 0
│ │ │ │ │   case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(1)], i: 0, mask: 201326592, shift: 26)) && instruction:
│ │ │ │ │   build 0i4
│ │ │ │ │   assembly += "\(instruction)"
│ │ │ │ │   
│ │ │ │ │ 
│ │ │ │ └ terminal
│ │ │ │   ├ context 4@0 [1xxxxx10:xxxxxxxx:xxxx00xx:xxxxxxx0] instruction 2@0 [00000001:11xxxxxx:xxxxxxxx:xxxxxxxx]
│ │ │ │   │ // 2@1
│ │ │ │   │ // ia.sinc:2584 0
│ │ │ │   │ case Rmr64 && Reg64:
│ │ │ │   │ build 1i4
│ │ │ │   │ build 0i4
│ │ │ │   │ intCarry register[512]i1 handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0) handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0)
│ │ │ │   │ intScarry register[523]i1 handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0) handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0)
│ │ │ │   │ intAdd handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0) handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0) handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0)
│ │ │ │   │ intSless register[519]i1 handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0) 0ihandle(i:0,select:v_size,offset:0)
│ │ │ │   │ intEqual register[518]i1 handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0) 0ihandle(i:0,select:v_size,offset:0)
│ │ │ │   │ intAnd unique[361216]ihandle(i:0,select:v_size,offset:0) handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0) 255ihandle(i:0,select:v_size,offset:0)
│ │ │ │   │ popcount unique[361472]i1 unique[361216]ihandle(i:0,select:v_size,offset:0)
│ │ │ │   │ intAnd unique[361728]i1 unique[361472]i1 1i1
│ │ │ │   │ intEqual register[514]i1 unique[361728]i1 0i1
│ │ │ │   │ assembly += "ADD \(Rmr64),\(Reg64)"
│ │ │ │   │ 
│ │ │ │   └ context 3@0 [1xxxxx10:xxxxxxxx:xxxx00xx:xxxxxxxx] instruction 1@0 [00000001:xxxxxxxx:xxxxxxxx:xxxxxxxx]
│ │ │ │     // 2@2
│ │ │ │     // lockable.sinc:217 0
│ │ │ │     case lockx && unlock && m64 && Reg64:
│ │ │ │     build 3i4
│ │ │ │     build 0i4
│ │ │ │     build 2i4
│ │ │ │     intCarry register[512]i1 handle(i:2,select:space,offset:0)[handle(i:2,select:v_offset,offset:0)]ihandle(i:2,select:v_size,offset:0) handle(i:3,select:space,offset:0)[handle(i:3,select:v_offset,offset:0)]ihandle(i:3,select:v_size,offset:0)
│ │ │ │     intScarry register[523]i1 handle(i:2,select:space,offset:0)[handle(i:2,select:v_offset,offset:0)]ihandle(i:2,select:v_size,offset:0) handle(i:3,select:space,offset:0)[handle(i:3,select:v_offset,offset:0)]ihandle(i:3,select:v_size,offset:0)
│ │ │ │     intAdd handle(i:2,select:space,offset:0)[handle(i:2,select:v_offset,offset:0)]ihandle(i:2,select:v_size,offset:0) handle(i:2,select:space,offset:0)[handle(i:2,select:v_offset,offset:0)]ihandle(i:2,select:v_size,offset:0) handle(i:3,select:space,offset:0)[handle(i:3,select:v_offset,offset:0)]ihandle(i:3,select:v_size,offset:0)
│ │ │ │     intSless register[519]i1 handle(i:2,select:space,offset:0)[handle(i:2,select:v_offset,offset:0)]ihandle(i:2,select:v_size,offset:0) 0ihandle(i:2,select:v_size,offset:0)
│ │ │ │     intEqual register[518]i1 handle(i:2,select:space,offset:0)[handle(i:2,select:v_offset,offset:0)]ihandle(i:2,select:v_size,offset:0) 0ihandle(i:2,select:v_size,offset:0)
│ │ │ │     intAnd unique[361216]ihandle(i:2,select:v_size,offset:0) handle(i:2,select:space,offset:0)[handle(i:2,select:v_offset,offset:0)]ihandle(i:2,select:v_size,offset:0) 255ihandle(i:2,select:v_size,offset:0)
│ │ │ │     popcount unique[361472]i1 unique[361216]ihandle(i:2,select:v_size,offset:0)
│ │ │ │     intAnd unique[361728]i1 unique[361472]i1 1i1
│ │ │ │     intEqual register[514]i1 unique[361728]i1 0i1
│ │ │ │     build 1i4
│ │ │ │     assembly += "ADD\(lockx) \(m64),\(Reg64)"
│ │ │ │     
│ │ │ │   
│ │ │ │ 
│ │ │ └ terminal
│ │ │   └ context 4@0 [0xxx10xx:xxxxxxxx:xxxxxxxx:xxxxxx0x]
│ │ │     // 0@1
│ │ │     // ia.sinc:2383 0
│ │ │     case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(1)], i: 0, mask: 201326592, shift: 26)) && instruction:
│ │ │     build 0i4
│ │ │     assembly += "\(instruction)"
│ │ │     
│ │ │   
│ │ │ 
│ │ ├ context[23..24]
│ │ │ ├ terminal
│ │ │ │ ├ context 4@0 [0xxx10xx:xxxxxxxx:xxxxxxxx:xxxxxx0x]
│ │ │ │ │ // 0@1
│ │ │ │ │ // ia.sinc:2383 0
│ │ │ │ │ case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(1)], i: 0, mask: 201326592, shift: 26)) && instruction:
│ │ │ │ │ build 0i4
│ │ │ │ │ assembly += "\(instruction)"
│ │ │ │ │ 
│ │ │ │ └ context 4@1 [xxxx001x:xxxx01x0:xxxxxxx0:00010xxx] instruction 1@0 [00000001:xxxxxxxx:xxxxxxxx:xxxxxxxx]
│ │ │ │   // 2@1
│ │ │ │   // avx.sinc:1826 0
│ │ │ │   case rexWprefix && vexVVVV_XmmReg && XmmReg1 && ZmmReg1 && XmmReg2_m128:
│ │ │ │   build 3i4
│ │ │ │   build 4i4
│ │ │ │   build 2i4
│ │ │ │   callother unique[1880064]i16 350i4 handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0) handle(i:4,select:space,offset:0)[handle(i:4,select:v_offset,offset:0)]ihandle(i:4,select:v_size,offset:0)
│ │ │ │   intZext handle(i:3,select:space,offset:0)[handle(i:3,select:v_offset,offset:0)]ihandle(i:3,select:v_size,offset:0) unique[1880064]i16
│ │ │ │   assembly += "VPHADDW \(XmmReg1), \(vexVVVV_XmmReg), \(XmmReg2_m128)"
│ │ │ │   
│ │ │ │ 
│ │ │ └ context[36..37]
│ │ │   ├ terminal
│ │ │   │ ├ context 4@0 [0xxx10xx:xxxxxxxx:xxxxxxxx:xxxxxx0x]
│ │ │   │ │ // 0@1
│ │ │   │ │ // ia.sinc:2383 0
│ │ │   │ │ case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(1)], i: 0, mask: 201326592, shift: 26)) && instruction:
│ │ │   │ │ build 0i4
│ │ │   │ │ assembly += "\(instruction)"
│ │ │   │ │ 
│ │ │   │ └ context 4@1 [xxxx001x:xxxx01x1:xxxxxxx0:00010xxx] instruction 1@0 [00000001:xxxxxxxx:xxxxxxxx:xxxxxxxx]
│ │ │   │   // 2@1
│ │ │   │   // avx2.sinc:255 0
│ │ │   │   case rexWprefix && vexVVVV_YmmReg && YmmReg1 && ZmmReg1 && YmmReg2_m256:
│ │ │   │   build 3i4
│ │ │   │   build 4i4
│ │ │   │   build 2i4
│ │ │   │   callother unique[2100480]i32 491i4 handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0) handle(i:4,select:space,offset:0)[handle(i:4,select:v_offset,offset:0)]ihandle(i:4,select:v_size,offset:0)
│ │ │   │   intZext handle(i:3,select:space,offset:0)[handle(i:3,select:v_offset,offset:0)]ihandle(i:3,select:v_size,offset:0) unique[2100480]i32
│ │ │   │   assembly += "VPHADDW \(YmmReg1), \(vexVVVV_YmmReg), \(YmmReg2_m256)"
│ │ │   │   
│ │ │   │ 
│ │ │   └ terminal
│ │ │     ├ context 4@0 [0xxx10xx:xxxxxxxx:xxxxxxxx:xxxxxx0x]
│ │ │     │ // 0@1
│ │ │     │ // ia.sinc:2383 0
│ │ │     │ case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(1)], i: 0, mask: 201326592, shift: 26)) && instruction:
│ │ │     │ build 0i4
│ │ │     │ assembly += "\(instruction)"
│ │ │     │ 
│ │ │     └ context 4@1 [xxxx0011:xxxx01x1:xxxxxxx0:00011xxx] instruction 1@0 [00000001:xxxxxxxx:xxxxxxxx:xxxxxxxx]
│ │ │       // 2@1
│ │ │       // avx2.sinc:1107 0
│ │ │       case YmmReg1 && ZmmReg1 && YmmReg2_m256 && imm8:
│ │ │       build 1i4
│ │ │       build 2i4
│ │ │       build 0i4
│ │ │       callother unique[2168064]i32 568i4 handle(i:2,select:space,offset:0)[handle(i:2,select:v_offset,offset:0)]ihandle(i:2,select:v_size,offset:0) handle(i:3,select:space,offset:0)[handle(i:3,select:v_offset,offset:0)]i1
│ │ │       intZext handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0) unique[2168064]i32
│ │ │       assembly += "VPERMPD \(YmmReg1), \(YmmReg2_m256), \(imm8)"
│ │ │       
│ │ │     
│ │ │   
│ │ │ 
│ │ ├ context[23..24]
│ │ │ ├ terminal
│ │ │ │ ├ context 4@0 [0xxx10xx:xxxxxxxx:xxxxxxxx:xxxxxx0x]
│ │ │ │ │ // 0@1
│ │ │ │ │ // ia.sinc:2383 0
│ │ │ │ │ case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(1)], i: 0, mask: 201326592, shift: 26)) && instruction:
│ │ │ │ │ build 0i4
│ │ │ │ │ assembly += "\(instruction)"
│ │ │ │ │ 
│ │ │ │ └ context 4@1 [xxxx0011:xxxx1010:xxxxxxx0:00011xxx] instruction 1@0 [00000001:xxxxxxxx:xxxxxxxx:xxxxxxxx]
│ │ │ │   // 2@1
│ │ │ │   // avx512.sinc:11365 0
│ │ │ │   case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(0)], i: 1, mask: 1048576, shift: 20)) && context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(0)], i: 1, mask: 983040, shift: 16)) && ZmmReg1 && ZmmOpMask64 && ZmmReg2_m512_m64bcst && imm8:
│ │ │ │   build 2i4
│ │ │ │   build 0i4
│ │ │ │   callother register[2300]i64 1251i4 handle(i:2,select:space,offset:0)[handle(i:2,select:v_offset,offset:0)]ihandle(i:2,select:v_size,offset:0) handle(i:3,select:space,offset:0)[handle(i:3,select:v_offset,offset:0)]i1
│ │ │ │   copy register[2364]i64 handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0)
│ │ │ │   build 1i4
│ │ │ │   copy handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0) register[2300]i64
│ │ │ │   assembly += "VPERMPD \(ZmmReg1)\(ZmmOpMask64), \(ZmmReg2_m512_m64bcst), \(imm8)"
│ │ │ │   
│ │ │ │ 
│ │ │ └ terminal
│ │ │   ├ context 4@0 [0xxx10xx:xxxxxxxx:xxxxxxxx:xxxxxx0x]
│ │ │   │ // 0@1
│ │ │   │ // ia.sinc:2383 0
│ │ │   │ case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(1)], i: 0, mask: 201326592, shift: 26)) && instruction:
│ │ │   │ build 0i4
│ │ │   │ assembly += "\(instruction)"
│ │ │   │ 
│ │ │   └ context 4@1 [xxxx0011:xxxx10x1:xxxxxxx0:00011xxx] instruction 1@0 [00000001:xxxxxxxx:xxxxxxxx:xxxxxxxx]
│ │ │     // 2@1
│ │ │     // avx512.sinc:11354 0
│ │ │     case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(0)], i: 1, mask: 1048576, shift: 20)) && context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(0)], i: 1, mask: 983040, shift: 16)) && YmmReg1 && ZmmReg1 && YmmOpMask64 && YmmReg2_m256_m64bcst && imm8:
│ │ │     build 1i4
│ │ │     build 3i4
│ │ │     build 0i4
│ │ │     callother register[2300]i32 1250i4 handle(i:3,select:space,offset:0)[handle(i:3,select:v_offset,offset:0)]ihandle(i:3,select:v_size,offset:0) handle(i:4,select:space,offset:0)[handle(i:4,select:v_offset,offset:0)]i1
│ │ │     copy register[2364]i32 handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0)
│ │ │     build 2i4
│ │ │     intZext handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0) register[2300]i32
│ │ │     assembly += "VPERMPD \(YmmReg1)\(YmmOpMask64), \(YmmReg2_m256_m64bcst), \(imm8)"
│ │ │     
│ │ │   
│ │ │ 
│ │ └ terminal
│ │   └ context 4@0 [0xxx10xx:xxxxxxxx:xxxxxxxx:xxxxxx0x]
│ │     // 0@1
│ │     // ia.sinc:2383 0
│ │     case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(1)], i: 0, mask: 201326592, shift: 26)) && instruction:
│ │     build 0i4
│ │     assembly += "\(instruction)"
│ │     
│ │   
│ │ 
│ ├ context[21..22]
│ │ ├ terminal
│ │ │ ├ context 4@0 [0xxx10xx:xxxxxxxx:xxxxxxxx:xxxxxx0x]
│ │ │ │ // 0@1
│ │ │ │ // ia.sinc:2383 0
│ │ │ │ case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(1)], i: 0, mask: 201326592, shift: 26)) && instruction:
│ │ │ │ build 0i4
│ │ │ │ assembly += "\(instruction)"
│ │ │ │ 
│ │ │ └ context 2@2 [xxxx00xx:xxxxxxx0:xxxxxxxx:xxxxxxxx] instruction 1@0 [00000010:xxxxxxxx:xxxxxxxx:xxxxxxxx]
│ │ │   // 2@1
│ │ │   // ia.sinc:2586 0
│ │ │   case rm8 && Reg8:
│ │ │   build 0i4
│ │ │   build 1i4
│ │ │   intCarry register[512]i1 handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0) handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0)
│ │ │   intScarry register[523]i1 handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0) handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0)
│ │ │   intAdd handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0) handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0) handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0)
│ │ │   intSless register[519]i1 handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0) 0ihandle(i:1,select:v_size,offset:0)
│ │ │   intEqual register[518]i1 handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0) 0ihandle(i:1,select:v_size,offset:0)
│ │ │   intAnd unique[361216]ihandle(i:1,select:v_size,offset:0) handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0) 255ihandle(i:1,select:v_size,offset:0)
│ │ │   popcount unique[361472]i1 unique[361216]ihandle(i:1,select:v_size,offset:0)
│ │ │   intAnd unique[361728]i1 unique[361472]i1 1i1
│ │ │   intEqual register[514]i1 unique[361728]i1 0i1
│ │ │   assembly += "ADD \(Reg8),\(rm8)"
│ │ │   
│ │ │ 
│ │ └ context[23..24]
│ │   ├ context[36..37]
│ │   │ ├ terminal
│ │   │ │ ├ context 4@0 [0xxx10xx:xxxxxxxx:xxxxxxxx:xxxxxx0x]
│ │   │ │ │ // 0@1
│ │   │ │ │ // ia.sinc:2383 0
│ │   │ │ │ case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(1)], i: 0, mask: 201326592, shift: 26)) && instruction:
│ │   │ │ │ build 0i4
│ │   │ │ │ assembly += "\(instruction)"
│ │   │ │ │ 
│ │   │ │ └ context 4@1 [xxxx001x:xxxx01x0:xxxxxxx0:00010xxx] instruction 1@0 [00000010:xxxxxxxx:xxxxxxxx:xxxxxxxx]
│ │   │ │   // 2@1
│ │   │ │   // avx.sinc:1834 0
│ │   │ │   case rexWprefix && vexVVVV_XmmReg && XmmReg1 && ZmmReg1 && XmmReg2_m128:
│ │   │ │   build 3i4
│ │   │ │   build 4i4
│ │   │ │   build 2i4
│ │   │ │   callother unique[1880832]i16 351i4 handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0) handle(i:4,select:space,offset:0)[handle(i:4,select:v_offset,offset:0)]ihandle(i:4,select:v_size,offset:0)
│ │   │ │   intZext handle(i:3,select:space,offset:0)[handle(i:3,select:v_offset,offset:0)]ihandle(i:3,select:v_size,offset:0) unique[1880832]i16
│ │   │ │   assembly += "VPHADDD \(XmmReg1), \(vexVVVV_XmmReg), \(XmmReg2_m128)"
│ │   │ │   
│ │   │ │ 
│ │   │ └ terminal
│ │   │   ├ context 4@0 [0xxx10xx:xxxxxxxx:xxxxxxxx:xxxxxx0x]
│ │   │   │ // 0@1
│ │   │   │ // ia.sinc:2383 0
│ │   │   │ case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(1)], i: 0, mask: 201326592, shift: 26)) && instruction:
│ │   │   │ build 0i4
│ │   │   │ assembly += "\(instruction)"
│ │   │   │ 
│ │   │   └ context 4@1 [xxxx0010:xxxx01x0:xxxxxxx0:00011xxx] instruction 1@0 [00000010:xxxxxxxx:xxxxxxxx:xxxxxxxx]
│ │   │     // 2@1
│ │   │     // avx2.sinc:916 0
│ │   │     case vexVVVV_XmmReg && XmmReg1 && ZmmReg1 && XmmReg2_m128 && imm8:
│ │   │     build 2i4
│ │   │     build 3i4
│ │   │     build 1i4
│ │   │     callother unique[2160384]i16 565i4 handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0) handle(i:3,select:space,offset:0)[handle(i:3,select:v_offset,offset:0)]ihandle(i:3,select:v_size,offset:0) handle(i:4,select:space,offset:0)[handle(i:4,select:v_offset,offset:0)]i1
│ │   │     intZext handle(i:2,select:space,offset:0)[handle(i:2,select:v_offset,offset:0)]ihandle(i:2,select:v_size,offset:0) unique[2160384]i16
│ │   │     assembly += "VPBLENDD \(XmmReg1), \(vexVVVV_XmmReg), \(XmmReg2_m128), \(imm8)"
│ │   │     
│ │   │   
│ │   │ 
│ │   └ context[36..37]
│ │     ├ terminal
│ │     │ ├ context 4@0 [0xxx10xx:xxxxxxxx:xxxxxxxx:xxxxxx0x]
│ │     │ │ // 0@1
│ │     │ │ // ia.sinc:2383 0
│ │     │ │ case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(1)], i: 0, mask: 201326592, shift: 26)) && instruction:
│ │     │ │ build 0i4
│ │     │ │ assembly += "\(instruction)"
│ │     │ │ 
│ │     │ └ context 4@1 [xxxx001x:xxxx01x1:xxxxxxx0:00010xxx] instruction 1@0 [00000010:xxxxxxxx:xxxxxxxx:xxxxxxxx]
│ │     │   // 2@1
│ │     │   // avx2.sinc:263 0
│ │     │   case rexWprefix && vexVVVV_YmmReg && YmmReg1 && ZmmReg1 && YmmReg2_m256:
│ │     │   build 3i4
│ │     │   build 4i4
│ │     │   build 2i4
│ │     │   callother unique[2101248]i32 492i4 handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0) handle(i:4,select:space,offset:0)[handle(i:4,select:v_offset,offset:0)]ihandle(i:4,select:v_size,offset:0)
│ │     │   intZext handle(i:3,select:space,offset:0)[handle(i:3,select:v_offset,offset:0)]ihandle(i:3,select:v_size,offset:0) unique[2101248]i32
│ │     │   assembly += "VPHADDD \(YmmReg1), \(vexVVVV_YmmReg), \(YmmReg2_m256)"
│ │     │   
│ │     │ 
│ │     └ terminal
│ │       ├ context 4@0 [0xxx10xx:xxxxxxxx:xxxxxxxx:xxxxxx0x]
│ │       │ // 0@1
│ │       │ // ia.sinc:2383 0
│ │       │ case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(1)], i: 0, mask: 201326592, shift: 26)) && instruction:
│ │       │ build 0i4
│ │       │ assembly += "\(instruction)"
│ │       │ 
│ │       └ context 4@1 [xxxx0010:xxxx01x1:xxxxxxx0:00011xxx] instruction 1@0 [00000010:xxxxxxxx:xxxxxxxx:xxxxxxxx]
│ │         // 2@1
│ │         // avx2.sinc:923 0
│ │         case vexVVVV_YmmReg && YmmReg1 && ZmmReg1 && YmmReg2_m256 && imm8:
│ │         build 2i4
│ │         build 3i4
│ │         build 1i4
│ │         callother unique[2161152]i32 565i4 handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0) handle(i:3,select:space,offset:0)[handle(i:3,select:v_offset,offset:0)]ihandle(i:3,select:v_size,offset:0) handle(i:4,select:space,offset:0)[handle(i:4,select:v_offset,offset:0)]i1
│ │         intZext handle(i:2,select:space,offset:0)[handle(i:2,select:v_offset,offset:0)]ihandle(i:2,select:v_size,offset:0) unique[2161152]i32
│ │         assembly += "VPBLENDD \(YmmReg1), \(vexVVVV_YmmReg), \(YmmReg2_m256), \(imm8)"
│ │         
│ │       
│ │     
│ │   
│ │ 
│ ├ context[20..22]
│ │ ├ context[6..8]
│ │ │ ├ terminal
│ │ │ │ ├ context 4@0 [0xxx10xx:xxxxxxxx:xxxxxxxx:xxxxxx0x]
│ │ │ │ │ // 0@1
│ │ │ │ │ // ia.sinc:2383 0
│ │ │ │ │ case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(1)], i: 0, mask: 201326592, shift: 26)) && instruction:
│ │ │ │ │ build 0i4
│ │ │ │ │ assembly += "\(instruction)"
│ │ │ │ │ 
│ │ │ │ └ context 4@0 [xxxxxx00:xxxxxxxx:xxxx00xx:xxxxxxx0] instruction 1@0 [00000011:xxxxxxxx:xxxxxxxx:xxxxxxxx]
│ │ │ │   // 2@1
│ │ │ │   // ia.sinc:2587 0
│ │ │ │   case rm16 && Reg16:
│ │ │ │   build 0i4
│ │ │ │   build 1i4
│ │ │ │   intCarry register[512]i1 handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0) handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0)
│ │ │ │   intScarry register[523]i1 handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0) handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0)
│ │ │ │   intAdd handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0) handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0) handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0)
│ │ │ │   intSless register[519]i1 handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0) 0ihandle(i:1,select:v_size,offset:0)
│ │ │ │   intEqual register[518]i1 handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0) 0ihandle(i:1,select:v_size,offset:0)
│ │ │ │   intAnd unique[361216]ihandle(i:1,select:v_size,offset:0) handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0) 255ihandle(i:1,select:v_size,offset:0)
│ │ │ │   popcount unique[361472]i1 unique[361216]ihandle(i:1,select:v_size,offset:0)
│ │ │ │   intAnd unique[361728]i1 unique[361472]i1 1i1
│ │ │ │   intEqual register[514]i1 unique[361728]i1 0i1
│ │ │ │   assembly += "ADD \(Reg16),\(rm16)"
│ │ │ │   
│ │ │ │ 
│ │ │ ├ terminal
│ │ │ │ ├ context 4@0 [0xxx10xx:xxxxxxxx:xxxxxxxx:xxxxxx0x]
│ │ │ │ │ // 0@1
│ │ │ │ │ // ia.sinc:2383 0
│ │ │ │ │ case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(1)], i: 0, mask: 201326592, shift: 26)) && instruction:
│ │ │ │ │ build 0i4
│ │ │ │ │ assembly += "\(instruction)"
│ │ │ │ │ 
│ │ │ │ └ context 4@0 [xxxxxx01:xxxxxxxx:xxxx00xx:xxxxxxx0] instruction 1@0 [00000011:xxxxxxxx:xxxxxxxx:xxxxxxxx]
│ │ │ │   // 2@1
│ │ │ │   // ia.sinc:2588 0
│ │ │ │   case rm32 && Reg32 && check_Reg32_dest:
│ │ │ │   build 0i4
│ │ │ │   build 1i4
│ │ │ │   intCarry register[512]i1 handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0) handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0)
│ │ │ │   intScarry register[523]i1 handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0) handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0)
│ │ │ │   intAdd handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0) handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0) handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0)
│ │ │ │   build 2i4
│ │ │ │   intSless register[519]i1 handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0) 0ihandle(i:1,select:v_size,offset:0)
│ │ │ │   intEqual register[518]i1 handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0) 0ihandle(i:1,select:v_size,offset:0)
│ │ │ │   intAnd unique[361216]ihandle(i:1,select:v_size,offset:0) handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0) 255ihandle(i:1,select:v_size,offset:0)
│ │ │ │   popcount unique[361472]i1 unique[361216]ihandle(i:1,select:v_size,offset:0)
│ │ │ │   intAnd unique[361728]i1 unique[361472]i1 1i1
│ │ │ │   intEqual register[514]i1 unique[361728]i1 0i1
│ │ │ │   assembly += "ADD \(Reg32),\(rm32)"
│ │ │ │   
│ │ │ │ 
│ │ │ ├ context[0..1]
│ │ │ │ ├ terminal
│ │ │ │ │ └ context 4@0 [0xxx10xx:xxxxxxxx:xxxxxxxx:xxxxxx0x]
│ │ │ │ │   // 0@1
│ │ │ │ │   // ia.sinc:2383 0
│ │ │ │ │   case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(1)], i: 0, mask: 201326592, shift: 26)) && instruction:
│ │ │ │ │   build 0i4
│ │ │ │ │   assembly += "\(instruction)"
│ │ │ │ │   
│ │ │ │ │ 
│ │ │ │ └ terminal
│ │ │ │   └ context 4@0 [1xxxxx10:xxxxxxxx:xxxx00xx:xxxxxxx0] instruction 1@0 [00000011:xxxxxxxx:xxxxxxxx:xxxxxxxx]
│ │ │ │     // 2@1
│ │ │ │     // ia.sinc:2590 0
│ │ │ │     case rm64 && Reg64:
│ │ │ │     build 0i4
│ │ │ │     build 1i4
│ │ │ │     intCarry register[512]i1 handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0) handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0)
│ │ │ │     intScarry register[523]i1 handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0) handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0)
│ │ │ │     intAdd handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0) handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0) handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0)
│ │ │ │     intSless register[519]i1 handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0) 0ihandle(i:1,select:v_size,offset:0)
│ │ │ │     intEqual register[518]i1 handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0) 0ihandle(i:1,select:v_size,offset:0)
│ │ │ │     intAnd unique[361216]ihandle(i:1,select:v_size,offset:0) handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0) 255ihandle(i:1,select:v_size,offset:0)
│ │ │ │     popcount unique[361472]i1 unique[361216]ihandle(i:1,select:v_size,offset:0)
│ │ │ │     intAnd unique[361728]i1 unique[361472]i1 1i1
│ │ │ │     intEqual register[514]i1 unique[361728]i1 0i1
│ │ │ │     assembly += "ADD \(Reg64),\(rm64)"
│ │ │ │     
│ │ │ │   
│ │ │ │ 
│ │ │ └ terminal
│ │ │   └ context 4@0 [0xxx10xx:xxxxxxxx:xxxxxxxx:xxxxxx0x]
│ │ │     // 0@1
│ │ │     // ia.sinc:2383 0
│ │ │     case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(1)], i: 0, mask: 201326592, shift: 26)) && instruction:
│ │ │     build 0i4
│ │ │     assembly += "\(instruction)"
│ │ │     
│ │ │   
│ │ │ 
│ │ ├ context[23..24]
│ │ │ ├ terminal
│ │ │ │ ├ context 4@0 [0xxx10xx:xxxxxxxx:xxxxxxxx:xxxxxx0x]
│ │ │ │ │ // 0@1
│ │ │ │ │ // ia.sinc:2383 0
│ │ │ │ │ case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(1)], i: 0, mask: 201326592, shift: 26)) && instruction:
│ │ │ │ │ build 0i4
│ │ │ │ │ assembly += "\(instruction)"
│ │ │ │ │ 
│ │ │ │ └ context 4@1 [xxxx001x:xxxx01x0:xxxxxxx0:00010xxx] instruction 1@0 [00000011:xxxxxxxx:xxxxxxxx:xxxxxxxx]
│ │ │ │   // 2@1
│ │ │ │   // avx.sinc:1842 0
│ │ │ │   case rexWprefix && vexVVVV_XmmReg && XmmReg1 && ZmmReg1 && XmmReg2_m128:
│ │ │ │   build 3i4
│ │ │ │   build 4i4
│ │ │ │   build 2i4
│ │ │ │   callother unique[1881600]i16 352i4 handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0) handle(i:4,select:space,offset:0)[handle(i:4,select:v_offset,offset:0)]ihandle(i:4,select:v_size,offset:0)
│ │ │ │   intZext handle(i:3,select:space,offset:0)[handle(i:3,select:v_offset,offset:0)]ihandle(i:3,select:v_size,offset:0) unique[1881600]i16
│ │ │ │   assembly += "VPHADDSW \(XmmReg1), \(vexVVVV_XmmReg), \(XmmReg2_m128)"
│ │ │ │   
│ │ │ │ 
│ │ │ └ terminal
│ │ │   ├ context 4@0 [0xxx10xx:xxxxxxxx:xxxxxxxx:xxxxxx0x]
│ │ │   │ // 0@1
│ │ │   │ // ia.sinc:2383 0
│ │ │   │ case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(1)], i: 0, mask: 201326592, shift: 26)) && instruction:
│ │ │   │ build 0i4
│ │ │   │ assembly += "\(instruction)"
│ │ │   │ 
│ │ │   └ context 4@1 [xxxx001x:xxxx01x1:xxxxxxx0:00010xxx] instruction 1@0 [00000011:xxxxxxxx:xxxxxxxx:xxxxxxxx]
│ │ │     // 2@1
│ │ │     // avx2.sinc:271 0
│ │ │     case rexWprefix && vexVVVV_YmmReg && YmmReg1 && ZmmReg1 && YmmReg2_m256:
│ │ │     build 3i4
│ │ │     build 4i4
│ │ │     build 2i4
│ │ │     callother unique[2102016]i32 493i4 handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0) handle(i:4,select:space,offset:0)[handle(i:4,select:v_offset,offset:0)]ihandle(i:4,select:v_size,offset:0)
│ │ │     intZext handle(i:3,select:space,offset:0)[handle(i:3,select:v_offset,offset:0)]ihandle(i:3,select:v_size,offset:0) unique[2102016]i32
│ │ │     assembly += "VPHADDSW \(YmmReg1), \(vexVVVV_YmmReg), \(YmmReg2_m256)"
│ │ │     
│ │ │   
│ │ │ 
│ │ ├ context[15..16]
│ │ │ ├ context[23..24]
│ │ │ │ ├ terminal
│ │ │ │ │ ├ context 4@0 [0xxx10xx:xxxxxxxx:xxxxxxxx:xxxxxx0x]
│ │ │ │ │ │ // 0@1
│ │ │ │ │ │ // ia.sinc:2383 0
│ │ │ │ │ │ case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(1)], i: 0, mask: 201326592, shift: 26)) && instruction:
│ │ │ │ │ │ build 0i4
│ │ │ │ │ │ assembly += "\(instruction)"
│ │ │ │ │ │ 
│ │ │ │ │ ├ context 4@1 [xxxx0010:xxxx1010:xxxxxxx0:00011xxx] instruction 1@0 [00000011:xxxxxxxx:xxxxxxxx:xxxxxxxx]
│ │ │ │ │ │ // 2@1
│ │ │ │ │ │ // avx512.sinc:6307 0
│ │ │ │ │ │ case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(0)], i: 1, mask: 1048576, shift: 20)) && context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(0)], i: 1, mask: 983040, shift: 16)) && evexV5_ZmmReg && ZmmReg1 && ZmmOpMask32 && ZmmReg2_m512_m32bcst && imm8:
│ │ │ │ │ │ build 3i4
│ │ │ │ │ │ build 1i4
│ │ │ │ │ │ callother register[2300]i64 939i4 handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0) handle(i:3,select:space,offset:0)[handle(i:3,select:v_offset,offset:0)]ihandle(i:3,select:v_size,offset:0) handle(i:4,select:space,offset:0)[handle(i:4,select:v_offset,offset:0)]i1
│ │ │ │ │ │ copy register[2364]i64 handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0)
│ │ │ │ │ │ build 2i4
│ │ │ │ │ │ copy handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0) register[2300]i64
│ │ │ │ │ │ assembly += "VALIGND \(ZmmReg1)\(ZmmOpMask32), \(evexV5_ZmmReg), \(ZmmReg2_m512_m32bcst), \(imm8)"
│ │ │ │ │ │ 
│ │ │ │ │ └ context 4@1 [xxxx0010:xxxx10x0:xxxxxxx0:00011xxx] instruction 1@0 [00000011:xxxxxxxx:xxxxxxxx:xxxxxxxx]
│ │ │ │ │   // 2@1
│ │ │ │ │   // avx512.sinc:6265 0
│ │ │ │ │   case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(0)], i: 1, mask: 1048576, shift: 20)) && context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(0)], i: 1, mask: 983040, shift: 16)) && evexV5_XmmReg && XmmReg1 && ZmmReg1 && XmmOpMask32 && XmmReg2_m128_m32bcst && imm8:
│ │ │ │ │   build 2i4
│ │ │ │ │   build 4i4
│ │ │ │ │   build 1i4
│ │ │ │ │   callother register[2300]i16 937i4 handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0) handle(i:4,select:space,offset:0)[handle(i:4,select:v_offset,offset:0)]ihandle(i:4,select:v_size,offset:0) handle(i:5,select:space,offset:0)[handle(i:5,select:v_offset,offset:0)]i1
│ │ │ │ │   copy register[2364]i16 handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0)
│ │ │ │ │   build 3i4
│ │ │ │ │   intZext handle(i:2,select:space,offset:0)[handle(i:2,select:v_offset,offset:0)]ihandle(i:2,select:v_size,offset:0) register[2300]i16
│ │ │ │ │   assembly += "VALIGND \(XmmReg1)\(XmmOpMask32), \(evexV5_XmmReg), \(XmmReg2_m128_m32bcst), \(imm8)"
│ │ │ │ │   
│ │ │ │ │ 
│ │ │ │ └ terminal
│ │ │ │   ├ context 4@0 [0xxx10xx:xxxxxxxx:xxxxxxxx:xxxxxx0x]
│ │ │ │   │ // 0@1
│ │ │ │   │ // ia.sinc:2383 0
│ │ │ │   │ case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(1)], i: 0, mask: 201326592, shift: 26)) && instruction:
│ │ │ │   │ build 0i4
│ │ │ │   │ assembly += "\(instruction)"
│ │ │ │   │ 
│ │ │ │   └ context 4@1 [xxxx0010:xxxx10x1:xxxxxxx0:00011xxx] instruction 1@0 [00000011:xxxxxxxx:xxxxxxxx:xxxxxxxx]
│ │ │ │     // 2@1
│ │ │ │     // avx512.sinc:6286 0
│ │ │ │     case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(0)], i: 1, mask: 1048576, shift: 20)) && context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(0)], i: 1, mask: 983040, shift: 16)) && evexV5_YmmReg && YmmReg1 && ZmmReg1 && YmmOpMask32 && YmmReg2_m256_m32bcst && imm8:
│ │ │ │     build 2i4
│ │ │ │     build 4i4
│ │ │ │     build 1i4
│ │ │ │     callother register[2300]i32 937i4 handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0) handle(i:4,select:space,offset:0)[handle(i:4,select:v_offset,offset:0)]ihandle(i:4,select:v_size,offset:0) handle(i:5,select:space,offset:0)[handle(i:5,select:v_offset,offset:0)]i1
│ │ │ │     copy register[2364]i32 handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0)
│ │ │ │     build 3i4
│ │ │ │     intZext handle(i:2,select:space,offset:0)[handle(i:2,select:v_offset,offset:0)]ihandle(i:2,select:v_size,offset:0) register[2300]i32
│ │ │ │     assembly += "VALIGND \(YmmReg1)\(YmmOpMask32), \(evexV5_YmmReg), \(YmmReg2_m256_m32bcst), \(imm8)"
│ │ │ │     
│ │ │ │   
│ │ │ │ 
│ │ │ └ context[23..24]
│ │ │   ├ terminal
│ │ │   │ ├ context 4@0 [0xxx10xx:xxxxxxxx:xxxxxxxx:xxxxxx0x]
│ │ │   │ │ // 0@1
│ │ │   │ │ // ia.sinc:2383 0
│ │ │   │ │ case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(1)], i: 0, mask: 201326592, shift: 26)) && instruction:
│ │ │   │ │ build 0i4
│ │ │   │ │ assembly += "\(instruction)"
│ │ │   │ │ 
│ │ │   │ ├ context 4@1 [xxxx0011:xxxx1010:xxxxxxx0:00011xxx] instruction 1@0 [00000011:xxxxxxxx:xxxxxxxx:xxxxxxxx]
│ │ │   │ │ // 2@1
│ │ │   │ │ // avx512.sinc:6318 0
│ │ │   │ │ case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(0)], i: 1, mask: 1048576, shift: 20)) && context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(0)], i: 1, mask: 983040, shift: 16)) && evexV5_ZmmReg && ZmmReg1 && ZmmOpMask64 && ZmmReg2_m512_m64bcst && imm8:
│ │ │   │ │ build 3i4
│ │ │   │ │ build 1i4
│ │ │   │ │ callother register[2300]i64 940i4 handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0) handle(i:3,select:space,offset:0)[handle(i:3,select:v_offset,offset:0)]ihandle(i:3,select:v_size,offset:0) handle(i:4,select:space,offset:0)[handle(i:4,select:v_offset,offset:0)]i1
│ │ │   │ │ copy register[2364]i64 handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0)
│ │ │   │ │ build 2i4
│ │ │   │ │ copy handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0) register[2300]i64
│ │ │   │ │ assembly += "VALIGNQ \(ZmmReg1)\(ZmmOpMask64), \(evexV5_ZmmReg), \(ZmmReg2_m512_m64bcst), \(imm8)"
│ │ │   │ │ 
│ │ │   │ └ context 4@1 [xxxx0011:xxxx10x0:xxxxxxx0:00011xxx] instruction 1@0 [00000011:xxxxxxxx:xxxxxxxx:xxxxxxxx]
│ │ │   │   // 2@1
│ │ │   │   // avx512.sinc:6276 0
│ │ │   │   case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(0)], i: 1, mask: 1048576, shift: 20)) && context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(0)], i: 1, mask: 983040, shift: 16)) && evexV5_XmmReg && XmmReg1 && ZmmReg1 && XmmOpMask64 && XmmReg2_m128_m64bcst && imm8:
│ │ │   │   build 2i4
│ │ │   │   build 4i4
│ │ │   │   build 1i4
│ │ │   │   callother register[2300]i16 938i4 handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0) handle(i:4,select:space,offset:0)[handle(i:4,select:v_offset,offset:0)]ihandle(i:4,select:v_size,offset:0) handle(i:5,select:space,offset:0)[handle(i:5,select:v_offset,offset:0)]i1
│ │ │   │   copy register[2364]i16 handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0)
│ │ │   │   build 3i4
│ │ │   │   intZext handle(i:2,select:space,offset:0)[handle(i:2,select:v_offset,offset:0)]ihandle(i:2,select:v_size,offset:0) register[2300]i16
│ │ │   │   assembly += "VALIGNQ \(XmmReg1)\(XmmOpMask64), \(evexV5_XmmReg), \(XmmReg2_m128_m64bcst), \(imm8)"
│ │ │   │   
│ │ │   │ 
│ │ │   └ terminal
│ │ │     ├ context 4@0 [0xxx10xx:xxxxxxxx:xxxxxxxx:xxxxxx0x]
│ │ │     │ // 0@1
│ │ │     │ // ia.sinc:2383 0
│ │ │     │ case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(1)], i: 0, mask: 201326592, shift: 26)) && instruction:
│ │ │     │ build 0i4
│ │ │     │ assembly += "\(instruction)"
│ │ │     │ 
│ │ │     └ context 4@1 [xxxx0011:xxxx10x1:xxxxxxx0:00011xxx] instruction 1@0 [00000011:xxxxxxxx:xxxxxxxx:xxxxxxxx]
│ │ │       // 2@1
│ │ │       // avx512.sinc:6296 0
│ │ │       case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(0)], i: 1, mask: 1048576, shift: 20)) && context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(0)], i: 1, mask: 983040, shift: 16)) && evexV5_YmmReg && YmmReg1 && ZmmReg1 && YmmOpMask64 && YmmReg2_m256_m64bcst && imm8:
│ │ │       build 2i4
│ │ │       build 4i4
│ │ │       build 1i4
│ │ │       callother register[2300]i32 938i4 handle(i:0,select:space,offset:0)[handle(i:0,select:v_offset,offset:0)]ihandle(i:0,select:v_size,offset:0) handle(i:4,select:space,offset:0)[handle(i:4,select:v_offset,offset:0)]ihandle(i:4,select:v_size,offset:0) handle(i:5,select:space,offset:0)[handle(i:5,select:v_offset,offset:0)]i1
│ │ │       copy register[2364]i32 handle(i:1,select:space,offset:0)[handle(i:1,select:v_offset,offset:0)]ihandle(i:1,select:v_size,offset:0)
│ │ │       build 3i4
│ │ │       intZext handle(i:2,select:space,offset:0)[handle(i:2,select:v_offset,offset:0)]ihandle(i:2,select:v_size,offset:0) register[2300]i32
│ │ │       assembly += "VALIGNQ \(YmmReg1)\(YmmOpMask64), \(evexV5_YmmReg), \(YmmReg2_m256_m64bcst), \(imm8)"
│ │ │       
│ │ │     
│ │ │   
│ │ │ 
│ │ └ terminal
│ │   └ context 4@0 [0xxx10xx:xxxxxxxx:xxxxxxxx:xxxxxx0x]
│ │     // 0@1
│ │     // ia.sinc:2383 0
│ │     case context_op(sla2swift.SleighSpec.ContextOp(children: [sla2swift.SleighSpec.PatternExpr.intb(1)], i: 0, mask: 201326592, shift: 26)) && instruction:
│ │     build 0i4
│ │     assembly += "\(instruction)"
│ │