AARCH64 instruction ldpsw handled improperly

[dt-12345]

Describe the bug
The ldpsw instruction loads two consecutive 32-bit values from memory and stores the in the two specified 64-bit registers. The decompiler appears to treat it as loading the lower 32 bits of two consecutive 64-bit values instead.

Expected behavior
Proper handling of ldpsw

Screenshots
Notes: param1->mObjIndex is at offset 0x88 and param1->mIsProcessing is at offset 0x90 (I believe the correct behavior is to load param1 + 0x88 into x10 and param1 + 0x8c into x11)

Environment (please complete the following information):

• OS: Windows 10 Home 22H2
• Java Version: 21.0.4
• Ghidra Version: 11.3
• Ghidra Origin: Official GitHub Release

[dt-12345]

I'm not sure if this is the same thing mentioned in #5791 or not, but that issue has already been closed and this is still present.

[GhidorahRex]

Yes, this is a separate issue. I'll get a fix in.

[GhidorahRex]

Looking at the pcode, line 3044 should be adding 4 instead of 8. Replacing the pcode in AARCH64base.sinc with this should fix it:

--- a/Ghidra/Processors/AARCH64/data/languages/AARCH64base.sinc
+++ b/Ghidra/Processors/AARCH64/data/languages/AARCH64base.sinc
:ldpsw Rt_GPR64, Rt2_GPR64, addrPairIndexed
is b_2531=0b0110100 & (b_24=1 | b_23=1) & b_22=1 & Rt2_GPR64 & addrPairIndexed & Rt_GPR64
{
	local addrval1:8 = sext(*:4 addrPairIndexed);
-	local addrval2:8 = sext(*:4 (addrPairIndexed + 8));
+	local addrval2:8 = sext(*:4 (addrPairIndexed + 4));
	Rt_GPR64 = addrval1;
	Rt2_GPR64 = addrval2;
}