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AARCH64 ldar instruction handled improperly in 32-bit case #8014

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@dt-12345

Description

@dt-12345

Describe the bug
ldar is unconditionally treated as a 64-bit load even when the destination register is a 32-bit register.

This appears to fix it:

--- a/Ghidra/Processors/AARCH64/data/languages/AARCH64base.sinc
+++ b/Ghidra/Processors/AARCH64/data/languages/AARCH64base.sinc
:ldar Rt_GPR32, addrReg
is size.ldstr=2 & b_2429=0x8 & b_23=1 & L=1 & b_21=0 & b_1620=0b11111 & b_15=1 & b_1014=0b11111 & addrReg & Rt_GPR32 & Rt_GPR64
{
-	Rt_GPR64 = *addrReg;
+	Rt_GPR64 = zext(*:4 addrReg);
}

Expected behavior
Proper handling of the instruction

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