Exception while searching for instructions

[patateqbool]

Hi there.

I got this exception while searching for an instruction in the disassembly view.

Exception in ida_idp.IDP_Hooks dispatcher function: SWIG director method error. Error detected when calling 'IDP_Hooks.ev_out_insn'
Traceback (most recent call last):
  File "/home/patate/idapro-7.4/plugins/amie.py", line 354, in ev_out_insn
    return self.arch.output(outctx)
  File "/home/patate/idapro-7.4/plugins/amie.py", line 251, in output
    mne, op = cp_reg.split()
ValueError: not enough values to unpack (expected 2, got 1)

[NeatMonster]

Please try the following patch and report the results:

diff --git a/aarch64.json b/aarch64.json
index 4650820..fafc196 100644
--- a/aarch64.json
+++ b/aarch64.json
@@ -12338,7 +12338,6 @@
         "IC IALLU": ["01", "000", "0111", "0101", "000"],
         "IC IALLUIS": ["01", "000", "0111", "0001", "000"],
         "IC IVAU": ["01", "011", "0111", "0101", "001"],
-        "S1_<op1>_<Cn>_<Cm>_<op2>": ["01", "xxx", "1x11", "xxxx", "xxx"],
         "TLBI ALLE1": ["01", "100", "1000", "0111", "100"],
         "TLBI ALLE1IS": ["01", "100", "1000", "0011", "100"],
         "TLBI ALLE1OS": ["01", "100", "1000", "0001", "100"],
@@ -12792,10 +12791,6 @@
         "long_name": "Address Translate Stage 1 EL3 Write",
         "purpose": "Performs stage 1 address translation as defined for EL3, with permissions as if\nwriting to the given virtual address.\n\nbits [0:63] - Input address for translation. The resulting address can be read\n              from the PAR_EL1. If the address translation instructions are\n              targeting a translation regime that is using AArch32, and so has a\n              VA of only 32 bits, then VA[63:32] is res0."
       },
-      "S1_<op1>_<Cn>_<Cm>_<op2>": {
-        "long_name": "IMPLEMENTATION DEFINED maintenance instructions",
-        "purpose": "This area of the System instruction encoding space is reserved for\nimplementation defined System instructions."
-      },
       "VAAE1": {
         "long_name": "TLB Invalidate by VA, All ASID, EL1",
         "purpose": "Invalidates cached copies of translation table entries from TLBs that meet all\nthe following requirements:\n\n  - The entry is a stage 1 translation table entry, from any level of the\ntranslation table walk.\n  - When EL2 is implemented and enabled in the Security state described by the\ncurrent value of SCR_EL3.NS:\n    - If HCR_EL2.{E2H, TGE} is not {1, 1}, the entry would be used with the\ncurrent VMID and would be required to translate the specified VA using the EL1&0\ntranslation regime.\n    - If HCR_EL2.{E2H, TGE} is {1, 1}, the entry would be required to translate\nthe specified VA using the EL2&0 translation regime.\n  - When EL2 is not implemented or is disabled in the current Security state,\nthe entry would be required to translate the specified VA using the EL1&0\ntranslation regime.\n\nThe invalidation applies to the PE that executes this System instruction.\n\nFor the EL1&0 and EL2&0 translation regimes, the invalidation applies to both\nglobal entries, and non-global entries with any ASID.\n\nTTL, bits [44:47]      - Translation Table Level.\nVA[55:12], bits [0:43] - Bits[55:12] of the virtual address to match."

It would be really helpful if you could specify the faulting instruction/register when opening an issue.