Convert VHDL package to Verilog or SV

[jabate-anova]

I have VHDL package files in my current directory which I'd like to convert to Verilog or SV using hdlConvertor. Is this possible?

As in the notebook example, I'm able to use visit_HdlContext(d) to display a VHDL package:

from hdlConvertor import HdlConvertor
from hdlConvertorAst.to.vhdl.vhdl2008 import ToVhdl2008

TEST_DIR = os.path.join("./")
filenames = [os.path.join(TEST_DIR, "axis_pkg.vhd"), ]
include_dirs = []
c = HdlConvertor()
d = c.parse(filenames, Language.VHDL, include_dirs, hierarchyOnly=False, debug=True)
to_vhdl = ToVhdl2008(sys.stdout) 
to_vhdl.visit_HdlContext(d) 

I see that the hdlConvertorAst.translate module may be able to help me, but I'm not sure how to proceed. If I import VHDL to verilog (from hdlConvertorAst.translate import vhdl_to_verilog), how could I use vhdl_to_verilog.link_module_dec_def(context) with my parsed VHDL?

Any help is appreciated, thanks!

[Nic30]

@jabate-anova

Sorry, I am seeing this issue just now, there are may people asking the same and the response is:

In some cases it is possible but it generic case it is not. It also depends on what you are expecting.
There are construct in VHDL which does not have equivalent in SV.
And there many builtin functions/data types. Translation of many elements does need full implementation of VHDL typesystem, builtins and std library. All this is ridiculous amount of work.

I did several translations of commercial projects. I recommend this:
Use hdlConvertor to parse VHDL AST, and hdlConvertor/hdlConvertorAst to print verilog. There are several translation helpers in
hdlConvertorAst.translate but they are not complete and you will need to implement things which are used in your code.

[poleguy]

This is the same question I was about to ask. I can't find any examples that produce valid verilog starting from even trivial VHDL. Can we produce a working python example from any of the 'cases' that are possible? Just as a starting point? And maybe a trivial working example that uses hdlConvertorAst.translat.vhdl_to_verilog?

[Nic30]

hdlConvertor currently does not perform elaboration. Although there are several non-public projects doing this, there is no public example after nearly 3 years (when this issue was posted). Mentioned projects are not public because whole project is one big hack to deal with Quartus/Vivado stuff and it is often very specific for some codebase.
Thus in order to be useful for others a significant amount of time would be required.

I am not sure if it is helpful, but there is ghdl option for this task see for example https://github.com/enjoy-digital/litex/blob/master/litex/build/vhd2v_converter.py#L202