OS/ThreadX: remove IRQ system state updates for SWI scheduling in SMP port

Commit 13248a2 introduced UPDATE_THREADX_SYSTEM_STATE in the normal
IRQ entry path to track per-core ISR nesting state.

However, the Nuclei RISC-V ThreadX SMP port handles scheduler switching
through the SysTimer SWI path, where ``eclic_msip_handler`` saves thread
context and ``PortThreadSwitch`` selects the next thread. The normal
``irq_entry`` path only dispatches hardware non-vector interrupts through
``JALMNXTI`` and does not need to mark ``_tx_thread_system_state`` as an
ISR nesting counter for the current scheduling model.

Keeping that update can prevent ThreadX preemption checks raised from
interrupt context from requesting a scheduler switch, because
``_tx_thread_system_state`` is non-zero while the IRQ is active. The port
already raises a SysTimer SWI for scheduling and handles that SWI after
the normal interrupt path exits, so there is no need to wait on the
IRQ-maintained system state before switching. Remove the IRQ entry
updates added by 13248a2.

Signed-off-by: Huaqi Fang <578567190@qq.com>

Author: fanghuaqi

OS/ThreadX/ports_smp/nuclei/gcc/interrupt.S

@@ -15,19 +15,6 @@
     csrc CSR_MSTATUS, MSTATUS_MIE
 .endm
 
-/* Update ThreadX SMP per-core ISR nesting state.
- * This macro must be called after SAVE_CONTEXT because it clobbers t0-t2.
- */
-.macro UPDATE_THREADX_SYSTEM_STATE delta
-    la t0, _tx_thread_system_state
-    csrr t1, CSR_MHARTID
-    slli t1, t1, LOG_REGBYTES
-    add t0, t0, t1
-    LOAD t2, 0(t0)
-    addi t2, t2, \delta
-    STORE t2, 0(t0)
-.endm
-
 /**
  * \brief  Macro for context save
  * \details
@@ -215,11 +202,6 @@ irq_entry:
     /* Save the necessary CSR registers */
     SAVE_CSR_CONTEXT
 
-    /* Mark this core as being in a normal IRQ handler.
-     * eclic_msip_handler is the scheduler SWI path and is handled separately.
-     */
-    UPDATE_THREADX_SYSTEM_STATE 1
-
     /* This special CSR read/write operation, which is actually
      * claim the CLIC to find its pending highest ID, if the ID
      * is not 0, then automatically enable the mstatus.MIE, and
@@ -230,11 +212,6 @@ irq_entry:
     /* Critical section with interrupts disabled */
     DISABLE_MIE
 
-    /* All nested IRQ work claimed by JALMNXTI is done; leave ThreadX ISR context
-     * before restoring the interrupted context.
-     */
-    UPDATE_THREADX_SYSTEM_STATE -1
-
     /* Restore the necessary CSR registers */
     RESTORE_CSR_CONTEXT
     /* Restore the caller saving registers (context) */

OS/ThreadX/ports_smp/nuclei/iar/interrupt.S

@@ -5,19 +5,6 @@ DISABLE_MIE MACRO
   csrci CSR_MSTATUS, MSTATUS_MIE
   ENDM
 
-/* Update ThreadX SMP per-core ISR nesting state.
- * This macro must be called after SAVE_CONTEXT because it clobbers t0-t2.
- */
-UPDATE_THREADX_SYSTEM_STATE MACRO delta
-    la t0, _tx_thread_system_state
-    csrr t1, CSR_MHARTID
-    slli t1, t1, LOG_REGBYTES
-    add t0, t0, t1
-    LOAD t2, 0(t0)
-    addi t2, t2, delta
-    STORE t2, 0(t0)
-  ENDM
-
 SAVE_CONTEXT MACRO
 #if defined(ECLIC_HW_CTX_AUTO) && defined(CFG_HAS_ECLICV2)
 #else
@@ -110,7 +97,6 @@ RESTORE_CSR_CONTEXT MACRO
     PUBLIC exc_entry, irq_entry, default_intexc_handler
     PUBLIC Undef_Handler
     EXTERN core_exception_handler
-    EXTERN _tx_thread_system_state
     SECTION `.text`:CODE:NOROOT(2)
     CODE
 
@@ -176,11 +162,6 @@ irq_entry:
     /* Save the necessary CSR registers */
     SAVE_CSR_CONTEXT
 
-    /* Mark this core as being in a normal IRQ handler.
-     * eclic_msip_handler is the scheduler SWI path and is handled separately.
-     */
-    UPDATE_THREADX_SYSTEM_STATE 1
-
     /* This special CSR read/write operation, which is actually
      * claim the CLIC to find its pending highest ID, if the ID
      * is not 0, then automatically enable the mstatus.MIE, and
@@ -191,11 +172,6 @@ irq_entry:
     /* Critical section with interrupts disabled */
     DISABLE_MIE
 
-    /* All nested IRQ work claimed by JALMNXTI is done; leave ThreadX ISR context
-     * before restoring the interrupted context.
-     */
-    UPDATE_THREADX_SYSTEM_STATE -1
-
     /* Restore the necessary CSR registers */
     RESTORE_CSR_CONTEXT
     /* Restore the caller saving registers (context) */