fix: cross-platform build (gate SIMD on x86_64, scope wayland/x11 to linux)

The v0.4.0 tree was implicitly x86_64-only and pulled linux-only display
servers into Windows/macOS builds. Two surgical fixes:

simd_queue.rs:
- Gate the AVX2 + BMI1 implementation of remove_order_by_size_simd on
  cfg(target_arch = "x86_64") and the use of std::arch::x86_64::* with
  it.
- Add a scalar fallback under cfg(not(target_arch = "x86_64")) with the
  same signature (still `unsafe fn` for parity, even though the scalar
  path doesn't require any unsafe behaviour at runtime).
- Validated by single-file rustc on aarch64-unknown-linux-gnu - the
  fallback compiles clean.

Cargo.toml:
- Move eframe's `wayland` / `x11` features to a
  [target.'cfg(target_os = "linux")'.dependencies] block so non-Linux
  builds no longer pull in wayland-scanner / x11-dl. The base entry
  retains `wgpu` and `glow`, and the Linux block adds the X11 / Wayland
  features on top via cargo's feature unification.

Net effect:
- Apple Silicon (aarch64-apple-darwin) and other non-x86_64 targets can
  now compile the engine.
- Windows + macOS x86_64 builds no longer carry the X11/Wayland deps.

Host (x86_64-linux) tree remains clippy-clean (-D warnings) and
fmt-check clean; all 13 lib tests still pass.

Author: OctopusTakopi

Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "binance_l3_est"
-version = "0.4.0"
+version = "0.4.1"
 edition = "2024"
 authors = ["OctopusTakopi"]
 repository = "https://github.com/OctopusTakopi/binance_l3_est"
@@ -9,8 +9,12 @@ license = "MIT"
 keywords = ["order book", "binance", "trading", "hft", "visualization"]
 
 [dependencies]
-eframe = { version = "0.32.0", features = ["wgpu", "glow", "wayland", "x11"] }
+# wayland/x11 features are linux-only and live in the target block below.
+eframe = { version = "0.32.0", features = ["wgpu", "glow"] }
 wgpu = { version = "25.0", features = ["vulkan", "vulkan-portability"] }
+
+[target.'cfg(target_os = "linux")'.dependencies]
+eframe = { version = "0.32.0", features = ["wayland", "x11"] }
 egui = { version = "0.32.0", features = ["default"] }
 jiff = { version = "0.2", features = ["serde"] }
 smallstr = { version = "0.3", features = ["serde", "std"] }

src/engine/simd_queue.rs

@@ -1,3 +1,4 @@
+#[cfg(target_arch = "x86_64")]
 use std::arch::x86_64::*;
 
 pub const NULL_BLOCK: u32 = u32::MAX;
@@ -234,12 +235,22 @@ impl QueuePtrs {
         }
     }
 
+    /// Find an order whose size exactly matches `target_size` and zero it in
+    /// place. Returns `true` if a match was found.
+    ///
+    /// On x86_64 this uses an AVX2 + BMI1 vector compare; on other
+    /// architectures it walks the queue scalarly. The `unsafe` qualifier is
+    /// kept on every target for signature parity (the SIMD path requires
+    /// AVX2/BMI1 at runtime).
+    ///
     /// # Safety
     ///
-    /// The CPU must support the AVX2 + BMI1 target features (this fn is gated by
-    /// `#[target_feature]` and can only be called on hardware where those flags
-    /// are present). The caller is also responsible for not aliasing `pool`
-    /// elsewhere for the duration of the call.
+    /// On x86_64 the CPU must support the AVX2 + BMI1 target features (the fn
+    /// is gated by `#[target_feature]` and can only be called on hardware
+    /// where those flags are present). On all targets the caller is
+    /// responsible for not aliasing `pool` elsewhere for the duration of the
+    /// call.
+    #[cfg(target_arch = "x86_64")]
     #[target_feature(enable = "avx2,bmi1")]
     pub unsafe fn remove_order_by_size_simd(
         &self,
@@ -283,4 +294,36 @@ impl QueuePtrs {
         }
         false
     }
+
+    /// Scalar fallback for non-x86_64 targets. Same contract as the SIMD
+    /// version above.
+    #[cfg(not(target_arch = "x86_64"))]
+    pub unsafe fn remove_order_by_size_simd(
+        &self,
+        pool: &mut GlobalOrderPool,
+        target_size: u64,
+    ) -> bool {
+        let mut curr_block_idx = self.head_block;
+        while curr_block_idx != NULL_BLOCK {
+            let block = pool.get_block_mut(curr_block_idx);
+            for i in 0u32..4 {
+                if curr_block_idx == self.head_block && i < self.head_offset {
+                    continue;
+                }
+                if curr_block_idx == self.tail_block && i >= self.tail_offset {
+                    continue;
+                }
+                let slot = &mut block.sizes[i as usize];
+                if *slot > 0 && *slot == target_size {
+                    *slot = 0;
+                    return true;
+                }
+            }
+            if curr_block_idx == self.tail_block {
+                break;
+            }
+            curr_block_idx = block.next_block_idx;
+        }
+        false
+    }
 }