Skip to content

Commit 9a3048c

Browse files
ZigaMahneZigaMahne
committed
Add initial pack contents
1 parent 960a912 commit 9a3048c

28 files changed

+278763
-1
lines changed

‎.github/workflows/pack.yml‎

Lines changed: 33 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,33 @@
1+
name: Build pack
2+
on:
3+
workflow_dispatch:
4+
pull_request:
5+
push:
6+
branches: [main]
7+
release:
8+
types: [published]
9+
10+
concurrency:
11+
group: ${{ github.workflow }}-${{ github.ref }}
12+
cancel-in-progress: true
13+
14+
jobs:
15+
pack:
16+
name: Generate pack
17+
runs-on: ubuntu-22.04
18+
steps:
19+
- uses: actions/checkout@v4
20+
with:
21+
fetch-depth: 0
22+
23+
- name: Fetch tags
24+
if: github.event_name == 'release'
25+
run: |
26+
git fetch --tags --force
27+
28+
- uses: Open-CMSIS-Pack/gen-pack-action@main
29+
with:
30+
doxygen-version: none
31+
packchk-version: 1.4.1
32+
gen-pack-script: ./gen_pack.sh
33+
gen-pack-output: ./output

‎.gitignore‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,3 @@
1+
# Pack build files
2+
/build/
3+
/output/

‎CMSIS/Debug/STM32F205_207_215_217.dbgconf‎

Lines changed: 47 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,47 @@
1+
// File: STM32F205_207_215_217.dbgconf
2+
// Version: 1.0.0
3+
// Note: refer to STM32F205xx STM32F207xx STM32F215xx STM32F217xx Reference manual (RM0033)
4+
// refer to STM32F20x, STM32F21x datasheets
5+
6+
// <<< Use Configuration Wizard in Context Menu >>>
7+
8+
// <h> Debug MCU configuration register (DBGMCU_CR)
9+
// <o.2> DBG_STANDBY <i> Debug standby mode
10+
// <o.1> DBG_STOP <i> Debug stop mode
11+
// <o.0> DBG_SLEEP <i> Debug sleep mode
12+
// </h>
13+
DbgMCU_CR = 0x00000007;
14+
15+
// <h> Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)
16+
// <i> Reserved bits must be kept at reset value
17+
// <o.26> DBG_CAN2_STOP <i> Debug CAN2 stopped when core is halted
18+
// <o.25> DBG_CAN1_STOP <i> Debug CAN2 stopped when core is halted
19+
// <o.23> DBG_I2C3_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
20+
// <o.22> DBG_I2C2_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
21+
// <o.21> DBG_I2C1_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
22+
// <o.12> DBG_IWDG_STOP <i> Debug independent watchdog stopped when core is halted
23+
// <o.11> DBG_WWDG_STOP <i> Debug window watchdog stopped when core is halted
24+
// <o.10> DBG_RTC_STOP <i> RTC stopped when core is halted
25+
// <o.8> DBG_TIM14_STOP <i> TIM14 counter stopped when core is halted
26+
// <o.7> DBG_TIM13_STOP <i> TIM13 counter stopped when core is halted
27+
// <o.6> DBG_TIM12_STOP <i> TIM12 counter stopped when core is halted
28+
// <o.5> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
29+
// <o.4> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
30+
// <o.3> DBG_TIM5_STOP <i> TIM5 counter stopped when core is halted
31+
// <o.2> DBG_TIM4_STOP <i> TIM4 counter stopped when core is halted
32+
// <o.1> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
33+
// <o.0> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
34+
// </h>
35+
DbgMCU_APB1_Fz = 0x00000000;
36+
37+
// <h> Debug MCU APB2 freeze register (DBGMCU_APB2_FZ)
38+
// <i> Reserved bits must be kept at reset value
39+
// <o.18> DBG_TIM11_STOP <i> TIM11 counter stopped when core is halted
40+
// <o.17> DBG_TIM10_STOP <i> TIM10 counter stopped when core is halted
41+
// <o.16> DBG_TIM9_STOP <i> TIM9 counter stopped when core is halted
42+
// <o.1> DBG_TIM8_STOP <i> TIM8 counter stopped when core is halted
43+
// <o.0> DBG_TIM1_STOP <i> TIM1 counter stopped when core is halted
44+
// </h>
45+
DbgMCU_APB2_Fz = 0x00000000;
46+
47+
// <<< end of configuration section >>>

‎CMSIS/Debug/STM32F205_207_215_217_DBGMCU.ini‎

Lines changed: 156 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,156 @@
1+
// File: STM32F205_207_215_217_DBGMCU.ini
2+
// Version: 1.0.0
3+
// Note: refer to STM32F205xx STM32F207xx STM32F215xx STM32F217xx Reference manual (RM0033)
4+
// refer to STM32F20x, STM32F21x datasheets
5+
6+
7+
/* variable to hold register values */
8+
define unsigned long DbgMCU_CR;
9+
define unsigned long DbgMCU_APB1_Fz;
10+
define unsigned long DbgMCU_APB2_Fz;
11+
12+
13+
14+
// <<< Use Configuration Wizard in Context Menu >>>
15+
16+
// <h> Debug MCU configuration register (DBGMCU_CR)
17+
// <i> Reserved bits must be kept at reset value
18+
// <o.6..7> TRACE_MODE <i> Trace mode
19+
// <0=> Asynchronous
20+
// <1=> Synchronous: TRACEDATA Size 1
21+
// <2=> Synchronous: TRACEDATA Size 2
22+
// <3=> Synchronous: TRACEDATA Size 4
23+
// <o.5> TRACE_IOEN <i> Trace I/O enable
24+
// <o.2> DBG_STANDBY <i> Debug standby mode
25+
// <o.1> DBG_STOP <i> Debug stop mode
26+
// <o.0> DBG_SLEEP <i> Debug sleep mode
27+
// </h>
28+
DbgMCU_CR = 0x00000007;
29+
30+
// <h> Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)
31+
// <i> Reserved bits must be kept at reset value
32+
// <o.26> DBG_CAN2_STOP <i> Debug CAN2 stopped when core is halted
33+
// <o.25> DBG_CAN1_STOP <i> Debug CAN2 stopped when core is halted
34+
// <o.23> DBG_I2C3_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
35+
// <o.22> DBG_I2C2_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
36+
// <o.21> DBG_I2C1_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
37+
// <o.12> DBG_IWDG_STOP <i> Debug independent watchdog stopped when core is halted
38+
// <o.11> DBG_WWDG_STOP <i> Debug window watchdog stopped when core is halted
39+
// <o.10> DBG_RTC_STOP <i> RTC stopped when core is halted
40+
// <o.8> DBG_TIM14_STOP <i> TIM14 counter stopped when core is halted
41+
// <o.7> DBG_TIM13_STOP <i> TIM13 counter stopped when core is halted
42+
// <o.6> DBG_TIM12_STOP <i> TIM12 counter stopped when core is halted
43+
// <o.5> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
44+
// <o.4> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
45+
// <o.3> DBG_TIM5_STOP <i> TIM5 counter stopped when core is halted
46+
// <o.2> DBG_TIM4_STOP <i> TIM4 counter stopped when core is halted
47+
// <o.1> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
48+
// <o.0> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
49+
// </h>
50+
DbgMCU_APB1_Fz = 0x00000000;
51+
52+
// <h> Debug MCU APB2 freeze register (DBGMCU_APB2_FZ)
53+
// <i> Reserved bits must be kept at reset value
54+
// <o.18> DBG_TIM11_STOP <i> TIM11 counter stopped when core is halted
55+
// <o.17> DBG_TIM10_STOP <i> TIM10 counter stopped when core is halted
56+
// <o.16> DBG_TIM9_STOP <i> TIM9 counter stopped when core is halted
57+
// <o.1> DBG_TIM8_STOP <i> TIM8 counter stopped when core is halted
58+
// <o.0> DBG_TIM1_STOP <i> TIM1 counter stopped when core is halted
59+
// </h>
60+
DbgMCU_APB2_Fz = 0x00000000;
61+
62+
// <h> TPIU Pin Routing
63+
// <i> TRACECLK: Pin PE2
64+
// <i> TRACED[0]: Pin PE3
65+
// <i> TRACED[1]: Pin PE4
66+
// <i> TRACED[2]: Pin PE5
67+
// <i> TRACED[3]: Pin PE6
68+
// </h>
69+
70+
// <<< end of configuration section >>>
71+
72+
73+
/*----------------------------------------------------------------------------
74+
Setup_TracePins() configure the used trace pins
75+
*----------------------------------------------------------------------------*/
76+
FUNC void Setup_TracePins (unsigned char trace_mode) {
77+
78+
if (trace_mode == 0) { /* asynchronous mode */
79+
/* configure SWO (PB3) */
80+
_WDWORD(0x40023830, ( _RDWORD(0x40023830) | 0x00000002) ); // RCC_AHB1ENR: IO port B clock enable
81+
_WDWORD(0x40020400, ((_RDWORD(0x40020400) & ~0x000000C0) | 0x00000080) ); // GPIOx_MODER: Set Mode (Alternate Function)
82+
_WDWORD(0x40020408, ((_RDWORD(0x40020408) ) | 0x000000C0) ); // GPIOx_OSPEEDR: Set Speed (Very High Speed)
83+
_WDWORD(0x4002040C, ((_RDWORD(0x4002040C) & ~0x000000C0) ) ); // GPIOx_PUPDR: Set I/O to no pull-up/pull-down
84+
_WDWORD(0x40020420, ((_RDWORD(0x40020420) & ~0x0000F000) ) ); // GPIOx_AFRL: Alternate Function to AF0
85+
}
86+
else { /* synchronous mode */
87+
/* configure TRACECLK (PE2) */
88+
_WDWORD(0x40023830, ( _RDWORD(0x40023830) | 0x00000010) ); // RCC_AHB1ENR: IO port E clock enable
89+
_WDWORD(0x40021000, ((_RDWORD(0x40021000) & ~0x00000030) | 0x00000020) ); // GPIOx_MODER: Set Mode (Alternate Function)
90+
_WDWORD(0x40021008, ((_RDWORD(0x40021008) ) | 0x00000030) ); // GPIOx_OSPEEDR: Set Speed (Very High Speed)
91+
_WDWORD(0x4002100C, ((_RDWORD(0x4002100C) & ~0x00000030) ) ); // GPIOx_PUPDR: Set I/O to no pull-up/pull-down
92+
_WDWORD(0x40021020, ((_RDWORD(0x40021020) & ~0x00000F00) ) ); // GPIOx_AFRL: Alternate Function to AF0
93+
94+
switch (trace_mode) {
95+
case 3: /* TRACEDATA[3..2] */
96+
/* configure TRACED3 */
97+
/* configure TRACED3 (PE6) */
98+
// _WDWORD(0x40023830, ( _RDWORD(0x40023830) | 0x00000010) ); // RCC_AHB1ENR: IO port E clock enable
99+
_WDWORD(0x40021000, ((_RDWORD(0x40021000) & ~0x00003000) | 0x00002000) ); // GPIOx_MODER: Set Mode (Alternate Function)
100+
_WDWORD(0x40021008, ((_RDWORD(0x40021008) ) | 0x00003000) ); // GPIOx_OSPEEDR: Set Speed (Very High Speed)
101+
_WDWORD(0x4002100C, ((_RDWORD(0x4002100C) & ~0x00003000) ) ); // GPIOx_PUPDR: Set I/O to no pull-up/pull-down
102+
_WDWORD(0x40021020, ((_RDWORD(0x40021020) & ~0x0F000000) ) ); // GPIOx_AFRL: Alternate Function to AF0
103+
104+
/* configure TRACED2 */
105+
/* configure TRACED2 (PE5) */
106+
// _WDWORD(0x40023830, ( _RDWORD(0x40023830) | 0x00000010) ); // RCC_AHB1ENR: IO port E clock enable
107+
_WDWORD(0x40021000, ((_RDWORD(0x40021000) & ~0x00000C00) | 0x00000800) ); // GPIOx_MODER: Set Mode (Alternate Function)
108+
_WDWORD(0x40021008, ((_RDWORD(0x40021008) ) | 0x00000C00) ); // GPIOx_OSPEEDR: Set Speed (Very High Speed)
109+
_WDWORD(0x4002100C, ((_RDWORD(0x4002100C) & ~0x00000C00) ) ); // GPIOx_PUPDR: Set I/O to no pull-up/pull-down
110+
_WDWORD(0x40021020, ((_RDWORD(0x40021020) & ~0x00F00000) ) ); // GPIOx_AFRL: Alternate Function to AF0
111+
112+
case 2: /* TRACEDATA[1] */
113+
/* configure TRACED1 */
114+
/* configure TRACED1 (PE4) */
115+
// _WDWORD(0x40023830, ( _RDWORD(0x40023830) | 0x00000010) ); // RCC_AHB1ENR: IO port E clock enable
116+
_WDWORD(0x40021000, ((_RDWORD(0x40021000) & ~0x00000300) | 0x00000200) ); // GPIOx_MODER: Set Mode (Alternate Function)
117+
_WDWORD(0x40021008, ((_RDWORD(0x40021008) ) | 0x00000300) ); // GPIOx_OSPEEDR: Set Speed (Very High Speed)
118+
_WDWORD(0x4002100C, ((_RDWORD(0x4002100C) & ~0x00000300) ) ); // GPIOx_PUPDR: Set I/O to no pull-up/pull-down
119+
_WDWORD(0x40021020, ((_RDWORD(0x40021020) & ~0x000F0000) ) ); // GPIOx_AFRL: Alternate Function to AF0
120+
121+
case 1: /* TRACEDATA[0] */
122+
/* configure TRACED0 (PE3) */
123+
// _WDWORD(0x40023830, ( _RDWORD(0x40023830) | 0x00000010) ); // RCC_AHB1ENR: IO port E clock enable
124+
_WDWORD(0x40021000, ((_RDWORD(0x40021000) & ~0x000000C0) | 0x00000080) ); // GPIOx_MODER: Set Mode (Alternate Function)
125+
_WDWORD(0x40021008, ((_RDWORD(0x40021008) ) | 0x000000C0) ); // GPIOx_OSPEEDR: Set Speed (Very High Speed)
126+
_WDWORD(0x4002100C, ((_RDWORD(0x4002100C) & ~0x000000C0) ) ); // GPIOx_PUPDR: Set I/O to no pull-up/pull-down
127+
_WDWORD(0x40021020, ((_RDWORD(0x40021020) & ~0x0000F000) ) ); // GPIOx_AFRL: Alternate Function to AF0
128+
break;
129+
}
130+
}
131+
132+
}
133+
134+
/*----------------------------------------------------------------------------
135+
Setup_DBGMCU() configure DBGMCU registers
136+
*----------------------------------------------------------------------------*/
137+
FUNC void Setup_DBGMCU (void) {
138+
139+
if (DbgMCU_CR & (1 << 5)){
140+
Setup_TracePins (((DbgMCU_CR >> 6) & 3));
141+
}
142+
143+
_WDWORD(0xE0042004, DbgMCU_CR); // Set DBGMCU_CR
144+
_WDWORD(0xE0042008, DbgMCU_APB1_Fz); // Set DBGMCU_APB1_FZ
145+
_WDWORD(0xE004200C, DbgMCU_APB2_Fz); // Set DBGMCU_APB2_FZ
146+
}
147+
148+
149+
/*----------------------------------------------------------------------------
150+
OnResetExec() Executed after reset via uVision's 'Reset'-button
151+
*----------------------------------------------------------------------------*/
152+
FUNC void OnResetExec (void) {
153+
Setup_DBGMCU();
154+
}
155+
156+
Setup_DBGMCU(); // Debugger Setup

‎CMSIS/Flash/FlashOS.h‎

Lines changed: 84 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,84 @@
1+
/* -----------------------------------------------------------------------------
2+
* Copyright (c) 2014 ARM Ltd.
3+
*
4+
* This software is provided 'as-is', without any express or implied warranty.
5+
* In no event will the authors be held liable for any damages arising from
6+
* the use of this software. Permission is granted to anyone to use this
7+
* software for any purpose, including commercial applications, and to alter
8+
* it and redistribute it freely, subject to the following restrictions:
9+
*
10+
* 1. The origin of this software must not be misrepresented; you must not
11+
* claim that you wrote the original software. If you use this software in
12+
* a product, an acknowledgment in the product documentation would be
13+
* appreciated but is not required.
14+
*
15+
* 2. Altered source versions must be plainly marked as such, and must not be
16+
* misrepresented as being the original software.
17+
*
18+
* 3. This notice may not be removed or altered from any source distribution.
19+
*
20+
*
21+
* $Date: 14. Jan 2014
22+
* $Revision: V1.00
23+
*
24+
* Project: FlashOS Headerfile for Flash drivers
25+
* --------------------------------------------------------------------------- */
26+
27+
/* History:
28+
* Version 1.00
29+
* Initial release
30+
*/
31+
32+
#define VERS 1 // Interface Version 1.01
33+
34+
#define UNKNOWN 0 // Unknown
35+
#define ONCHIP 1 // On-chip Flash Memory
36+
#define EXT8BIT 2 // External Flash Device on 8-bit Bus
37+
#define EXT16BIT 3 // External Flash Device on 16-bit Bus
38+
#define EXT32BIT 4 // External Flash Device on 32-bit Bus
39+
#define EXTSPI 5 // External Flash Device on SPI
40+
41+
#define SECTOR_NUM 512 // Max Number of Sector Items
42+
#define PAGE_MAX 65536 // Max Page Size for Programming
43+
44+
struct FlashSectors {
45+
unsigned long szSector; // Sector Size in Bytes
46+
unsigned long AddrSector; // Address of Sector
47+
};
48+
49+
#define SECTOR_END 0xFFFFFFFF, 0xFFFFFFFF
50+
51+
struct FlashDevice {
52+
unsigned short Vers; // Version Number and Architecture
53+
char DevName[128]; // Device Name and Description
54+
unsigned short DevType; // Device Type: ONCHIP, EXT8BIT, EXT16BIT, ...
55+
unsigned long DevAdr; // Default Device Start Address
56+
unsigned long szDev; // Total Size of Device
57+
unsigned long szPage; // Programming Page Size
58+
unsigned long Res; // Reserved for future Extension
59+
unsigned char valEmpty; // Content of Erased Memory
60+
61+
unsigned long toProg; // Time Out of Program Page Function
62+
unsigned long toErase; // Time Out of Erase Sector Function
63+
64+
struct FlashSectors sectors[SECTOR_NUM];
65+
};
66+
67+
#define FLASH_DRV_VERS (0x0100+VERS) // Driver Version, do not modify!
68+
69+
// Flash Programming Functions (Called by FlashOS)
70+
extern int Init (unsigned long adr, // Initialize Flash
71+
unsigned long clk,
72+
unsigned long fnc);
73+
extern int UnInit (unsigned long fnc); // De-initialize Flash
74+
extern int BlankCheck (unsigned long adr, // Blank Check
75+
unsigned long sz,
76+
unsigned char pat);
77+
extern int EraseChip (void); // Erase complete Device
78+
extern int EraseSector (unsigned long adr); // Erase Sector Function
79+
extern int ProgramPage (unsigned long adr, // Program Page Function
80+
unsigned long sz,
81+
unsigned char *buf);
82+
extern unsigned long Verify (unsigned long adr, // Verify Function
83+
unsigned long sz,
84+
unsigned char *buf);

0 commit comments

Comments
 (0)