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add missing dbgconf files (#47)
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‎CubeMX/RTE/Device/STM32U585AIIx/STM32U535_545_575_585_59x_5Ax.dbgconf‎

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// File: STM32U535_545_575_585_59x_5Ax.dbgconf
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// Version: 1.0.0
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// Note: refer to STM32U5 reference manual (RM0456)
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// refer to STM32U535xx datasheet (DS14217)
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// STM32U545xx datasheet (DS14216)
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// STM32U575xx datasheet (DS13737)
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// STM32U585xx datasheet (DS13086)
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// STM32U59xxx datasheet (DS13633)
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// STM32U5Axxx datasheet (DS13543)
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// <<< Use Configuration Wizard in Context Menu >>>
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// <h> Debug MCU configuration register (DBGMCU_CR)
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// <o.2> DBG_STANDBY <i> Debug standby mode
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// <o.1> DBG_STOP <i> Debug stop mode
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// </h>
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DbgMCU_CR = 0x00000006;
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// <h> Debug MCU APB1L freeze register (DBGMCU_APB1LFZR)
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// <i> Reserved bits must be kept at reset value
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// <o.22> DBG_I2C2_STOP <i> I2C2 SMBUS timeout is frozen while CPU is in debug mode
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// <o.21> DBG_I2C1_STOP <i> I2C1 SMBUS timeout is frozen while CPU is in debug mode
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// <o.12> DBG_IWDG_STOP <i> Debug independent watchdog is frozen while CPU is in debug mode
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// <o.11> DBG_WWDG_STOP <i> Debug window watchdog is frozen while CPU is in debug mode
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// <o.5> DBG_TIM7_STOP <i> TIM7 is frozen while CPU is in debug mode
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// <o.4> DBG_TIM6_STOP <i> TIM6 is frozen while CPU is in debug mode
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// <o.3> DBG_TIM5_STOP <i> TIM5 is frozen while CPU is in debug mode
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// <o.2> DBG_TIM4_STOP <i> TIM4 is frozen while CPU is in debug mode
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// <o.1> DBG_TIM3_STOP <i> TIM3 is frozen while CPU is in debug mode
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// <o.0> DBG_TIM2_STOP <i> TIM2 is frozen while CPU is in debug mode
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// </h>
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DbgMCU_APB1L_Fz = 0x00000000;
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// <h> Debug MCU APB1H freeze register (DBGMCU_APB1HFZR)
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// <i> Reserved bits must be kept at reset value
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// <o.7> DBG_I2C6_STOP <i> I2C6 is frozen while CPU is in debug mode
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// <i> Reserved on STM32U535/545/575/585 devices
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// <o.6> DBG_I2C5_STOP <i> I2C5 is frozen while CPU is in debug mode
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// <i> Reserved on STM32U535/545/575/585 devices
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// <o.5> DBG_LPTIM2_STOP <i> LPTIM2 is frozen while CPU is in debug mode
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// <o.1> DBG_I2C4_STOP <i> I2C4 is frozen while CPU is in debug mode
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// </h>
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DbgMCU_APB1H_Fz = 0x00000000;
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// <h> Debug MCU APB2 freeze register (DBGMCU_APB2FZR)
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// <i> Reserved bits must be kept at reset value
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// <o.18> DBG_TIM17_STOP <i> TIM17 is frozen while CPU is in debug mode
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// <o.17> DBG_TIM16_STOP <i> TIM16 is frozen while CPU is in debug mode
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// <o.16> DBG_TIM15_STOP <i> TIM15 is frozen while CPU is in debug mode
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// <o.13> DBG_TIM8_STOP <i> TIM8 is frozen while CPU is in debug mode
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// <o.11> DBG_TIM1_STOP <i> TIM1 is frozen while CPU is in debug mode
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// </h>
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DbgMCU_APB2_Fz = 0x00000000;
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// <h> Debug MCU APB3 freeze register (DBGMCU_APB3FZR)
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// <i> Reserved bits must be kept at reset value
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// <o.30> DBG_RTC_STOP <i> RTC is frozen while CPU is in debug mode.
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// <o.19> DBG_LPTIM4_STOP <i> LPTIM4 is frozen while CPU is in debug mode
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// <o.18> DBG_LPTIM3_STOP <i> LPTIM3 is frozen while CPU is in debug mode
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// <o.17> DBG_LPTIM1_STOP <i> LPTIM1 is frozen while CPU is in debug mode
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// <o.10> DBG_I2C3_STOP <i> I2C3 is frozen while CPU is in debug mode
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// </h>
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DbgMCU_APB3_Fz = 0x00000000;
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// <h> Debug MCU AHB1 freeze register (DBGMCU_AHB1FZR)
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// <i> Reserved bits must be kept at reset value
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// <o.15> DBG_GPDMA15_STOP <i> GPDMA channel 15 is frozen while CPU is in debug mode
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// <o.14> DBG_GPDMA14_STOP <i> GPDMA channel 14 is frozen while CPU is in debug mode
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// <o.13> DBG_GPDMA13_STOP <i> GPDMA channel 13 is frozen while CPU is in debug mode
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// <o.12> DBG_GPDMA12_STOP <i> GPDMA channel 12 is frozen while CPU is in debug mode
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// <o.11> DBG_GPDMA11_STOP <i> GPDMA channel 11 is frozen while CPU is in debug mode
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// <o.10> DBG_GPDMA10_STOP <i> GPDMA channel 10 is frozen while CPU is in debug mode
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// <o.9> DBG_GPDMA9_STOP <i> GPDMA channel 9 is frozen while CPU is in debug mode
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// <o.8> DBG_GPDMA8_STOP <i> GPDMA channel 8 is frozen while CPU is in debug mode
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// <o.7> DBG_GPDMA7_STOP <i> GPDMA channel 7 is frozen while CPU is in debug mode
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// <o.6> DBG_GPDMA6_STOP <i> GPDMA channel 6 is frozen while CPU is in debug mode
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// <o.5> DBG_GPDMA5_STOP <i> GPDMA channel 5 is frozen while CPU is in debug mode
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// <o.4> DBG_GPDMA4_STOP <i> GPDMA channel 4 is frozen while CPU is in debug mode
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// <o.3> DBG_GPDMA3_STOP <i> GPDMA channel 3 is frozen while CPU is in debug mode
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// <o.2> DBG_GPDMA2_STOP <i> GPDMA channel 2 is frozen while CPU is in debug mode
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// <o.1> DBG_GPDMA1_STOP <i> GPDMA channel 1 is frozen while CPU is in debug mode
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// <o.0> DBG_GPDMA0_STOP <i> GPDMA channel 0 is frozen while CPU is in debug mode
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// </h>
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DbgMCU_AHB1_Fz = 0x00000000;
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// <h> Debug MCU AHB3 freeze register (DBGMCU_AHB3FZR)
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// <i> Reserved bits must be kept at reset value
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// <o.3> DBG_LPDMA3_STOP <i> LPDMA channel 3 is frozen while CPU is in debug mode
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// <o.2> DBG_LPDMA2_STOP <i> LPDMA channel 2 is frozen while CPU is in debug mode
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// <o.1> DBG_LPDMA1_STOP <i> LPDMA channel 1 is frozen while CPU is in debug mode
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// <o.0> DBG_LPDMA0_STOP <i> LPDMA channel 0 is frozen while CPU is in debug mode
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// </h>
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DbgMCU_AHB3_Fz = 0x00000000;
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// <h> TPIU Pin Routing
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// <o0> TRACECLK
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// <i> ETM Trace Clock
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// <0x0002000A=> Pin PE2
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// <0x00000008=> Pin PA8
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// <i> TRACECLK: Pin PE2
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// <o1> TRACED0
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// <i> ETM Trace Data 0
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// <0x00040003=> Pin PE3
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// <0x00020009=> Pin PC9
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// <0x00020001=> Pin PC1
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// <o2> TRACED1
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// <i> ETM Trace Data 1
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// <0x0002000A=> Pin PC10
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// <0x00040004=> Pin PE4
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// <o3> TRACED2
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// <i> ETM Trace Data 2
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// <0x00040005=> Pin PE5
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// <0x00030002=> Pin PD2
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// <o4> TRACED3
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// <i> ETM Trace Data 3
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// <0x00040006=> Pin PE6
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// <0x0002000C=> Pin PC12
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// </h>
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TraceClk_Pin = 0x00040002;
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TraceD0_Pin = 0x00020009;
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TraceD1_Pin = 0x0002000A;
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TraceD2_Pin = 0x00040005;
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TraceD3_Pin = 0x0002000C;
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// <h> Flash Download Options
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// <o.0> Option Byte Loading <i> Launch the Option Byte Loading after a Flash Download by setting the OBL_LAUNCH bit (causes a reset)
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// </h>
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DoOptionByteLoading = 0x00000000;
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// <<< end of configuration section >>>

‎CubeMX/RTE/Device/STM32U585AIIx/[email protected]‎

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// File: STM32U535_545_575_585_59x_5Ax.dbgconf
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// Version: 1.0.0
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// Note: refer to STM32U5 reference manual (RM0456)
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// refer to STM32U535xx datasheet (DS14217)
5+
// STM32U545xx datasheet (DS14216)
6+
// STM32U575xx datasheet (DS13737)
7+
// STM32U585xx datasheet (DS13086)
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// STM32U59xxx datasheet (DS13633)
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// STM32U5Axxx datasheet (DS13543)
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// <<< Use Configuration Wizard in Context Menu >>>
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// <h> Debug MCU configuration register (DBGMCU_CR)
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// <o.2> DBG_STANDBY <i> Debug standby mode
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// <o.1> DBG_STOP <i> Debug stop mode
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// </h>
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DbgMCU_CR = 0x00000006;
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// <h> Debug MCU APB1L freeze register (DBGMCU_APB1LFZR)
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// <i> Reserved bits must be kept at reset value
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// <o.22> DBG_I2C2_STOP <i> I2C2 SMBUS timeout is frozen while CPU is in debug mode
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// <o.21> DBG_I2C1_STOP <i> I2C1 SMBUS timeout is frozen while CPU is in debug mode
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// <o.12> DBG_IWDG_STOP <i> Debug independent watchdog is frozen while CPU is in debug mode
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// <o.11> DBG_WWDG_STOP <i> Debug window watchdog is frozen while CPU is in debug mode
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// <o.5> DBG_TIM7_STOP <i> TIM7 is frozen while CPU is in debug mode
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// <o.4> DBG_TIM6_STOP <i> TIM6 is frozen while CPU is in debug mode
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// <o.3> DBG_TIM5_STOP <i> TIM5 is frozen while CPU is in debug mode
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// <o.2> DBG_TIM4_STOP <i> TIM4 is frozen while CPU is in debug mode
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// <o.1> DBG_TIM3_STOP <i> TIM3 is frozen while CPU is in debug mode
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// <o.0> DBG_TIM2_STOP <i> TIM2 is frozen while CPU is in debug mode
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// </h>
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DbgMCU_APB1L_Fz = 0x00000000;
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// <h> Debug MCU APB1H freeze register (DBGMCU_APB1HFZR)
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// <i> Reserved bits must be kept at reset value
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// <o.7> DBG_I2C6_STOP <i> I2C6 is frozen while CPU is in debug mode
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// <i> Reserved on STM32U535/545/575/585 devices
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// <o.6> DBG_I2C5_STOP <i> I2C5 is frozen while CPU is in debug mode
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// <i> Reserved on STM32U535/545/575/585 devices
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// <o.5> DBG_LPTIM2_STOP <i> LPTIM2 is frozen while CPU is in debug mode
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// <o.1> DBG_I2C4_STOP <i> I2C4 is frozen while CPU is in debug mode
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// </h>
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DbgMCU_APB1H_Fz = 0x00000000;
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// <h> Debug MCU APB2 freeze register (DBGMCU_APB2FZR)
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// <i> Reserved bits must be kept at reset value
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// <o.18> DBG_TIM17_STOP <i> TIM17 is frozen while CPU is in debug mode
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// <o.17> DBG_TIM16_STOP <i> TIM16 is frozen while CPU is in debug mode
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// <o.16> DBG_TIM15_STOP <i> TIM15 is frozen while CPU is in debug mode
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// <o.13> DBG_TIM8_STOP <i> TIM8 is frozen while CPU is in debug mode
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// <o.11> DBG_TIM1_STOP <i> TIM1 is frozen while CPU is in debug mode
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// </h>
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DbgMCU_APB2_Fz = 0x00000000;
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// <h> Debug MCU APB3 freeze register (DBGMCU_APB3FZR)
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// <i> Reserved bits must be kept at reset value
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// <o.30> DBG_RTC_STOP <i> RTC is frozen while CPU is in debug mode.
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// <o.19> DBG_LPTIM4_STOP <i> LPTIM4 is frozen while CPU is in debug mode
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// <o.18> DBG_LPTIM3_STOP <i> LPTIM3 is frozen while CPU is in debug mode
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// <o.17> DBG_LPTIM1_STOP <i> LPTIM1 is frozen while CPU is in debug mode
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// <o.10> DBG_I2C3_STOP <i> I2C3 is frozen while CPU is in debug mode
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// </h>
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DbgMCU_APB3_Fz = 0x00000000;
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// <h> Debug MCU AHB1 freeze register (DBGMCU_AHB1FZR)
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// <i> Reserved bits must be kept at reset value
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// <o.15> DBG_GPDMA15_STOP <i> GPDMA channel 15 is frozen while CPU is in debug mode
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// <o.14> DBG_GPDMA14_STOP <i> GPDMA channel 14 is frozen while CPU is in debug mode
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// <o.13> DBG_GPDMA13_STOP <i> GPDMA channel 13 is frozen while CPU is in debug mode
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// <o.12> DBG_GPDMA12_STOP <i> GPDMA channel 12 is frozen while CPU is in debug mode
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// <o.11> DBG_GPDMA11_STOP <i> GPDMA channel 11 is frozen while CPU is in debug mode
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// <o.10> DBG_GPDMA10_STOP <i> GPDMA channel 10 is frozen while CPU is in debug mode
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// <o.9> DBG_GPDMA9_STOP <i> GPDMA channel 9 is frozen while CPU is in debug mode
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// <o.8> DBG_GPDMA8_STOP <i> GPDMA channel 8 is frozen while CPU is in debug mode
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// <o.7> DBG_GPDMA7_STOP <i> GPDMA channel 7 is frozen while CPU is in debug mode
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// <o.6> DBG_GPDMA6_STOP <i> GPDMA channel 6 is frozen while CPU is in debug mode
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// <o.5> DBG_GPDMA5_STOP <i> GPDMA channel 5 is frozen while CPU is in debug mode
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// <o.4> DBG_GPDMA4_STOP <i> GPDMA channel 4 is frozen while CPU is in debug mode
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// <o.3> DBG_GPDMA3_STOP <i> GPDMA channel 3 is frozen while CPU is in debug mode
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// <o.2> DBG_GPDMA2_STOP <i> GPDMA channel 2 is frozen while CPU is in debug mode
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// <o.1> DBG_GPDMA1_STOP <i> GPDMA channel 1 is frozen while CPU is in debug mode
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// <o.0> DBG_GPDMA0_STOP <i> GPDMA channel 0 is frozen while CPU is in debug mode
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// </h>
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DbgMCU_AHB1_Fz = 0x00000000;
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// <h> Debug MCU AHB3 freeze register (DBGMCU_AHB3FZR)
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// <i> Reserved bits must be kept at reset value
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// <o.3> DBG_LPDMA3_STOP <i> LPDMA channel 3 is frozen while CPU is in debug mode
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// <o.2> DBG_LPDMA2_STOP <i> LPDMA channel 2 is frozen while CPU is in debug mode
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// <o.1> DBG_LPDMA1_STOP <i> LPDMA channel 1 is frozen while CPU is in debug mode
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// <o.0> DBG_LPDMA0_STOP <i> LPDMA channel 0 is frozen while CPU is in debug mode
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// </h>
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DbgMCU_AHB3_Fz = 0x00000000;
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// <h> TPIU Pin Routing
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// <o0> TRACECLK
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// <i> ETM Trace Clock
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// <0x0002000A=> Pin PE2
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// <0x00000008=> Pin PA8
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// <i> TRACECLK: Pin PE2
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// <o1> TRACED0
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// <i> ETM Trace Data 0
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// <0x00040003=> Pin PE3
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// <0x00020009=> Pin PC9
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// <0x00020001=> Pin PC1
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// <o2> TRACED1
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// <i> ETM Trace Data 1
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// <0x0002000A=> Pin PC10
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// <0x00040004=> Pin PE4
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// <o3> TRACED2
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// <i> ETM Trace Data 2
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// <0x00040005=> Pin PE5
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// <0x00030002=> Pin PD2
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// <o4> TRACED3
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// <i> ETM Trace Data 3
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// <0x00040006=> Pin PE6
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// <0x0002000C=> Pin PC12
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// </h>
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TraceClk_Pin = 0x00040002;
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TraceD0_Pin = 0x00020009;
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TraceD1_Pin = 0x0002000A;
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TraceD2_Pin = 0x00040005;
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TraceD3_Pin = 0x0002000C;
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// <h> Flash Download Options
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// <o.0> Option Byte Loading <i> Launch the Option Byte Loading after a Flash Download by setting the OBL_LAUNCH bit (causes a reset)
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// </h>
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DoOptionByteLoading = 0x00000000;
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// <<< end of configuration section >>>

‎Hello/RTE/Device/SSE-300-MPS3/CM55.dbgconf‎

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// Copyright (c) 2024 Arm Limited. All rights reserved.
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// SPDX-License-Identifier: Apache-2.0
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// <<< Use Configuration Wizard in Context Menu >>>
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// <e> Fixed Debug Authentication
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// <i> Use a fixed value for Debug Authentication. Only secure debug authentication configurable.
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DAuthFixed = 0x1;
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// <q.2> Secure Invasive Debug
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// <q.3> Secure Non-Invasive Debug
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DAuthConfig = 0xF;
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// </e>
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// <<< end of configuration section >>>

‎Hello/RTE/Device/SSE-300-MPS3/[email protected]‎

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// Copyright (c) 2024 Arm Limited. All rights reserved.
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// SPDX-License-Identifier: Apache-2.0
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// <<< Use Configuration Wizard in Context Menu >>>
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// <e> Fixed Debug Authentication
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// <i> Use a fixed value for Debug Authentication. Only secure debug authentication configurable.
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DAuthFixed = 0x1;
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// <q.2> Secure Invasive Debug
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// <q.3> Secure Non-Invasive Debug
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DAuthConfig = 0xF;
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// </e>
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// <<< end of configuration section >>>

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