Skip to content

Commit cbb136b

Browse files
DavidLesnjakDavidLesnjak
authored
Update CubeMX example (ROM and RAM target types) (#39)
1 parent 983aabd commit cbb136b

File tree

255 files changed

+183637
-57794
lines changed

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

255 files changed

+183637
-57794
lines changed

‎CubeMX/CubeMX.cbuild-pack.yml‎

Lines changed: 0 additions & 14 deletions
This file was deleted.

‎CubeMX/CubeMX.cbuild-set.yml‎

Lines changed: 0 additions & 4 deletions
This file was deleted.

‎CubeMX/CubeMX.cproject.yml‎

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,4 @@
11
project:
2-
packs:
3-
- pack: ARM::CMSIS-RTX@^5.9.0 # RTOS Software Pack
4-
52
groups:
63
- group: Documentation
74
files:
@@ -15,3 +12,9 @@ project:
1512
- component: Device:CubeMX
1613
- component: CMSIS:RTOS2:Keil RTX5&Source
1714
- component: CMSIS:OS Tick
15+
16+
linker:
17+
- script: RTE/Device/STM32U585AIIx/ac6_linker_script.sct.src
18+
- regions: $regions_header$
19+
for-compiler: AC6
20+

‎CubeMX/CubeMX.csolution.yml‎

Lines changed: 14 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -4,19 +4,29 @@ solution:
44
cdefault:
55
compiler: AC6 # currently required for components Compiler:I/O
66

7-
# it is recommended to list the pack or packs that define the device or board used in the csolution.yml file
7+
# it is recommended to list the pack or packs that define the device or board used in the csolution.yml file
88
packs:
9-
- pack: ARM::CMSIS@^6.0.0
9+
- pack: ARM::CMSIS@^6.1.0
1010
- pack: Keil::B-U585I-IOT02A_BSP@^2.0.0
1111
- pack: Keil::STM32U5xx_DFP@^3.0.0
12+
- pack: ARM::CMSIS-RTX@^5.9.0
1213
target-types:
13-
- type: MyBoard # My evaluation kit
14+
- type: MyBoard_ROM # My evaluation kit (Execution from ROM)
1415
board: B-U585I-IOT02A # Board name as defined by the pack
16+
variables:
17+
- regions_header: RTE/Device/STM32U585AIIx/regions_B-U585I-IOT02A_ROM.h
18+
19+
- type: MyBoard_RAM # My evaluation kit (Execution from RAM)
20+
board: B-U585I-IOT02A # Board name as defined by the pack
21+
variables:
22+
- regions_header: RTE/Device/STM32U585AIIx/regions_B-U585I-IOT02A_RAM.h
23+
define:
24+
- VECT_TAB_SRAM
1525

1626
build-types: # defines toolchain options for 'debug' and 'release'
1727
- type: Debug
1828
debug: on
19-
optimize: none
29+
optimize: debug
2030

2131
- type: Release
2232
debug: off

‎CubeMX/RTE/Device/STM32U585AIIx/regions_B-U585I-IOT02A_RAM.h‎

Lines changed: 100 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,100 @@
1+
#ifndef REGIONS_B_U585I_IOT02A_H
2+
#define REGIONS_B_U585I_IOT02A_H
3+
4+
5+
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
6+
//------ With VS Code: Open Preview for Configuration Wizard -------------------
7+
8+
// <n> Auto-generated using information from packs
9+
// <i> Device Family Pack (DFP): Keil::[email protected]
10+
// <i> Board Support Pack (BSP): Keil::[email protected]
11+
12+
// <h> ROM Configuration
13+
// =======================
14+
// <h> __ROM0 (modified: Execution memory is RAM)
15+
// <o> Base address <0x0-0xFFFFFFFF:8>
16+
// <i> Defines base address of memory region. Default: 0x08000000
17+
// <i> Contains Startup and Vector Table
18+
#define __ROM0_BASE 0x20000000
19+
// <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
20+
// <i> Defines size of memory region. Default: 0x00200000
21+
#define __ROM0_SIZE 0x00030000
22+
// </h>
23+
24+
// <h> __ROM1 (unused)
25+
// <o> Base address <0x0-0xFFFFFFFF:8>
26+
// <i> Defines base address of memory region.
27+
#define __ROM1_BASE 0
28+
// <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
29+
// <i> Defines size of memory region.
30+
#define __ROM1_SIZE 0
31+
// </h>
32+
33+
// <h> __ROM2 (unused)
34+
// <o> Base address <0x0-0xFFFFFFFF:8>
35+
// <i> Defines base address of memory region.
36+
#define __ROM2_BASE 0
37+
// <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
38+
// <i> Defines size of memory region.
39+
#define __ROM2_SIZE 0
40+
// </h>
41+
42+
// <h> __ROM3 (unused)
43+
// <o> Base address <0x0-0xFFFFFFFF:8>
44+
// <i> Defines base address of memory region.
45+
#define __ROM3_BASE 0
46+
// <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
47+
// <i> Defines size of memory region.
48+
#define __ROM3_SIZE 0
49+
// </h>
50+
51+
// </h>
52+
53+
// <h> RAM Configuration
54+
// =======================
55+
// <h> __RAM0 (is rwx memory: SRAM1_2 from DFP)
56+
// <o> Base address <0x0-0xFFFFFFFF:8>
57+
// <i> Defines base address of memory region. Default: 0x20000000
58+
// <i> Contains uninitialized RAM, Stack, and Heap
59+
#define __RAM0_BASE 0x20030000
60+
// <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
61+
// <i> Defines size of memory region. Default: 0x00040000
62+
#define __RAM0_SIZE 0x00010000
63+
// </h>
64+
65+
// <h> __RAM1 (unused)
66+
// <o> Base address <0x0-0xFFFFFFFF:8>
67+
// <i> Defines base address of memory region.
68+
#define __RAM1_BASE 0
69+
// <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
70+
// <i> Defines size of memory region.
71+
#define __RAM1_SIZE 0
72+
// </h>
73+
74+
// <h> __RAM2 (unused)
75+
// <o> Base address <0x0-0xFFFFFFFF:8>
76+
// <i> Defines base address of memory region.
77+
#define __RAM2_BASE 0
78+
// <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
79+
// <i> Defines size of memory region.
80+
#define __RAM2_SIZE 0
81+
// </h>
82+
83+
// <h> __RAM3 (unused)
84+
// <o> Base address <0x0-0xFFFFFFFF:8>
85+
// <i> Defines base address of memory region.
86+
#define __RAM3_BASE 0
87+
// <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
88+
// <i> Defines size of memory region.
89+
#define __RAM3_SIZE 0
90+
// </h>
91+
92+
// </h>
93+
94+
// <n> Resources that are not allocated to linker regions
95+
// <i> rwx RAM: SRAM3 from DFP: BASE: 0x20040000 SIZE: 0x00080000
96+
// <i> rwx RAM: RAM-External from BSP: BASE: 0x90000000 SIZE: 0x00800000
97+
// <i> rx ROM: Flash-External from BSP: BASE: 0x70000000 SIZE: 0x04000000
98+
99+
100+
#endif /* REGIONS_B_U585I_IOT02A_H */

‎CubeMX/RTE/Device/STM32U585AIIx/regions_B-U585I-IOT02A.h‎ renamed to ‎CubeMX/RTE/Device/STM32U585AIIx/regions_B-U585I-IOT02A_ROM.h‎

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -91,13 +91,6 @@
9191

9292
// </h>
9393

94-
// <h> Stack / Heap Configuration
95-
// <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
96-
// <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
97-
#define __STACK_SIZE 0x00000200
98-
#define __HEAP_SIZE 0x00000C00
99-
// </h>
100-
10194
// <n> Resources that are not allocated to linker regions
10295
// <i> rwx RAM: SRAM3 from DFP: BASE: 0x20040000 SIZE: 0x00080000
10396
// <i> rwx RAM: RAM-External from BSP: BASE: 0x90000000 SIZE: 0x00800000

‎CubeMX/RTE/Device/STM32U585AIIx/regions_B_U585I_IOT02A.h‎

Lines changed: 0 additions & 70 deletions
This file was deleted.

‎CubeMX/RTE/_Debug_MyBoard/RTE_Components.h‎ renamed to ‎CubeMX/RTE/_Debug_MyBoard_RAM/RTE_Components.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,8 @@
22
* CSOLUTION generated file: DO NOT EDIT!
33
* Generated by: csolution version 2.6.0
44
*
5-
* Project: 'CubeMX.Debug+MyBoard'
6-
* Target: 'Debug+MyBoard'
5+
* Project: 'CubeMX.Debug+MyBoard_RAM'
6+
* Target: 'Debug+MyBoard_RAM'
77
*/
88

99
#ifndef RTE_COMPONENTS_H

‎CubeMX/RTE/_Release_MyBoard/RTE_Components.h‎ renamed to ‎CubeMX/RTE/_Debug_MyBoard_ROM/RTE_Components.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,8 @@
22
* CSOLUTION generated file: DO NOT EDIT!
33
* Generated by: csolution version 2.6.0
44
*
5-
* Project: 'CubeMX.Release+MyBoard'
6-
* Target: 'Release+MyBoard'
5+
* Project: 'CubeMX.Debug+MyBoard_ROM'
6+
* Target: 'Debug+MyBoard_ROM'
77
*/
88

99
#ifndef RTE_COMPONENTS_H

‎CubeMX/RTE/_Release_MyBoard_RAM/RTE_Components.h‎

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,21 @@
1+
/*
2+
* CSOLUTION generated file: DO NOT EDIT!
3+
* Generated by: csolution version 2.6.0
4+
*
5+
* Project: 'CubeMX.Release+MyBoard_RAM'
6+
* Target: 'Release+MyBoard_RAM'
7+
*/
8+
9+
#ifndef RTE_COMPONENTS_H
10+
#define RTE_COMPONENTS_H
11+
12+
/* ARM::CMSIS:RTOS2:Keil RTX5&[email protected] */
13+
#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */
14+
#define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */
15+
#define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */
16+
/* Keil::Device:[email protected] */
17+
#define RTE_DEVICE_CUBE_MX
18+
#define CMSIS_device_header "stm32u5xx.h"
19+
20+
21+
#endif /* RTE_COMPONENTS_H */

0 commit comments

Comments
 (0)