From e92d8d217ae17334039c699250ad4696744e5cc6 Mon Sep 17 00:00:00 2001 From: Hassen Gassoumi Date: Wed, 12 Sep 2018 11:34:55 +0200 Subject: [PATCH 1/3] Update Vivado version to 2018.2 for Hybrid Design --- .../mn-dual-shmem-gpio/vivado/system.xdc | 60 +- .../mn-dual-shmem-gpio/vivado/system_bd.tcl | 2488 +++++++---------- 2 files changed, 1049 insertions(+), 1499 deletions(-) diff --git a/hardware/boards/xilinx-z702/mn-dual-shmem-gpio/vivado/system.xdc b/hardware/boards/xilinx-z702/mn-dual-shmem-gpio/vivado/system.xdc index 43f1e029a..ea2d55837 100644 --- a/hardware/boards/xilinx-z702/mn-dual-shmem-gpio/vivado/system.xdc +++ b/hardware/boards/xilinx-z702/mn-dual-shmem-gpio/vivado/system.xdc @@ -331,4 +331,62 @@ set_clock_groups -asynchronous -group [get_clocks {system_i/proc_sys_rst/periphe set_clock_groups -asynchronous -group [get_clocks {system_i/proc_sys_rst/peripheral_aresetn[0]}] -group [get_clocks clk_mii1_tx] set_false_path -reset_path -from [get_clocks clk_mii0_rx] -to [get_clocks clk_mii0_rx] set_false_path -reset_path -from [get_clocks clk_mii1_rx] -to [get_clocks clk_mii1_rx] -######################################################################## \ No newline at end of file +######################################################################## + +set_property IOSTANDARD LVCMOS25 [get_ports {BENCHMARK_PIO_tri_io[7]}] +set_property IOSTANDARD LVCMOS25 [get_ports {BENCHMARK_PIO_tri_io[6]}] +set_property IOSTANDARD LVCMOS25 [get_ports {BENCHMARK_PIO_tri_io[5]}] +set_property IOSTANDARD LVCMOS25 [get_ports {BENCHMARK_PIO_tri_io[4]}] +set_property IOSTANDARD LVCMOS25 [get_ports {BENCHMARK_PIO_tri_io[3]}] +set_property IOSTANDARD LVCMOS25 [get_ports {BENCHMARK_PIO_tri_io[2]}] +set_property IOSTANDARD LVCMOS25 [get_ports {BENCHMARK_PIO_tri_io[1]}] +set_property IOSTANDARD LVCMOS25 [get_ports {BENCHMARK_PIO_tri_io[0]}] +set_property IOSTANDARD LVCMOS25 [get_ports {HOST_BENCHMARK_PIO_tri_io[7]}] +set_property IOSTANDARD LVCMOS25 [get_ports {HOST_BENCHMARK_PIO_tri_io[6]}] +set_property IOSTANDARD LVCMOS25 [get_ports {HOST_BENCHMARK_PIO_tri_io[5]}] +set_property IOSTANDARD LVCMOS25 [get_ports {HOST_BENCHMARK_PIO_tri_io[4]}] +set_property IOSTANDARD LVCMOS25 [get_ports {HOST_BENCHMARK_PIO_tri_io[3]}] +set_property IOSTANDARD LVCMOS25 [get_ports {HOST_BENCHMARK_PIO_tri_io[2]}] +set_property IOSTANDARD LVCMOS25 [get_ports {HOST_BENCHMARK_PIO_tri_io[1]}] +set_property IOSTANDARD LVCMOS25 [get_ports {HOST_BENCHMARK_PIO_tri_io[0]}] +set_property PACKAGE_PIN AB20 [get_ports {BENCHMARK_PIO_tri_io[7]}] +set_property PACKAGE_PIN AB19 [get_ports {BENCHMARK_PIO_tri_io[6]}] +set_property PACKAGE_PIN W13 [get_ports {BENCHMARK_PIO_tri_io[5]}] +set_property PACKAGE_PIN V13 [get_ports {BENCHMARK_PIO_tri_io[4]}] +set_property PACKAGE_PIN AB16 [get_ports {BENCHMARK_PIO_tri_io[3]}] +set_property PACKAGE_PIN AA16 [get_ports {BENCHMARK_PIO_tri_io[2]}] +set_property PACKAGE_PIN V15 [get_ports {BENCHMARK_PIO_tri_io[1]}] +set_property PACKAGE_PIN V14 [get_ports {BENCHMARK_PIO_tri_io[0]}] +set_property PACKAGE_PIN U16 [get_ports {HOST_BENCHMARK_PIO_tri_io[7]}] +set_property PACKAGE_PIN U15 [get_ports {HOST_BENCHMARK_PIO_tri_io[6]}] +set_property PACKAGE_PIN AB17 [get_ports {HOST_BENCHMARK_PIO_tri_io[5]}] +set_property PACKAGE_PIN AA17 [get_ports {HOST_BENCHMARK_PIO_tri_io[4]}] +set_property PACKAGE_PIN U21 [get_ports {HOST_BENCHMARK_PIO_tri_io[3]}] +set_property PACKAGE_PIN T21 [get_ports {HOST_BENCHMARK_PIO_tri_io[2]}] +set_property PACKAGE_PIN V17 [get_ports {HOST_BENCHMARK_PIO_tri_io[1]}] +set_property PACKAGE_PIN U17 [get_ports {HOST_BENCHMARK_PIO_tri_io[0]}] +set_property IOSTANDARD LVCMOS25 [get_ports {LEDS_6BIT_tri_o[5]}] +set_property IOSTANDARD LVCMOS25 [get_ports {LEDS_6BIT_tri_o[4]}] +set_property IOSTANDARD LVCMOS25 [get_ports {LEDS_6BIT_tri_o[3]}] +set_property IOSTANDARD LVCMOS25 [get_ports {LEDS_6BIT_tri_o[2]}] +set_property IOSTANDARD LVCMOS25 [get_ports {LEDS_6BIT_tri_o[1]}] +set_property IOSTANDARD LVCMOS25 [get_ports {LEDS_6BIT_tri_o[0]}] +set_property PACKAGE_PIN W17 [get_ports {LEDS_6BIT_tri_o[5]}] +set_property PACKAGE_PIN W5 [get_ports {LEDS_6BIT_tri_o[4]}] +set_property PACKAGE_PIN V7 [get_ports {LEDS_6BIT_tri_o[3]}] +set_property PACKAGE_PIN W10 [get_ports {LEDS_6BIT_tri_o[2]}] +set_property PACKAGE_PIN P18 [get_ports {LEDS_6BIT_tri_o[1]}] +set_property PACKAGE_PIN P17 [get_ports {LEDS_6BIT_tri_o[0]}] +set_property IOSTANDARD LVCMOS25 [get_ports {NODE_SWITCHES_tri_io[1]}] +set_property IOSTANDARD LVCMOS25 [get_ports {NODE_SWITCHES_tri_io[0]}] +set_property PACKAGE_PIN W6 [get_ports {NODE_SWITCHES_tri_io[1]}] +set_property PACKAGE_PIN W7 [get_ports {NODE_SWITCHES_tri_io[0]}] +set_property IOSTANDARD LVCMOS25 [get_ports {POWERLINK_LED_tri_o[1]}] +set_property IOSTANDARD LVCMOS25 [get_ports {POWERLINK_LED_tri_o[0]}] +set_property PACKAGE_PIN D15 [get_ports {POWERLINK_LED_tri_o[0]}] +set_property PACKAGE_PIN E15 [get_ports {POWERLINK_LED_tri_o[1]}] +set_property PACKAGE_PIN N17 [get_ports {SMI_mdio_io[1]}] +set_property PACKAGE_PIN N15 [get_ports {SMI_mdio_io[0]}] +set_property IOSTANDARD LVCMOS25 [get_ports {SMI_mdio_io[1]}] +set_property IOSTANDARD LVCMOS25 [get_ports {SMI_mdio_io[0]}] + diff --git a/hardware/boards/xilinx-z702/mn-dual-shmem-gpio/vivado/system_bd.tcl b/hardware/boards/xilinx-z702/mn-dual-shmem-gpio/vivado/system_bd.tcl index 36e7477df..0c390159d 100644 --- a/hardware/boards/xilinx-z702/mn-dual-shmem-gpio/vivado/system_bd.tcl +++ b/hardware/boards/xilinx-z702/mn-dual-shmem-gpio/vivado/system_bd.tcl @@ -1,30 +1,18 @@ + ################################################################ -# @file system_bd.tcl -# -# @brief TCL file for Zynq-ZC702 board -# -# @details This is the TCL file for generating the hardware block -# design for Zynq-ZC702 board -# -################################################################ -# # This is a generated script based on design: system # +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. ################################################################ -if { $argc != 1 } { - puts "The script requires 1 input." - puts "Please try again." - exit -1 - } else { - #puts [expr [lindex $argv 0] + [lindex $argv 1]] - } namespace eval _tcl { proc get_script_folder {} { set script_path [file normalize [info script]] set script_folder [file dirname $script_path] return $script_folder - } +} } variable script_folder set script_folder [_tcl::get_script_folder] @@ -32,7 +20,7 @@ set script_folder [_tcl::get_script_folder] ################################################################ # Check if script is running in correct Vivado version. ################################################################ -set scripts_vivado_version 2016.2 +set scripts_vivado_version 2018.2 set current_vivado_version [version -short] if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { @@ -46,6 +34,13 @@ if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { # START ################################################################ +# To test this script, run the following commands from Vivado Tcl console: +# source system_script.tcl + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + # Create project set proj_name system create_project -force $proj_name system -part xc7z020clg484-1 @@ -60,8 +55,6 @@ set_property target_language VHDL [current_project] set proj_dir [get_property directory $obj] set_property ip_repo_paths $proj_dir/../../../../../ipcore/xilinx [current_project] update_ip_catalog - -# CHANGE DESIGN NAME HERE set design_name system # If you do not already have an existing IP Integrator design open, @@ -101,7 +94,7 @@ if { ${design_name} eq "" } { set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." set nRet 1 } elseif { [get_files -quiet ${design_name}.bd] ne "" } { - # USE CASES: + # USE CASES: # 6) Current opened design, has components, but diff names, design_name exists in project. # 7) No opened design, design_name exists in project. @@ -129,6 +122,51 @@ if { $nRet != 0 } { return $nRet } +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +xilinx.com:ip:axi_gpio:2.0\ +br-automation.com:ip:axi_openmac:1.02a\ +xilinx.com:ip:clk_wiz:6.0\ +xilinx.com:ip:mdm:3.2\ +xilinx.com:ip:fit_timer:2.0\ +xilinx.com:ip:xlconstant:1.1\ +xilinx.com:ip:microblaze:10.0\ +xilinx.com:ip:axi_intc:4.1\ +xilinx.com:ip:xlconcat:2.1\ +xilinx.com:ip:proc_sys_reset:5.0\ +xilinx.com:ip:processing_system7:5.5\ +xilinx.com:ip:lmb_bram_if_cntlr:4.0\ +xilinx.com:ip:lmb_v10:3.0\ +xilinx.com:ip:blk_mem_gen:8.4\ +" + + set list_ips_missing "" + common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +if { $bCheckIPsPassed != 1 } { + common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + ################################################################## # DESIGN PROCs ################################################################## @@ -140,7 +178,7 @@ proc create_hier_cell_pcp_bram { parentCell nameHier } { variable script_folder if { $parentCell eq "" || $nameHier eq "" } { - catch {common::send_msg_id "BD_TCL-102" "ERROR" create_hier_cell_pcp_bram() - Empty argument(s)!"} + catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_pcp_bram() - Empty argument(s)!"} return } @@ -179,7 +217,7 @@ proc create_hier_cell_pcp_bram { parentCell nameHier } { # Create instance: dlmb_bram_if_cntlr, and set properties set dlmb_bram_if_cntlr [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 dlmb_bram_if_cntlr ] set_property -dict [ list \ -CONFIG.C_ECC {0} \ + CONFIG.C_ECC {0} \ ] $dlmb_bram_if_cntlr # Create instance: dlmb_v10, and set properties @@ -188,17 +226,23 @@ CONFIG.C_ECC {0} \ # Create instance: ilmb_bram_if_cntlr, and set properties set ilmb_bram_if_cntlr [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 ilmb_bram_if_cntlr ] set_property -dict [ list \ -CONFIG.C_ECC {0} \ + CONFIG.C_ECC {0} \ ] $ilmb_bram_if_cntlr # Create instance: ilmb_v10, and set properties set ilmb_v10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 ilmb_v10 ] # Create instance: lmb_bram, and set properties - set lmb_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.3 lmb_bram ] + set lmb_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 lmb_bram ] set_property -dict [ list \ -CONFIG.Memory_Type {True_Dual_Port_RAM} \ -CONFIG.use_bram_block {BRAM_Controller} \ + CONFIG.EN_SAFETY_CKT {false} \ + CONFIG.Enable_B {Use_ENB_Pin} \ + CONFIG.Memory_Type {True_Dual_Port_RAM} \ + CONFIG.Port_B_Clock {100} \ + CONFIG.Port_B_Enable_Rate {100} \ + CONFIG.Port_B_Write_Rate {50} \ + CONFIG.Use_RSTB_Pin {true} \ + CONFIG.use_bram_block {BRAM_Controller} \ ] $lmb_bram # Create interface connections @@ -223,6 +267,7 @@ CONFIG.use_bram_block {BRAM_Controller} \ proc create_root_design { parentCell } { variable script_folder + variable design_name if { $parentCell eq "" } { set parentCell [get_bd_cells /] @@ -261,8 +306,8 @@ proc create_root_design { parentCell } { set SMI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mdio_rtl:1.0 SMI ] set clk_in [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 clk_in ] set_property -dict [ list \ -CONFIG.FREQ_HZ {200000000} \ - ] $clk_in + CONFIG.FREQ_HZ {200000000} \ + ] $clk_in # Create ports set axi_powerlink_0_PHY0_PWRDWN_INT_n_pin [ create_bd_port -dir O -from 0 -to 0 axi_powerlink_0_PHY0_PWRDWN_INT_n_pin ] @@ -270,154 +315,117 @@ CONFIG.FREQ_HZ {200000000} \ set oSmi_nPhyRst [ create_bd_port -dir O -from 1 -to 0 -type rst oSmi_nPhyRst ] set reset [ create_bd_port -dir I -type rst reset ] set_property -dict [ list \ -CONFIG.POLARITY {ACTIVE_HIGH} \ + CONFIG.POLARITY {ACTIVE_HIGH} \ ] $reset # Create instance: BENCHMARK_PIO, and set properties set BENCHMARK_PIO [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 BENCHMARK_PIO ] set_property -dict [ list \ -CONFIG.C_GPIO_WIDTH {8} \ + CONFIG.C_GPIO_WIDTH {8} \ ] $BENCHMARK_PIO # Create instance: HOST_BENCHMARK_PIO, and set properties set HOST_BENCHMARK_PIO [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 HOST_BENCHMARK_PIO ] set_property -dict [ list \ -CONFIG.C_GPIO_WIDTH {8} \ + CONFIG.C_GPIO_WIDTH {8} \ ] $HOST_BENCHMARK_PIO # Create instance: LEDS_6BIT, and set properties set LEDS_6BIT [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 LEDS_6BIT ] set_property -dict [ list \ -CONFIG.C_ALL_OUTPUTS {1} \ -CONFIG.C_GPIO_WIDTH {6} \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_GPIO_WIDTH {6} \ ] $LEDS_6BIT # Create instance: Node_Switches, and set properties set Node_Switches [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 Node_Switches ] set_property -dict [ list \ -CONFIG.C_ALL_OUTPUTS {0} \ -CONFIG.C_GPIO_WIDTH {2} \ + CONFIG.C_ALL_OUTPUTS {0} \ + CONFIG.C_GPIO_WIDTH {2} \ ] $Node_Switches - # Create instance: pcp, and set properties - set pcp [ create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.6 pcp ] - set_property -dict [ list \ -CONFIG.C_BASE_VECTORS {0x00000000} \ -CONFIG.C_CACHE_BYTE_SIZE {32768} \ -CONFIG.C_DCACHE_ALWAYS_USED {1} \ -CONFIG.C_DCACHE_BASEADDR {0x0000000020000000} \ -CONFIG.C_DCACHE_BYTE_SIZE {16384} \ -CONFIG.C_DCACHE_HIGHADDR {0x000000003FFFFFFF} \ -CONFIG.C_DCACHE_LINE_LEN {8} \ -CONFIG.C_DEBUG_ENABLED {1} \ -CONFIG.C_D_AXI {1} \ -CONFIG.C_D_LMB {1} \ -CONFIG.C_ICACHE_ALWAYS_USED {1} \ -CONFIG.C_ICACHE_BASEADDR {0x20000000} \ -CONFIG.C_ICACHE_HIGHADDR {0x3FFFFFFF} \ -CONFIG.C_ICACHE_LINE_LEN {8} \ -CONFIG.C_I_LMB {1} \ -CONFIG.C_USE_BARREL {1} \ -CONFIG.C_USE_DCACHE {1} \ -CONFIG.C_USE_DIV {1} \ -CONFIG.C_USE_HW_MUL {1} \ -CONFIG.C_USE_ICACHE {1} \ -CONFIG.C_USE_INTERRUPT {2} \ -CONFIG.C_USE_MSR_INSTR {1} \ -CONFIG.C_USE_PCMP_INSTR {1} \ - ] $pcp - - # Create instance: pcp_bram - create_hier_cell_pcp_bram [current_bd_instance .] pcp_bram - # Create instance: POWERLINK_Led, and set properties set POWERLINK_Led [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 POWERLINK_Led ] set_property -dict [ list \ -CONFIG.C_ALL_OUTPUTS {1} \ -CONFIG.C_GPIO_WIDTH {2} \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_GPIO_WIDTH {2} \ ] $POWERLINK_Led # Create instance: axi4lite_0, and set properties set axi4lite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi4lite_0 ] set_property -dict [ list \ -CONFIG.NUM_MI {3} \ + CONFIG.NUM_MI {3} \ + CONFIG.SYNCHRONIZATION_STAGES {2} \ ] $axi4lite_0 # Create instance: axi4lite_mb_0, and set properties set axi4lite_mb_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi4lite_mb_0 ] set_property -dict [ list \ -CONFIG.NUM_MI {7} \ + CONFIG.NUM_MI {7} \ + CONFIG.SYNCHRONIZATION_STAGES {2} \ ] $axi4lite_mb_0 # Create instance: axi_0, and set properties set axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_0 ] set_property -dict [ list \ -CONFIG.NUM_MI {1} \ -CONFIG.NUM_SI {3} \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {3} \ + CONFIG.SYNCHRONIZATION_STAGES {2} \ ] $axi_0 # Create instance: axi_openmac_0, and set properties set axi_openmac_0 [ create_bd_cell -type ip -vlnv br-automation.com:ip:axi_openmac:1.02a axi_openmac_0 ] set_property -dict [ list \ -CONFIG.C_S_AXI_MAC_PKT_BASEADDR {0x60a00000} \ -CONFIG.C_S_AXI_MAC_PKT_HIGHADDR {0x60a0ffff} \ -CONFIG.C_S_AXI_MAC_PKT_MIN_SIZE {0x0000FFFF} \ -CONFIG.C_S_AXI_MAC_REG_ACLK_FREQ_HZ {500000000} \ -CONFIG.C_S_AXI_MAC_REG_CLK_XING {0} \ -CONFIG.C_S_AXI_MAC_REG_MIN_SIZE {0x0003FFFF} \ -CONFIG.C_S_AXI_MAC_REG_RNG0_BASEADDR {0x78800000} \ -CONFIG.C_S_AXI_MAC_REG_RNG0_HIGHADDR {0x7880ffff} \ -CONFIG.C_S_AXI_MAC_REG_RNG1_BASEADDR {0x78820000} \ -CONFIG.C_S_AXI_MAC_REG_RNG1_HIGHADDR {0x7882ffff} \ -CONFIG.gDmaBurstCountWidth {3} \ -CONFIG.gEnableDmaObserver {1} \ -CONFIG.gPacketBufferLocRx {2} \ -CONFIG.gPacketBufferLog2Size {14} \ -CONFIG.gPhyPortCount {2} \ -CONFIG.gPhyPortType {2} \ -CONFIG.gSmiPortCount {2} \ -CONFIG.gTimerEnablePulse {1} \ -CONFIG.gui_extraSmi {1} \ -CONFIG.gui_phyCount {2} \ -CONFIG.gui_phyType {2} \ -CONFIG.gui_rxBufLoc {2} \ -CONFIG.gui_tmrPulse {1} \ -CONFIG.gui_txBufSize {16} \ + CONFIG.C_S_AXI_MAC_PKT_BASEADDR {0x60a00000} \ + CONFIG.C_S_AXI_MAC_PKT_HIGHADDR {0x60a0ffff} \ + CONFIG.C_S_AXI_MAC_PKT_MIN_SIZE {0x0000FFFF} \ + CONFIG.C_S_AXI_MAC_REG_ACLK_FREQ_HZ {500000000} \ + CONFIG.C_S_AXI_MAC_REG_CLK_XING {0} \ + CONFIG.C_S_AXI_MAC_REG_MIN_SIZE {0x0003FFFF} \ + CONFIG.C_S_AXI_MAC_REG_RNG0_BASEADDR {0x78800000} \ + CONFIG.C_S_AXI_MAC_REG_RNG0_HIGHADDR {0x7880ffff} \ + CONFIG.C_S_AXI_MAC_REG_RNG1_BASEADDR {0x78820000} \ + CONFIG.C_S_AXI_MAC_REG_RNG1_HIGHADDR {0x7882ffff} \ + CONFIG.gDmaBurstCountWidth {3} \ + CONFIG.gEnableDmaObserver {1} \ + CONFIG.gPacketBufferLocRx {2} \ + CONFIG.gPacketBufferLog2Size {14} \ + CONFIG.gPhyPortCount {2} \ + CONFIG.gPhyPortType {2} \ + CONFIG.gSmiPortCount {2} \ + CONFIG.gTimerEnablePulse {1} \ + CONFIG.gui_extraSmi {1} \ + CONFIG.gui_phyCount {2} \ + CONFIG.gui_phyType {2} \ + CONFIG.gui_rxBufLoc {2} \ + CONFIG.gui_tmrPulse {1} \ + CONFIG.gui_txBufSize {16} \ ] $axi_openmac_0 # Create instance: clock_generator, and set properties - set clock_generator [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.3 clock_generator ] - set_property -dict [ list \ -CONFIG.CLKIN1_JITTER_PS {50.0} \ -CONFIG.CLKOUT1_JITTER {112.316} \ -CONFIG.CLKOUT1_PHASE_ERROR {89.971} \ -CONFIG.CLKOUT2_JITTER {129.198} \ -CONFIG.CLKOUT2_PHASE_ERROR {89.971} \ -CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {50} \ -CONFIG.CLKOUT2_USED {true} \ -CONFIG.CLK_IN1_BOARD_INTERFACE {sys_diff_clock} \ -CONFIG.MMCM_CLKFBOUT_MULT_F {5.000} \ -CONFIG.MMCM_CLKIN1_PERIOD {5.0} \ -CONFIG.MMCM_CLKIN2_PERIOD {10.0} \ -CONFIG.MMCM_CLKOUT0_DIVIDE_F {10.000} \ -CONFIG.MMCM_CLKOUT1_DIVIDE {20} \ -CONFIG.MMCM_COMPENSATION {ZHOLD} \ -CONFIG.MMCM_DIVCLK_DIVIDE {1} \ -CONFIG.NUM_OUT_CLKS {2} \ -CONFIG.PRIM_SOURCE {Differential_clock_capable_pin} \ - ] $clock_generator - - # Need to retain value_src of defaults + set clock_generator [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clock_generator ] set_property -dict [ list \ -CONFIG.MMCM_CLKIN2_PERIOD.VALUE_SRC {DEFAULT} \ -CONFIG.MMCM_CLKOUT0_DIVIDE_F.VALUE_SRC {DEFAULT} \ -CONFIG.MMCM_COMPENSATION.VALUE_SRC {DEFAULT} \ + CONFIG.CLKIN1_JITTER_PS {50.0} \ + CONFIG.CLKOUT1_JITTER {112.316} \ + CONFIG.CLKOUT1_PHASE_ERROR {89.971} \ + CONFIG.CLKOUT2_JITTER {129.198} \ + CONFIG.CLKOUT2_PHASE_ERROR {89.971} \ + CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {50} \ + CONFIG.CLKOUT2_USED {true} \ + CONFIG.CLK_IN1_BOARD_INTERFACE {sys_diff_clock} \ + CONFIG.MMCM_CLKFBOUT_MULT_F {5.000} \ + CONFIG.MMCM_CLKIN1_PERIOD {5.000} \ + CONFIG.MMCM_CLKIN2_PERIOD {10.0} \ + CONFIG.MMCM_CLKOUT1_DIVIDE {20} \ + CONFIG.MMCM_DIVCLK_DIVIDE {1} \ + CONFIG.NUM_OUT_CLKS {2} \ + CONFIG.PRIM_SOURCE {Differential_clock_capable_pin} \ ] $clock_generator # Create instance: debug_module, and set properties set debug_module [ create_bd_cell -type ip -vlnv xilinx.com:ip:mdm:3.2 debug_module ] set_property -dict [ list \ -CONFIG.C_USE_UART {1} \ + CONFIG.C_USE_UART {1} \ ] $debug_module # Create instance: fit_timer_0, and set properties @@ -429,22 +437,53 @@ CONFIG.C_USE_UART {1} \ # Create instance: net_vcc_phy1, and set properties set net_vcc_phy1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 net_vcc_phy1 ] + # Create instance: pcp, and set properties + set pcp [ create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:10.0 pcp ] + set_property -dict [ list \ + CONFIG.C_BASE_VECTORS {0x00000000} \ + CONFIG.C_CACHE_BYTE_SIZE {32768} \ + CONFIG.C_DCACHE_ALWAYS_USED {1} \ + CONFIG.C_DCACHE_BASEADDR {0x0000000020000000} \ + CONFIG.C_DCACHE_BYTE_SIZE {16384} \ + CONFIG.C_DCACHE_HIGHADDR {0x000000003FFFFFFF} \ + CONFIG.C_DCACHE_LINE_LEN {8} \ + CONFIG.C_DEBUG_ENABLED {1} \ + CONFIG.C_D_AXI {1} \ + CONFIG.C_D_LMB {1} \ + CONFIG.C_ICACHE_ALWAYS_USED {1} \ + CONFIG.C_ICACHE_BASEADDR {0x0000000020000000} \ + CONFIG.C_ICACHE_HIGHADDR {0x000000003FFFFFFF} \ + CONFIG.C_ICACHE_LINE_LEN {8} \ + CONFIG.C_I_LMB {1} \ + CONFIG.C_USE_BARREL {1} \ + CONFIG.C_USE_DCACHE {1} \ + CONFIG.C_USE_DIV {1} \ + CONFIG.C_USE_HW_MUL {1} \ + CONFIG.C_USE_ICACHE {1} \ + CONFIG.C_USE_INTERRUPT {2} \ + CONFIG.C_USE_MSR_INSTR {1} \ + CONFIG.C_USE_PCMP_INSTR {1} \ + ] $pcp + + # Create instance: pcp_bram + create_hier_cell_pcp_bram [current_bd_instance .] pcp_bram + # Create instance: pcp_intc, and set properties set pcp_intc [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 pcp_intc ] set_property -dict [ list \ -CONFIG.C_HAS_FAST {1} \ + CONFIG.C_HAS_FAST {1} \ ] $pcp_intc # Create instance: pcp_xlconcat, and set properties set pcp_xlconcat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pcp_xlconcat ] set_property -dict [ list \ -CONFIG.NUM_PORTS {3} \ + CONFIG.NUM_PORTS {3} \ ] $pcp_xlconcat # Create instance: proc_sys_rst, and set properties set proc_sys_rst [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_rst ] set_property -dict [ list \ -CONFIG.C_AUX_RESET_HIGH {0} \ + CONFIG.C_AUX_RESET_HIGH {0} \ ] $proc_sys_rst # Create instance: proc_sys_rst1, and set properties @@ -453,1286 +492,828 @@ CONFIG.C_AUX_RESET_HIGH {0} \ # Create instance: processing_system7_0, and set properties set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ] set_property -dict [ list \ -CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {23.809523} \ -CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \ -CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {25.000000} \ -CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {125.000000} \ -CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \ -CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \ -CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \ -CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \ -CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \ -CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \ -CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {50.000000} \ -CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \ -CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \ -CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \ -CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {50.000000} \ -CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \ -CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {666.666666} \ -CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \ -CONFIG.PCW_CAN0_CAN0_IO {MIO 46 .. 47} \ -CONFIG.PCW_CAN0_GRP_CLK_ENABLE {0} \ -CONFIG.PCW_CAN0_GRP_CLK_IO {} \ -CONFIG.PCW_CAN1_GRP_CLK_ENABLE {0} \ -CONFIG.PCW_CAN1_GRP_CLK_IO {} \ -CONFIG.PCW_DDR_PRIORITY_READPORT_1 {} \ -CONFIG.PCW_DDR_PRIORITY_READPORT_3 {} \ -CONFIG.PCW_DDR_PRIORITY_WRITEPORT_1 {} \ -CONFIG.PCW_DDR_PRIORITY_WRITEPORT_3 {} \ -CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {0} \ -CONFIG.PCW_ENET1_GRP_MDIO_IO {} \ -CONFIG.PCW_ENET_RESET_ENABLE {1} \ -CONFIG.PCW_ENET_RESET_POLARITY {Active Low} \ -CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \ -CONFIG.PCW_EN_4K_TIMER {0} \ -CONFIG.PCW_EN_CAN0 {1} \ -CONFIG.PCW_EN_EMIO_GPIO {1} \ -CONFIG.PCW_EN_EMIO_TTC0 {1} \ -CONFIG.PCW_EN_ENET0 {1} \ -CONFIG.PCW_EN_I2C0 {1} \ -CONFIG.PCW_EN_QSPI {1} \ -CONFIG.PCW_EN_SDIO0 {1} \ -CONFIG.PCW_EN_TTC0 {1} \ -CONFIG.PCW_EN_UART1 {1} \ -CONFIG.PCW_EN_USB0 {1} \ -CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC {IO PLL} \ -CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \ -CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {2} \ -CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC {IO PLL} \ -CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \ -CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \ -CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC {IO PLL} \ -CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \ -CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \ -CONFIG.PCW_FCLK3_PERIPHERAL_CLKSRC {IO PLL} \ -CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \ -CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \ -CONFIG.PCW_FCLK_CLK0_BUF {true} \ -CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \ -CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {50} \ -CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {50} \ -CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {50} \ -CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \ -CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1} \ -CONFIG.PCW_GPIO_EMIO_GPIO_IO {1} \ -CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {1} \ -CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \ -CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \ -CONFIG.PCW_GPIO_PERIPHERAL_ENABLE {0} \ -CONFIG.PCW_I2C0_GRP_INT_ENABLE {0} \ -CONFIG.PCW_I2C0_GRP_INT_IO {} \ -CONFIG.PCW_I2C1_I2C1_IO {} \ -CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {111.111115} \ -CONFIG.PCW_I2C_RESET_ENABLE {1} \ -CONFIG.PCW_I2C_RESET_POLARITY {Active Low} \ -CONFIG.PCW_I2C_RESET_SELECT {Share reset pin} \ -CONFIG.PCW_IOPLL_CTRL_FBDIV {30} \ -CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} \ -CONFIG.PCW_IRQ_F2P_INTR {1} \ -CONFIG.PCW_MIO_0_DIRECTION {in} \ -CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_0_PULLUP {enabled} \ -CONFIG.PCW_MIO_0_SLEW {slow} \ -CONFIG.PCW_MIO_10_DIRECTION {inout} \ -CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_10_PULLUP {enabled} \ -CONFIG.PCW_MIO_10_SLEW {slow} \ -CONFIG.PCW_MIO_11_DIRECTION {out} \ -CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_11_PULLUP {enabled} \ -CONFIG.PCW_MIO_11_SLEW {slow} \ -CONFIG.PCW_MIO_12_DIRECTION {inout} \ -CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_12_PULLUP {enabled} \ -CONFIG.PCW_MIO_12_SLEW {slow} \ -CONFIG.PCW_MIO_13_DIRECTION {out} \ -CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_13_PULLUP {enabled} \ -CONFIG.PCW_MIO_13_SLEW {slow} \ -CONFIG.PCW_MIO_14_DIRECTION {inout} \ -CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_14_PULLUP {enabled} \ -CONFIG.PCW_MIO_14_SLEW {slow} \ -CONFIG.PCW_MIO_15_DIRECTION {in} \ -CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_15_PULLUP {enabled} \ -CONFIG.PCW_MIO_15_SLEW {slow} \ -CONFIG.PCW_MIO_16_DIRECTION {out} \ -CONFIG.PCW_MIO_16_IOTYPE {HSTL 1.8V} \ -CONFIG.PCW_MIO_16_PULLUP {disabled} \ -CONFIG.PCW_MIO_16_SLEW {slow} \ -CONFIG.PCW_MIO_17_DIRECTION {out} \ -CONFIG.PCW_MIO_17_IOTYPE {HSTL 1.8V} \ -CONFIG.PCW_MIO_17_PULLUP {disabled} \ -CONFIG.PCW_MIO_17_SLEW {slow} \ -CONFIG.PCW_MIO_18_DIRECTION {out} \ -CONFIG.PCW_MIO_18_IOTYPE {HSTL 1.8V} \ -CONFIG.PCW_MIO_18_PULLUP {disabled} \ -CONFIG.PCW_MIO_18_SLEW {slow} \ -CONFIG.PCW_MIO_19_DIRECTION {out} \ -CONFIG.PCW_MIO_19_IOTYPE {HSTL 1.8V} \ -CONFIG.PCW_MIO_19_PULLUP {disabled} \ -CONFIG.PCW_MIO_19_SLEW {slow} \ -CONFIG.PCW_MIO_1_DIRECTION {out} \ -CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_1_PULLUP {enabled} \ -CONFIG.PCW_MIO_1_SLEW {slow} \ -CONFIG.PCW_MIO_20_DIRECTION {out} \ -CONFIG.PCW_MIO_20_IOTYPE {HSTL 1.8V} \ -CONFIG.PCW_MIO_20_PULLUP {disabled} \ -CONFIG.PCW_MIO_20_SLEW {slow} \ -CONFIG.PCW_MIO_21_DIRECTION {out} \ -CONFIG.PCW_MIO_21_IOTYPE {HSTL 1.8V} \ -CONFIG.PCW_MIO_21_PULLUP {disabled} \ -CONFIG.PCW_MIO_21_SLEW {slow} \ -CONFIG.PCW_MIO_22_DIRECTION {in} \ -CONFIG.PCW_MIO_22_IOTYPE {HSTL 1.8V} \ -CONFIG.PCW_MIO_22_PULLUP {disabled} \ -CONFIG.PCW_MIO_22_SLEW {slow} \ -CONFIG.PCW_MIO_23_DIRECTION {in} \ -CONFIG.PCW_MIO_23_IOTYPE {HSTL 1.8V} \ -CONFIG.PCW_MIO_23_PULLUP {disabled} \ -CONFIG.PCW_MIO_23_SLEW {slow} \ -CONFIG.PCW_MIO_24_DIRECTION {in} \ -CONFIG.PCW_MIO_24_IOTYPE {HSTL 1.8V} \ -CONFIG.PCW_MIO_24_PULLUP {disabled} \ -CONFIG.PCW_MIO_24_SLEW {slow} \ -CONFIG.PCW_MIO_25_DIRECTION {in} \ -CONFIG.PCW_MIO_25_IOTYPE {HSTL 1.8V} \ -CONFIG.PCW_MIO_25_PULLUP {disabled} \ -CONFIG.PCW_MIO_25_SLEW {slow} \ -CONFIG.PCW_MIO_26_DIRECTION {in} \ -CONFIG.PCW_MIO_26_IOTYPE {HSTL 1.8V} \ -CONFIG.PCW_MIO_26_PULLUP {disabled} \ -CONFIG.PCW_MIO_26_SLEW {slow} \ -CONFIG.PCW_MIO_27_DIRECTION {in} \ -CONFIG.PCW_MIO_27_IOTYPE {HSTL 1.8V} \ -CONFIG.PCW_MIO_27_PULLUP {disabled} \ -CONFIG.PCW_MIO_27_SLEW {slow} \ -CONFIG.PCW_MIO_28_DIRECTION {inout} \ -CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_28_PULLUP {disabled} \ -CONFIG.PCW_MIO_28_SLEW {slow} \ -CONFIG.PCW_MIO_29_DIRECTION {in} \ -CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_29_PULLUP {disabled} \ -CONFIG.PCW_MIO_29_SLEW {slow} \ -CONFIG.PCW_MIO_2_DIRECTION {inout} \ -CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_2_PULLUP {disabled} \ -CONFIG.PCW_MIO_2_SLEW {slow} \ -CONFIG.PCW_MIO_30_DIRECTION {out} \ -CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_30_PULLUP {disabled} \ -CONFIG.PCW_MIO_30_SLEW {slow} \ -CONFIG.PCW_MIO_31_DIRECTION {in} \ -CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_31_PULLUP {disabled} \ -CONFIG.PCW_MIO_31_SLEW {slow} \ -CONFIG.PCW_MIO_32_DIRECTION {inout} \ -CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_32_PULLUP {disabled} \ -CONFIG.PCW_MIO_32_SLEW {slow} \ -CONFIG.PCW_MIO_33_DIRECTION {inout} \ -CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_33_PULLUP {disabled} \ -CONFIG.PCW_MIO_33_SLEW {slow} \ -CONFIG.PCW_MIO_34_DIRECTION {inout} \ -CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_34_PULLUP {disabled} \ -CONFIG.PCW_MIO_34_SLEW {slow} \ -CONFIG.PCW_MIO_35_DIRECTION {inout} \ -CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_35_PULLUP {disabled} \ -CONFIG.PCW_MIO_35_SLEW {slow} \ -CONFIG.PCW_MIO_36_DIRECTION {in} \ -CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_36_PULLUP {disabled} \ -CONFIG.PCW_MIO_36_SLEW {slow} \ -CONFIG.PCW_MIO_37_DIRECTION {inout} \ -CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_37_PULLUP {disabled} \ -CONFIG.PCW_MIO_37_SLEW {slow} \ -CONFIG.PCW_MIO_38_DIRECTION {inout} \ -CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_38_PULLUP {disabled} \ -CONFIG.PCW_MIO_38_SLEW {slow} \ -CONFIG.PCW_MIO_39_DIRECTION {inout} \ -CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_39_PULLUP {disabled} \ -CONFIG.PCW_MIO_39_SLEW {slow} \ -CONFIG.PCW_MIO_3_DIRECTION {inout} \ -CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_3_PULLUP {disabled} \ -CONFIG.PCW_MIO_3_SLEW {slow} \ -CONFIG.PCW_MIO_40_DIRECTION {inout} \ -CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_40_PULLUP {disabled} \ -CONFIG.PCW_MIO_40_SLEW {slow} \ -CONFIG.PCW_MIO_41_DIRECTION {inout} \ -CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_41_PULLUP {disabled} \ -CONFIG.PCW_MIO_41_SLEW {slow} \ -CONFIG.PCW_MIO_42_DIRECTION {inout} \ -CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_42_PULLUP {disabled} \ -CONFIG.PCW_MIO_42_SLEW {slow} \ -CONFIG.PCW_MIO_43_DIRECTION {inout} \ -CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_43_PULLUP {disabled} \ -CONFIG.PCW_MIO_43_SLEW {slow} \ -CONFIG.PCW_MIO_44_DIRECTION {inout} \ -CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_44_PULLUP {disabled} \ -CONFIG.PCW_MIO_44_SLEW {slow} \ -CONFIG.PCW_MIO_45_DIRECTION {inout} \ -CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_45_PULLUP {disabled} \ -CONFIG.PCW_MIO_45_SLEW {slow} \ -CONFIG.PCW_MIO_46_DIRECTION {in} \ -CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_46_PULLUP {enabled} \ -CONFIG.PCW_MIO_46_SLEW {slow} \ -CONFIG.PCW_MIO_47_DIRECTION {out} \ -CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_47_PULLUP {enabled} \ -CONFIG.PCW_MIO_47_SLEW {slow} \ -CONFIG.PCW_MIO_48_DIRECTION {out} \ -CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_48_PULLUP {disabled} \ -CONFIG.PCW_MIO_48_SLEW {slow} \ -CONFIG.PCW_MIO_49_DIRECTION {in} \ -CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_49_PULLUP {disabled} \ -CONFIG.PCW_MIO_49_SLEW {slow} \ -CONFIG.PCW_MIO_4_DIRECTION {inout} \ -CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_4_PULLUP {disabled} \ -CONFIG.PCW_MIO_4_SLEW {slow} \ -CONFIG.PCW_MIO_50_DIRECTION {inout} \ -CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_50_PULLUP {enabled} \ -CONFIG.PCW_MIO_50_SLEW {slow} \ -CONFIG.PCW_MIO_51_DIRECTION {inout} \ -CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_51_PULLUP {enabled} \ -CONFIG.PCW_MIO_51_SLEW {slow} \ -CONFIG.PCW_MIO_52_DIRECTION {out} \ -CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_52_PULLUP {disabled} \ -CONFIG.PCW_MIO_52_SLEW {slow} \ -CONFIG.PCW_MIO_53_DIRECTION {inout} \ -CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_53_PULLUP {disabled} \ -CONFIG.PCW_MIO_53_SLEW {slow} \ -CONFIG.PCW_MIO_5_DIRECTION {inout} \ -CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_5_PULLUP {disabled} \ -CONFIG.PCW_MIO_5_SLEW {slow} \ -CONFIG.PCW_MIO_6_DIRECTION {out} \ -CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_6_PULLUP {disabled} \ -CONFIG.PCW_MIO_6_SLEW {slow} \ -CONFIG.PCW_MIO_7_DIRECTION {out} \ -CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_7_PULLUP {disabled} \ -CONFIG.PCW_MIO_7_SLEW {slow} \ -CONFIG.PCW_MIO_8_DIRECTION {out} \ -CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_8_PULLUP {disabled} \ -CONFIG.PCW_MIO_8_SLEW {slow} \ -CONFIG.PCW_MIO_9_DIRECTION {inout} \ -CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_9_PULLUP {enabled} \ -CONFIG.PCW_MIO_9_SLEW {slow} \ -CONFIG.PCW_MIO_TREE_PERIPHERALS {SD 0#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#USB Reset#Quad SPI Flash#GPIO#GPIO#ENET Reset#GPIO#I2C Reset#GPIO#SD 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#CAN 0#CAN 0#UART 1#UART 1#I2C 0#I2C 0#Enet 0#Enet 0} \ -CONFIG.PCW_MIO_TREE_SIGNALS {cd#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]#qspi0_sclk#reset#qspi_fbclk#gpio[9]#gpio[10]#reset#gpio[12]#reset#gpio[14]#wp#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#rx#tx#tx#rx#scl#sda#mdc#mdio} \ -CONFIG.PCW_NAND_CYCLES_T_AR {1} \ -CONFIG.PCW_NAND_CYCLES_T_CLR {1} \ -CONFIG.PCW_NAND_CYCLES_T_RC {11} \ -CONFIG.PCW_NAND_CYCLES_T_REA {1} \ -CONFIG.PCW_NAND_CYCLES_T_RR {1} \ -CONFIG.PCW_NAND_CYCLES_T_WC {11} \ -CONFIG.PCW_NAND_CYCLES_T_WP {1} \ -CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \ -CONFIG.PCW_NAND_GRP_D8_IO {} \ -CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \ -CONFIG.PCW_NOR_CS0_T_CEOE {1} \ -CONFIG.PCW_NOR_CS0_T_PC {1} \ -CONFIG.PCW_NOR_CS0_T_RC {11} \ -CONFIG.PCW_NOR_CS0_T_TR {1} \ -CONFIG.PCW_NOR_CS0_T_WC {11} \ -CONFIG.PCW_NOR_CS0_T_WP {1} \ -CONFIG.PCW_NOR_CS0_WE_TIME {0} \ -CONFIG.PCW_NOR_CS1_T_CEOE {1} \ -CONFIG.PCW_NOR_CS1_T_PC {1} \ -CONFIG.PCW_NOR_CS1_T_RC {11} \ -CONFIG.PCW_NOR_CS1_T_TR {1} \ -CONFIG.PCW_NOR_CS1_T_WC {11} \ -CONFIG.PCW_NOR_CS1_T_WP {1} \ -CONFIG.PCW_NOR_CS1_WE_TIME {0} \ -CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \ -CONFIG.PCW_NOR_GRP_A25_IO {} \ -CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \ -CONFIG.PCW_NOR_GRP_CS1_IO {} \ -CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \ -CONFIG.PCW_NOR_GRP_SRAM_CS1_IO {} \ -CONFIG.PCW_NOR_NOR_IO {} \ -CONFIG.PCW_PLL_BYPASSMODE_ENABLE {0} \ -CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 1.8V} \ -CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \ -CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {1} \ -CONFIG.PCW_QSPI_GRP_FBCLK_IO {MIO 8} \ -CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \ -CONFIG.PCW_QSPI_GRP_IO1_IO {} \ -CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC {IO PLL} \ -CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {5} \ -CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \ -CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} \ -CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \ -CONFIG.PCW_SD0_GRP_CD_ENABLE {1} \ -CONFIG.PCW_SD0_GRP_CD_IO {MIO 0} \ -CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \ -CONFIG.PCW_SD0_GRP_POW_IO {} \ -CONFIG.PCW_SD1_GRP_POW_ENABLE {0} \ -CONFIG.PCW_SD1_GRP_POW_IO {} \ -CONFIG.PCW_SD1_PERIPHERAL_ENABLE {0} \ -CONFIG.PCW_SD1_SD1_IO {} \ -CONFIG.PCW_SPI0_GRP_SS1_ENABLE {0} \ -CONFIG.PCW_SPI0_GRP_SS1_IO {} \ -CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {0} \ -CONFIG.PCW_SPI0_SPI0_IO {} \ -CONFIG.PCW_SPI1_GRP_SS1_ENABLE {0} \ -CONFIG.PCW_SPI1_GRP_SS1_IO {} \ -CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {0} \ -CONFIG.PCW_SPI1_SPI1_IO {} \ -CONFIG.PCW_TRACE_GRP_2BIT_ENABLE {0} \ -CONFIG.PCW_TRACE_GRP_2BIT_IO {} \ -CONFIG.PCW_TRACE_GRP_4BIT_ENABLE {0} \ -CONFIG.PCW_TRACE_GRP_4BIT_IO {} \ -CONFIG.PCW_TRACE_INTERNAL_WIDTH {2} \ -CONFIG.PCW_TRACE_PERIPHERAL_ENABLE {0} \ -CONFIG.PCW_TRACE_TRACE_IO {} \ -CONFIG.PCW_TTC_PERIPHERAL_FREQMHZ {50} \ -CONFIG.PCW_UART0_BAUD_RATE {115200} \ -CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \ -CONFIG.PCW_UART0_GRP_FULL_IO {} \ -CONFIG.PCW_UART1_BAUD_RATE {115200} \ -CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \ -CONFIG.PCW_UART1_GRP_FULL_IO {} \ -CONFIG.PCW_USB1_USB1_IO {} \ -CONFIG.preset {ZC702} \ + CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \ + CONFIG.PCW_ACT_CAN0_PERIPHERAL_FREQMHZ {23.8095} \ + CONFIG.PCW_ACT_CAN1_PERIPHERAL_FREQMHZ {23.8095} \ + CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {23.809523} \ + CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \ + CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {25.000000} \ + CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {125.000000} \ + CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \ + CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_I2C_PERIPHERAL_FREQMHZ {50} \ + CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \ + CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \ + CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {50.000000} \ + CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \ + CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC_PERIPHERAL_FREQMHZ {50} \ + CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {50.000000} \ + CONFIG.PCW_ACT_USB0_PERIPHERAL_FREQMHZ {60} \ + CONFIG.PCW_ACT_USB1_PERIPHERAL_FREQMHZ {60} \ + CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \ + CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {666.666666} \ + CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \ + CONFIG.PCW_CAN0_BASEADDR {0xE0008000} \ + CONFIG.PCW_CAN0_CAN0_IO {MIO 46 .. 47} \ + CONFIG.PCW_CAN0_GRP_CLK_ENABLE {0} \ + CONFIG.PCW_CAN0_HIGHADDR {0xE0008FFF} \ + CONFIG.PCW_CAN0_PERIPHERAL_CLKSRC {External} \ + CONFIG.PCW_CAN0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_CAN0_PERIPHERAL_FREQMHZ {-1} \ + CONFIG.PCW_CAN1_BASEADDR {0xE0009000} \ + CONFIG.PCW_CAN1_GRP_CLK_ENABLE {0} \ + CONFIG.PCW_CAN1_HIGHADDR {0xE0009FFF} \ + CONFIG.PCW_CAN1_PERIPHERAL_CLKSRC {External} \ + CONFIG.PCW_CAN1_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_CAN1_PERIPHERAL_FREQMHZ {-1} \ + CONFIG.PCW_CAN_PERIPHERAL_CLKSRC {IO PLL} \ + CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {7} \ + CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {6} \ + CONFIG.PCW_CAN_PERIPHERAL_FREQMHZ {23.8095} \ + CONFIG.PCW_CAN_PERIPHERAL_VALID {1} \ + CONFIG.PCW_CLK0_FREQ {100000000} \ + CONFIG.PCW_CLK1_FREQ {10000000} \ + CONFIG.PCW_CLK2_FREQ {10000000} \ + CONFIG.PCW_CLK3_FREQ {10000000} \ + CONFIG.PCW_CORE0_FIQ_INTR {0} \ + CONFIG.PCW_CORE0_IRQ_INTR {0} \ + CONFIG.PCW_CORE1_FIQ_INTR {0} \ + CONFIG.PCW_CORE1_IRQ_INTR {0} \ + CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} \ + CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \ + CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} \ + CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \ + CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {33.333333} \ + CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {DDR PLL} \ + CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \ + CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \ + CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ {10.159} \ + CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \ + CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \ + CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION {HPR(0)/LPR(32)} \ + CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL {15} \ + CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL {2} \ + CONFIG.PCW_DDR_PERIPHERAL_CLKSRC {DDR PLL} \ + CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \ + CONFIG.PCW_DDR_PORT0_HPR_ENABLE {0} \ + CONFIG.PCW_DDR_PORT1_HPR_ENABLE {0} \ + CONFIG.PCW_DDR_PORT2_HPR_ENABLE {0} \ + CONFIG.PCW_DDR_PORT3_HPR_ENABLE {0} \ + CONFIG.PCW_DDR_RAM_BASEADDR {0x00100000} \ + CONFIG.PCW_DDR_RAM_HIGHADDR {0x3FFFFFFF} \ + CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL {2} \ + CONFIG.PCW_DM_WIDTH {4} \ + CONFIG.PCW_DQS_WIDTH {4} \ + CONFIG.PCW_DQ_WIDTH {32} \ + CONFIG.PCW_ENET0_BASEADDR {0xE000B000} \ + CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \ + CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \ + CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \ + CONFIG.PCW_ENET0_HIGHADDR {0xE000BFFF} \ + CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \ + CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8} \ + CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {5} \ + CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {100 Mbps} \ + CONFIG.PCW_ENET0_RESET_ENABLE {1} \ + CONFIG.PCW_ENET0_RESET_IO {MIO 11} \ + CONFIG.PCW_ENET1_BASEADDR {0xE000C000} \ + CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {0} \ + CONFIG.PCW_ENET1_HIGHADDR {0xE000CFFF} \ + CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC {External} \ + CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {1000 Mbps} \ + CONFIG.PCW_ENET1_RESET_ENABLE {0} \ + CONFIG.PCW_ENET_RESET_ENABLE {1} \ + CONFIG.PCW_ENET_RESET_POLARITY {Active Low} \ + CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \ + CONFIG.PCW_EN_4K_TIMER {0} \ + CONFIG.PCW_EN_CAN0 {1} \ + CONFIG.PCW_EN_CAN1 {0} \ + CONFIG.PCW_EN_CLK0_PORT {1} \ + CONFIG.PCW_EN_CLK1_PORT {0} \ + CONFIG.PCW_EN_CLK2_PORT {0} \ + CONFIG.PCW_EN_CLK3_PORT {0} \ + CONFIG.PCW_EN_CLKTRIG0_PORT {0} \ + CONFIG.PCW_EN_CLKTRIG1_PORT {0} \ + CONFIG.PCW_EN_CLKTRIG2_PORT {0} \ + CONFIG.PCW_EN_CLKTRIG3_PORT {0} \ + CONFIG.PCW_EN_DDR {1} \ + CONFIG.PCW_EN_EMIO_CAN0 {0} \ + CONFIG.PCW_EN_EMIO_CAN1 {0} \ + CONFIG.PCW_EN_EMIO_CD_SDIO0 {0} \ + CONFIG.PCW_EN_EMIO_CD_SDIO1 {0} \ + CONFIG.PCW_EN_EMIO_ENET0 {0} \ + CONFIG.PCW_EN_EMIO_ENET1 {0} \ + CONFIG.PCW_EN_EMIO_GPIO {1} \ + CONFIG.PCW_EN_EMIO_I2C0 {0} \ + CONFIG.PCW_EN_EMIO_I2C1 {0} \ + CONFIG.PCW_EN_EMIO_MODEM_UART0 {0} \ + CONFIG.PCW_EN_EMIO_MODEM_UART1 {0} \ + CONFIG.PCW_EN_EMIO_PJTAG {0} \ + CONFIG.PCW_EN_EMIO_SDIO0 {0} \ + CONFIG.PCW_EN_EMIO_SDIO1 {0} \ + CONFIG.PCW_EN_EMIO_SPI0 {0} \ + CONFIG.PCW_EN_EMIO_SPI1 {0} \ + CONFIG.PCW_EN_EMIO_SRAM_INT {0} \ + CONFIG.PCW_EN_EMIO_TRACE {0} \ + CONFIG.PCW_EN_EMIO_TTC0 {1} \ + CONFIG.PCW_EN_EMIO_TTC1 {0} \ + CONFIG.PCW_EN_EMIO_UART0 {0} \ + CONFIG.PCW_EN_EMIO_UART1 {0} \ + CONFIG.PCW_EN_EMIO_WDT {0} \ + CONFIG.PCW_EN_EMIO_WP_SDIO0 {0} \ + CONFIG.PCW_EN_EMIO_WP_SDIO1 {0} \ + CONFIG.PCW_EN_ENET0 {1} \ + CONFIG.PCW_EN_ENET1 {0} \ + CONFIG.PCW_EN_GPIO {1} \ + CONFIG.PCW_EN_I2C0 {1} \ + CONFIG.PCW_EN_I2C1 {0} \ + CONFIG.PCW_EN_MODEM_UART0 {0} \ + CONFIG.PCW_EN_MODEM_UART1 {0} \ + CONFIG.PCW_EN_PJTAG {0} \ + CONFIG.PCW_EN_PTP_ENET0 {0} \ + CONFIG.PCW_EN_PTP_ENET1 {0} \ + CONFIG.PCW_EN_QSPI {1} \ + CONFIG.PCW_EN_RST0_PORT {1} \ + CONFIG.PCW_EN_RST1_PORT {0} \ + CONFIG.PCW_EN_RST2_PORT {0} \ + CONFIG.PCW_EN_RST3_PORT {0} \ + CONFIG.PCW_EN_SDIO0 {1} \ + CONFIG.PCW_EN_SDIO1 {0} \ + CONFIG.PCW_EN_SMC {0} \ + CONFIG.PCW_EN_SPI0 {0} \ + CONFIG.PCW_EN_SPI1 {0} \ + CONFIG.PCW_EN_TRACE {0} \ + CONFIG.PCW_EN_TTC0 {1} \ + CONFIG.PCW_EN_TTC1 {0} \ + CONFIG.PCW_EN_UART0 {0} \ + CONFIG.PCW_EN_UART1 {1} \ + CONFIG.PCW_EN_USB0 {1} \ + CONFIG.PCW_EN_USB1 {0} \ + CONFIG.PCW_EN_WDT {0} \ + CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC {IO PLL} \ + CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \ + CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {2} \ + CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC {IO PLL} \ + CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC {IO PLL} \ + CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_FCLK3_PERIPHERAL_CLKSRC {IO PLL} \ + CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_FCLK_CLK0_BUF {TRUE} \ + CONFIG.PCW_FCLK_CLK1_BUF {FALSE} \ + CONFIG.PCW_FCLK_CLK2_BUF {FALSE} \ + CONFIG.PCW_FCLK_CLK3_BUF {FALSE} \ + CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \ + CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {50} \ + CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {50} \ + CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {50} \ + CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \ + CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \ + CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \ + CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \ + CONFIG.PCW_FTM_CTI_IN0 {} \ + CONFIG.PCW_FTM_CTI_IN2 {} \ + CONFIG.PCW_FTM_CTI_OUT0 {} \ + CONFIG.PCW_FTM_CTI_OUT2 {} \ + CONFIG.PCW_GP0_EN_MODIFIABLE_TXN {0} \ + CONFIG.PCW_GP0_NUM_READ_THREADS {4} \ + CONFIG.PCW_GP0_NUM_WRITE_THREADS {4} \ + CONFIG.PCW_GP1_EN_MODIFIABLE_TXN {0} \ + CONFIG.PCW_GP1_NUM_READ_THREADS {4} \ + CONFIG.PCW_GP1_NUM_WRITE_THREADS {4} \ + CONFIG.PCW_GPIO_BASEADDR {0xE000A000} \ + CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1} \ + CONFIG.PCW_GPIO_EMIO_GPIO_IO {1} \ + CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {1} \ + CONFIG.PCW_GPIO_HIGHADDR {0xE000AFFF} \ + CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \ + CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \ + CONFIG.PCW_GPIO_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_I2C0_BASEADDR {0xE0004000} \ + CONFIG.PCW_I2C0_GRP_INT_ENABLE {0} \ + CONFIG.PCW_I2C0_HIGHADDR {0xE0004FFF} \ + CONFIG.PCW_I2C0_I2C0_IO {MIO 50 .. 51} \ + CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_I2C0_RESET_ENABLE {1} \ + CONFIG.PCW_I2C0_RESET_IO {MIO 13} \ + CONFIG.PCW_I2C1_BASEADDR {0xE0005000} \ + CONFIG.PCW_I2C1_GRP_INT_ENABLE {0} \ + CONFIG.PCW_I2C1_HIGHADDR {0xE0005FFF} \ + CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_I2C1_RESET_ENABLE {0} \ + CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_I2C_RESET_ENABLE {1} \ + CONFIG.PCW_I2C_RESET_POLARITY {Active Low} \ + CONFIG.PCW_I2C_RESET_SELECT {Share reset pin} \ + CONFIG.PCW_IMPORT_BOARD_PRESET {None} \ + CONFIG.PCW_INCLUDE_ACP_TRANS_CHECK {0} \ + CONFIG.PCW_INCLUDE_TRACE_BUFFER {0} \ + CONFIG.PCW_IOPLL_CTRL_FBDIV {30} \ + CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} \ + CONFIG.PCW_IRQ_F2P_INTR {1} \ + CONFIG.PCW_IRQ_F2P_MODE {DIRECT} \ + CONFIG.PCW_MIO_0_DIRECTION {in} \ + CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_0_PULLUP {enabled} \ + CONFIG.PCW_MIO_0_SLEW {slow} \ + CONFIG.PCW_MIO_10_DIRECTION {inout} \ + CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_10_PULLUP {enabled} \ + CONFIG.PCW_MIO_10_SLEW {slow} \ + CONFIG.PCW_MIO_11_DIRECTION {out} \ + CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_11_PULLUP {enabled} \ + CONFIG.PCW_MIO_11_SLEW {slow} \ + CONFIG.PCW_MIO_12_DIRECTION {inout} \ + CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_12_PULLUP {enabled} \ + CONFIG.PCW_MIO_12_SLEW {slow} \ + CONFIG.PCW_MIO_13_DIRECTION {out} \ + CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_13_PULLUP {enabled} \ + CONFIG.PCW_MIO_13_SLEW {slow} \ + CONFIG.PCW_MIO_14_DIRECTION {inout} \ + CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_14_PULLUP {enabled} \ + CONFIG.PCW_MIO_14_SLEW {slow} \ + CONFIG.PCW_MIO_15_DIRECTION {in} \ + CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_15_PULLUP {enabled} \ + CONFIG.PCW_MIO_15_SLEW {slow} \ + CONFIG.PCW_MIO_16_DIRECTION {out} \ + CONFIG.PCW_MIO_16_IOTYPE {HSTL 1.8V} \ + CONFIG.PCW_MIO_16_PULLUP {disabled} \ + CONFIG.PCW_MIO_16_SLEW {slow} \ + CONFIG.PCW_MIO_17_DIRECTION {out} \ + CONFIG.PCW_MIO_17_IOTYPE {HSTL 1.8V} \ + CONFIG.PCW_MIO_17_PULLUP {disabled} \ + CONFIG.PCW_MIO_17_SLEW {slow} \ + CONFIG.PCW_MIO_18_DIRECTION {out} \ + CONFIG.PCW_MIO_18_IOTYPE {HSTL 1.8V} \ + CONFIG.PCW_MIO_18_PULLUP {disabled} \ + CONFIG.PCW_MIO_18_SLEW {slow} \ + CONFIG.PCW_MIO_19_DIRECTION {out} \ + CONFIG.PCW_MIO_19_IOTYPE {HSTL 1.8V} \ + CONFIG.PCW_MIO_19_PULLUP {disabled} \ + CONFIG.PCW_MIO_19_SLEW {slow} \ + CONFIG.PCW_MIO_1_DIRECTION {out} \ + CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_1_PULLUP {enabled} \ + CONFIG.PCW_MIO_1_SLEW {slow} \ + CONFIG.PCW_MIO_20_DIRECTION {out} \ + CONFIG.PCW_MIO_20_IOTYPE {HSTL 1.8V} \ + CONFIG.PCW_MIO_20_PULLUP {disabled} \ + CONFIG.PCW_MIO_20_SLEW {slow} \ + CONFIG.PCW_MIO_21_DIRECTION {out} \ + CONFIG.PCW_MIO_21_IOTYPE {HSTL 1.8V} \ + CONFIG.PCW_MIO_21_PULLUP {disabled} \ + CONFIG.PCW_MIO_21_SLEW {slow} \ + CONFIG.PCW_MIO_22_DIRECTION {in} \ + CONFIG.PCW_MIO_22_IOTYPE {HSTL 1.8V} \ + CONFIG.PCW_MIO_22_PULLUP {disabled} \ + CONFIG.PCW_MIO_22_SLEW {slow} \ + CONFIG.PCW_MIO_23_DIRECTION {in} \ + CONFIG.PCW_MIO_23_IOTYPE {HSTL 1.8V} \ + CONFIG.PCW_MIO_23_PULLUP {disabled} \ + CONFIG.PCW_MIO_23_SLEW {slow} \ + CONFIG.PCW_MIO_24_DIRECTION {in} \ + CONFIG.PCW_MIO_24_IOTYPE {HSTL 1.8V} \ + CONFIG.PCW_MIO_24_PULLUP {disabled} \ + CONFIG.PCW_MIO_24_SLEW {slow} \ + CONFIG.PCW_MIO_25_DIRECTION {in} \ + CONFIG.PCW_MIO_25_IOTYPE {HSTL 1.8V} \ + CONFIG.PCW_MIO_25_PULLUP {disabled} \ + CONFIG.PCW_MIO_25_SLEW {slow} \ + CONFIG.PCW_MIO_26_DIRECTION {in} \ + CONFIG.PCW_MIO_26_IOTYPE {HSTL 1.8V} \ + CONFIG.PCW_MIO_26_PULLUP {disabled} \ + CONFIG.PCW_MIO_26_SLEW {slow} \ + CONFIG.PCW_MIO_27_DIRECTION {in} \ + CONFIG.PCW_MIO_27_IOTYPE {HSTL 1.8V} \ + CONFIG.PCW_MIO_27_PULLUP {disabled} \ + CONFIG.PCW_MIO_27_SLEW {slow} \ + CONFIG.PCW_MIO_28_DIRECTION {inout} \ + CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_28_PULLUP {disabled} \ + CONFIG.PCW_MIO_28_SLEW {slow} \ + CONFIG.PCW_MIO_29_DIRECTION {in} \ + CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_29_PULLUP {disabled} \ + CONFIG.PCW_MIO_29_SLEW {slow} \ + CONFIG.PCW_MIO_2_DIRECTION {inout} \ + CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_2_PULLUP {disabled} \ + CONFIG.PCW_MIO_2_SLEW {slow} \ + CONFIG.PCW_MIO_30_DIRECTION {out} \ + CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_30_PULLUP {disabled} \ + CONFIG.PCW_MIO_30_SLEW {slow} \ + CONFIG.PCW_MIO_31_DIRECTION {in} \ + CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_31_PULLUP {disabled} \ + CONFIG.PCW_MIO_31_SLEW {slow} \ + CONFIG.PCW_MIO_32_DIRECTION {inout} \ + CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_32_PULLUP {disabled} \ + CONFIG.PCW_MIO_32_SLEW {slow} \ + CONFIG.PCW_MIO_33_DIRECTION {inout} \ + CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_33_PULLUP {disabled} \ + CONFIG.PCW_MIO_33_SLEW {slow} \ + CONFIG.PCW_MIO_34_DIRECTION {inout} \ + CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_34_PULLUP {disabled} \ + CONFIG.PCW_MIO_34_SLEW {slow} \ + CONFIG.PCW_MIO_35_DIRECTION {inout} \ + CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_35_PULLUP {disabled} \ + CONFIG.PCW_MIO_35_SLEW {slow} \ + CONFIG.PCW_MIO_36_DIRECTION {in} \ + CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_36_PULLUP {disabled} \ + CONFIG.PCW_MIO_36_SLEW {slow} \ + CONFIG.PCW_MIO_37_DIRECTION {inout} \ + CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_37_PULLUP {disabled} \ + CONFIG.PCW_MIO_37_SLEW {slow} \ + CONFIG.PCW_MIO_38_DIRECTION {inout} \ + CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_38_PULLUP {disabled} \ + CONFIG.PCW_MIO_38_SLEW {slow} \ + CONFIG.PCW_MIO_39_DIRECTION {inout} \ + CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_39_PULLUP {disabled} \ + CONFIG.PCW_MIO_39_SLEW {slow} \ + CONFIG.PCW_MIO_3_DIRECTION {inout} \ + CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_3_PULLUP {disabled} \ + CONFIG.PCW_MIO_3_SLEW {slow} \ + CONFIG.PCW_MIO_40_DIRECTION {inout} \ + CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_40_PULLUP {disabled} \ + CONFIG.PCW_MIO_40_SLEW {slow} \ + CONFIG.PCW_MIO_41_DIRECTION {inout} \ + CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_41_PULLUP {disabled} \ + CONFIG.PCW_MIO_41_SLEW {slow} \ + CONFIG.PCW_MIO_42_DIRECTION {inout} \ + CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_42_PULLUP {disabled} \ + CONFIG.PCW_MIO_42_SLEW {slow} \ + CONFIG.PCW_MIO_43_DIRECTION {inout} \ + CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_43_PULLUP {disabled} \ + CONFIG.PCW_MIO_43_SLEW {slow} \ + CONFIG.PCW_MIO_44_DIRECTION {inout} \ + CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_44_PULLUP {disabled} \ + CONFIG.PCW_MIO_44_SLEW {slow} \ + CONFIG.PCW_MIO_45_DIRECTION {inout} \ + CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_45_PULLUP {disabled} \ + CONFIG.PCW_MIO_45_SLEW {slow} \ + CONFIG.PCW_MIO_46_DIRECTION {in} \ + CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_46_PULLUP {enabled} \ + CONFIG.PCW_MIO_46_SLEW {slow} \ + CONFIG.PCW_MIO_47_DIRECTION {out} \ + CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_47_PULLUP {enabled} \ + CONFIG.PCW_MIO_47_SLEW {slow} \ + CONFIG.PCW_MIO_48_DIRECTION {out} \ + CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_48_PULLUP {disabled} \ + CONFIG.PCW_MIO_48_SLEW {slow} \ + CONFIG.PCW_MIO_49_DIRECTION {in} \ + CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_49_PULLUP {disabled} \ + CONFIG.PCW_MIO_49_SLEW {slow} \ + CONFIG.PCW_MIO_4_DIRECTION {inout} \ + CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_4_PULLUP {disabled} \ + CONFIG.PCW_MIO_4_SLEW {slow} \ + CONFIG.PCW_MIO_50_DIRECTION {inout} \ + CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_50_PULLUP {enabled} \ + CONFIG.PCW_MIO_50_SLEW {slow} \ + CONFIG.PCW_MIO_51_DIRECTION {inout} \ + CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_51_PULLUP {enabled} \ + CONFIG.PCW_MIO_51_SLEW {slow} \ + CONFIG.PCW_MIO_52_DIRECTION {out} \ + CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_52_PULLUP {disabled} \ + CONFIG.PCW_MIO_52_SLEW {slow} \ + CONFIG.PCW_MIO_53_DIRECTION {inout} \ + CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_53_PULLUP {disabled} \ + CONFIG.PCW_MIO_53_SLEW {slow} \ + CONFIG.PCW_MIO_5_DIRECTION {inout} \ + CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_5_PULLUP {disabled} \ + CONFIG.PCW_MIO_5_SLEW {slow} \ + CONFIG.PCW_MIO_6_DIRECTION {out} \ + CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_6_PULLUP {disabled} \ + CONFIG.PCW_MIO_6_SLEW {slow} \ + CONFIG.PCW_MIO_7_DIRECTION {out} \ + CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_7_PULLUP {disabled} \ + CONFIG.PCW_MIO_7_SLEW {slow} \ + CONFIG.PCW_MIO_8_DIRECTION {out} \ + CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_8_PULLUP {disabled} \ + CONFIG.PCW_MIO_8_SLEW {slow} \ + CONFIG.PCW_MIO_9_DIRECTION {inout} \ + CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_9_PULLUP {enabled} \ + CONFIG.PCW_MIO_9_SLEW {slow} \ + CONFIG.PCW_MIO_PRIMITIVE {54} \ + CONFIG.PCW_MIO_TREE_PERIPHERALS {SD 0#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#USB Reset#Quad SPI Flash#GPIO#GPIO#ENET Reset#GPIO#I2C Reset#GPIO#SD 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#CAN 0#CAN 0#UART 1#UART 1#I2C 0#I2C 0#Enet 0#Enet 0} \ + CONFIG.PCW_MIO_TREE_SIGNALS {cd#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#reset#qspi_fbclk#gpio[9]#gpio[10]#reset#gpio[12]#reset#gpio[14]#wp#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#rx#tx#tx#rx#scl#sda#mdc#mdio} \ + CONFIG.PCW_M_AXI_GP0_ENABLE_STATIC_REMAP {0} \ + CONFIG.PCW_M_AXI_GP0_ID_WIDTH {12} \ + CONFIG.PCW_M_AXI_GP0_SUPPORT_NARROW_BURST {0} \ + CONFIG.PCW_M_AXI_GP0_THREAD_ID_WIDTH {12} \ + CONFIG.PCW_M_AXI_GP1_ENABLE_STATIC_REMAP {0} \ + CONFIG.PCW_M_AXI_GP1_ID_WIDTH {12} \ + CONFIG.PCW_M_AXI_GP1_SUPPORT_NARROW_BURST {0} \ + CONFIG.PCW_M_AXI_GP1_THREAD_ID_WIDTH {12} \ + CONFIG.PCW_NAND_CYCLES_T_AR {1} \ + CONFIG.PCW_NAND_CYCLES_T_CLR {1} \ + CONFIG.PCW_NAND_CYCLES_T_RC {11} \ + CONFIG.PCW_NAND_CYCLES_T_REA {1} \ + CONFIG.PCW_NAND_CYCLES_T_RR {1} \ + CONFIG.PCW_NAND_CYCLES_T_WC {11} \ + CONFIG.PCW_NAND_CYCLES_T_WP {1} \ + CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \ + CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_NOR_CS0_T_CEOE {1} \ + CONFIG.PCW_NOR_CS0_T_PC {1} \ + CONFIG.PCW_NOR_CS0_T_RC {11} \ + CONFIG.PCW_NOR_CS0_T_TR {1} \ + CONFIG.PCW_NOR_CS0_T_WC {11} \ + CONFIG.PCW_NOR_CS0_T_WP {1} \ + CONFIG.PCW_NOR_CS0_WE_TIME {0} \ + CONFIG.PCW_NOR_CS1_T_CEOE {1} \ + CONFIG.PCW_NOR_CS1_T_PC {1} \ + CONFIG.PCW_NOR_CS1_T_RC {11} \ + CONFIG.PCW_NOR_CS1_T_TR {1} \ + CONFIG.PCW_NOR_CS1_T_WC {11} \ + CONFIG.PCW_NOR_CS1_T_WP {1} \ + CONFIG.PCW_NOR_CS1_WE_TIME {0} \ + CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \ + CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \ + CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \ + CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \ + CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \ + CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \ + CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_NOR_SRAM_CS0_T_CEOE {1} \ + CONFIG.PCW_NOR_SRAM_CS0_T_PC {1} \ + CONFIG.PCW_NOR_SRAM_CS0_T_RC {11} \ + CONFIG.PCW_NOR_SRAM_CS0_T_TR {1} \ + CONFIG.PCW_NOR_SRAM_CS0_T_WC {11} \ + CONFIG.PCW_NOR_SRAM_CS0_T_WP {1} \ + CONFIG.PCW_NOR_SRAM_CS0_WE_TIME {0} \ + CONFIG.PCW_NOR_SRAM_CS1_T_CEOE {1} \ + CONFIG.PCW_NOR_SRAM_CS1_T_PC {1} \ + CONFIG.PCW_NOR_SRAM_CS1_T_RC {11} \ + CONFIG.PCW_NOR_SRAM_CS1_T_TR {1} \ + CONFIG.PCW_NOR_SRAM_CS1_T_WC {11} \ + CONFIG.PCW_NOR_SRAM_CS1_T_WP {1} \ + CONFIG.PCW_NOR_SRAM_CS1_WE_TIME {0} \ + CONFIG.PCW_OVERRIDE_BASIC_CLOCK {0} \ + CONFIG.PCW_P2F_CAN0_INTR {0} \ + CONFIG.PCW_P2F_CAN1_INTR {0} \ + CONFIG.PCW_P2F_CTI_INTR {0} \ + CONFIG.PCW_P2F_DMAC0_INTR {0} \ + CONFIG.PCW_P2F_DMAC1_INTR {0} \ + CONFIG.PCW_P2F_DMAC2_INTR {0} \ + CONFIG.PCW_P2F_DMAC3_INTR {0} \ + CONFIG.PCW_P2F_DMAC4_INTR {0} \ + CONFIG.PCW_P2F_DMAC5_INTR {0} \ + CONFIG.PCW_P2F_DMAC6_INTR {0} \ + CONFIG.PCW_P2F_DMAC7_INTR {0} \ + CONFIG.PCW_P2F_DMAC_ABORT_INTR {0} \ + CONFIG.PCW_P2F_ENET0_INTR {0} \ + CONFIG.PCW_P2F_ENET1_INTR {0} \ + CONFIG.PCW_P2F_GPIO_INTR {0} \ + CONFIG.PCW_P2F_I2C0_INTR {0} \ + CONFIG.PCW_P2F_I2C1_INTR {0} \ + CONFIG.PCW_P2F_QSPI_INTR {0} \ + CONFIG.PCW_P2F_SDIO0_INTR {0} \ + CONFIG.PCW_P2F_SDIO1_INTR {0} \ + CONFIG.PCW_P2F_SMC_INTR {0} \ + CONFIG.PCW_P2F_SPI0_INTR {0} \ + CONFIG.PCW_P2F_SPI1_INTR {0} \ + CONFIG.PCW_P2F_UART0_INTR {0} \ + CONFIG.PCW_P2F_UART1_INTR {0} \ + CONFIG.PCW_P2F_USB0_INTR {0} \ + CONFIG.PCW_P2F_USB1_INTR {0} \ + CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0 {0.063} \ + CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1 {0.062} \ + CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2 {0.065} \ + CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3 {0.083} \ + CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 {-0.007} \ + CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 {-0.010} \ + CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 {-0.006} \ + CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 {-0.048} \ + CONFIG.PCW_PACKAGE_NAME {clg484} \ + CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC {IO PLL} \ + CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \ + CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ {200} \ + CONFIG.PCW_PERIPHERAL_BOARD_PRESET {part0} \ + CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_PLL_BYPASSMODE_ENABLE {0} \ + CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 1.8V} \ + CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \ + CONFIG.PCW_PS7_SI_REV {PRODUCTION} \ + CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {1} \ + CONFIG.PCW_QSPI_GRP_FBCLK_IO {MIO 8} \ + CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \ + CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \ + CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \ + CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \ + CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS {0xFCFFFFFF} \ + CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC {IO PLL} \ + CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {5} \ + CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} \ + CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \ + CONFIG.PCW_SD0_GRP_CD_ENABLE {1} \ + CONFIG.PCW_SD0_GRP_CD_IO {MIO 0} \ + CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \ + CONFIG.PCW_SD0_GRP_WP_ENABLE {1} \ + CONFIG.PCW_SD0_GRP_WP_IO {MIO 15} \ + CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \ + CONFIG.PCW_SD1_GRP_CD_ENABLE {0} \ + CONFIG.PCW_SD1_GRP_POW_ENABLE {0} \ + CONFIG.PCW_SD1_GRP_WP_ENABLE {0} \ + CONFIG.PCW_SD1_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_SDIO0_BASEADDR {0xE0100000} \ + CONFIG.PCW_SDIO0_HIGHADDR {0xE0100FFF} \ + CONFIG.PCW_SDIO1_BASEADDR {0xE0101000} \ + CONFIG.PCW_SDIO1_HIGHADDR {0xE0101FFF} \ + CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC {IO PLL} \ + CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {20} \ + CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50} \ + CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \ + CONFIG.PCW_SINGLE_QSPI_DATA_MODE {x4} \ + CONFIG.PCW_SMC_CYCLE_T0 {NA} \ + CONFIG.PCW_SMC_CYCLE_T1 {NA} \ + CONFIG.PCW_SMC_CYCLE_T2 {NA} \ + CONFIG.PCW_SMC_CYCLE_T3 {NA} \ + CONFIG.PCW_SMC_CYCLE_T4 {NA} \ + CONFIG.PCW_SMC_CYCLE_T5 {NA} \ + CONFIG.PCW_SMC_CYCLE_T6 {NA} \ + CONFIG.PCW_SMC_PERIPHERAL_CLKSRC {IO PLL} \ + CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ {100} \ + CONFIG.PCW_SMC_PERIPHERAL_VALID {0} \ + CONFIG.PCW_SPI0_BASEADDR {0xE0006000} \ + CONFIG.PCW_SPI0_GRP_SS0_ENABLE {0} \ + CONFIG.PCW_SPI0_GRP_SS1_ENABLE {0} \ + CONFIG.PCW_SPI0_GRP_SS2_ENABLE {0} \ + CONFIG.PCW_SPI0_HIGHADDR {0xE0006FFF} \ + CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_SPI1_BASEADDR {0xE0007000} \ + CONFIG.PCW_SPI1_GRP_SS0_ENABLE {0} \ + CONFIG.PCW_SPI1_GRP_SS1_ENABLE {0} \ + CONFIG.PCW_SPI1_GRP_SS2_ENABLE {0} \ + CONFIG.PCW_SPI1_HIGHADDR {0xE0007FFF} \ + CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_SPI_PERIPHERAL_CLKSRC {IO PLL} \ + CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ {166.666666} \ + CONFIG.PCW_SPI_PERIPHERAL_VALID {0} \ + CONFIG.PCW_S_AXI_ACP_ARUSER_VAL {31} \ + CONFIG.PCW_S_AXI_ACP_AWUSER_VAL {31} \ + CONFIG.PCW_S_AXI_ACP_ID_WIDTH {3} \ + CONFIG.PCW_S_AXI_GP0_ID_WIDTH {6} \ + CONFIG.PCW_S_AXI_GP1_ID_WIDTH {6} \ + CONFIG.PCW_S_AXI_HP0_DATA_WIDTH {64} \ + CONFIG.PCW_S_AXI_HP0_ID_WIDTH {6} \ + CONFIG.PCW_S_AXI_HP1_DATA_WIDTH {64} \ + CONFIG.PCW_S_AXI_HP1_ID_WIDTH {6} \ + CONFIG.PCW_S_AXI_HP2_DATA_WIDTH {64} \ + CONFIG.PCW_S_AXI_HP2_ID_WIDTH {6} \ + CONFIG.PCW_S_AXI_HP3_DATA_WIDTH {64} \ + CONFIG.PCW_S_AXI_HP3_ID_WIDTH {6} \ + CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC {External} \ + CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ {200} \ + CONFIG.PCW_TRACE_BUFFER_CLOCK_DELAY {12} \ + CONFIG.PCW_TRACE_BUFFER_FIFO_SIZE {128} \ + CONFIG.PCW_TRACE_GRP_16BIT_ENABLE {0} \ + CONFIG.PCW_TRACE_GRP_2BIT_ENABLE {0} \ + CONFIG.PCW_TRACE_GRP_32BIT_ENABLE {0} \ + CONFIG.PCW_TRACE_GRP_4BIT_ENABLE {0} \ + CONFIG.PCW_TRACE_GRP_8BIT_ENABLE {0} \ + CONFIG.PCW_TRACE_INTERNAL_WIDTH {2} \ + CONFIG.PCW_TRACE_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_TRACE_PIPELINE_WIDTH {8} \ + CONFIG.PCW_TTC0_BASEADDR {0xE0104000} \ + CONFIG.PCW_TTC0_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \ + CONFIG.PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ {133.333333} \ + CONFIG.PCW_TTC0_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \ + CONFIG.PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ {133.333333} \ + CONFIG.PCW_TTC0_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \ + CONFIG.PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ {133.333333} \ + CONFIG.PCW_TTC0_HIGHADDR {0xE0104fff} \ + CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_TTC0_TTC0_IO {EMIO} \ + CONFIG.PCW_TTC1_BASEADDR {0xE0105000} \ + CONFIG.PCW_TTC1_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \ + CONFIG.PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ {133.333333} \ + CONFIG.PCW_TTC1_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \ + CONFIG.PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ {133.333333} \ + CONFIG.PCW_TTC1_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \ + CONFIG.PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ {133.333333} \ + CONFIG.PCW_TTC1_HIGHADDR {0xE0105fff} \ + CONFIG.PCW_TTC1_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_TTC_PERIPHERAL_FREQMHZ {50} \ + CONFIG.PCW_UART0_BASEADDR {0xE0000000} \ + CONFIG.PCW_UART0_BAUD_RATE {115200} \ + CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \ + CONFIG.PCW_UART0_HIGHADDR {0xE0000FFF} \ + CONFIG.PCW_UART0_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_UART1_BASEADDR {0xE0001000} \ + CONFIG.PCW_UART1_BAUD_RATE {115200} \ + CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \ + CONFIG.PCW_UART1_HIGHADDR {0xE0001FFF} \ + CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49} \ + CONFIG.PCW_UART_PERIPHERAL_CLKSRC {IO PLL} \ + CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {20} \ + CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {50} \ + CONFIG.PCW_UART_PERIPHERAL_VALID {1} \ + CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \ + CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE {0} \ + CONFIG.PCW_UIPARAM_DDR_AL {0} \ + CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \ + CONFIG.PCW_UIPARAM_DDR_BL {8} \ + CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.537} \ + CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.442} \ + CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.464} \ + CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.521} \ + CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {32 Bit} \ + CONFIG.PCW_UIPARAM_DDR_CL {7} \ + CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM {0} \ + CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH {61.0905} \ + CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY {160} \ + CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM {0} \ + CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH {61.0905} \ + CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY {160} \ + CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM {0} \ + CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH {61.0905} \ + CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY {160} \ + CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM {0} \ + CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH {61.0905} \ + CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY {160} \ + CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN {0} \ + CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \ + CONFIG.PCW_UIPARAM_DDR_CWL {6} \ + CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {2048 MBits} \ + CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM {0} \ + CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH {68.4725} \ + CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY {160} \ + CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM {0} \ + CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH {71.086} \ + CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY {160} \ + CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM {0} \ + CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH {66.794} \ + CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY {160} \ + CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM {0} \ + CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH {108.7385} \ + CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY {160} \ + CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.217} \ + CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.133} \ + CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0.089} \ + CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0.248} \ + CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM {0} \ + CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH {64.1705} \ + CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY {160} \ + CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM {0} \ + CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH {63.686} \ + CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY {160} \ + CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM {0} \ + CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH {68.46} \ + CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY {160} \ + CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM {0} \ + CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH {105.4895} \ + CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY {160} \ + CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {8 Bits} \ + CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \ + CONFIG.PCW_UIPARAM_DDR_ENABLE {1} \ + CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {533.333333} \ + CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP {Normal (0-85)} \ + CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3} \ + CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J256M8 HX-15E} \ + CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \ + CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \ + CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} \ + CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} \ + CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} \ + CONFIG.PCW_UIPARAM_DDR_T_FAW {30.0} \ + CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {36.0} \ + CONFIG.PCW_UIPARAM_DDR_T_RC {49.5} \ + CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \ + CONFIG.PCW_UIPARAM_DDR_T_RP {7} \ + CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {1} \ + CONFIG.PCW_UIPARAM_GENERATE_SUMMARY {NA} \ + CONFIG.PCW_USB0_BASEADDR {0xE0102000} \ + CONFIG.PCW_USB0_HIGHADDR {0xE0102fff} \ + CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \ + CONFIG.PCW_USB0_RESET_ENABLE {1} \ + CONFIG.PCW_USB0_RESET_IO {MIO 7} \ + CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} \ + CONFIG.PCW_USB1_BASEADDR {0xE0103000} \ + CONFIG.PCW_USB1_HIGHADDR {0xE0103fff} \ + CONFIG.PCW_USB1_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_USB1_PERIPHERAL_FREQMHZ {60} \ + CONFIG.PCW_USB1_RESET_ENABLE {0} \ + CONFIG.PCW_USB_RESET_ENABLE {1} \ + CONFIG.PCW_USB_RESET_POLARITY {Active Low} \ + CONFIG.PCW_USB_RESET_SELECT {Share reset pin} \ + CONFIG.PCW_USE_AXI_FABRIC_IDLE {0} \ + CONFIG.PCW_USE_AXI_NONSECURE {0} \ + CONFIG.PCW_USE_CORESIGHT {0} \ + CONFIG.PCW_USE_CROSS_TRIGGER {0} \ + CONFIG.PCW_USE_CR_FABRIC {1} \ + CONFIG.PCW_USE_DDR_BYPASS {0} \ + CONFIG.PCW_USE_DEBUG {0} \ + CONFIG.PCW_USE_DEFAULT_ACP_USER_VAL {0} \ + CONFIG.PCW_USE_DMA0 {0} \ + CONFIG.PCW_USE_DMA1 {0} \ + CONFIG.PCW_USE_DMA2 {0} \ + CONFIG.PCW_USE_DMA3 {0} \ + CONFIG.PCW_USE_EXPANDED_IOP {1} \ + CONFIG.PCW_USE_EXPANDED_PS_SLCR_REGISTERS {0} \ + CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \ + CONFIG.PCW_USE_HIGH_OCM {1} \ + CONFIG.PCW_USE_M_AXI_GP0 {1} \ + CONFIG.PCW_USE_M_AXI_GP1 {0} \ + CONFIG.PCW_USE_PROC_EVENT_BUS {0} \ + CONFIG.PCW_USE_PS_SLCR_REGISTERS {0} \ + CONFIG.PCW_USE_S_AXI_ACP {0} \ + CONFIG.PCW_USE_S_AXI_GP0 {1} \ + CONFIG.PCW_USE_S_AXI_GP1 {0} \ + CONFIG.PCW_USE_S_AXI_HP0 {1} \ + CONFIG.PCW_USE_S_AXI_HP1 {0} \ + CONFIG.PCW_USE_S_AXI_HP2 {0} \ + CONFIG.PCW_USE_S_AXI_HP3 {0} \ + CONFIG.PCW_USE_TRACE {0} \ + CONFIG.PCW_USE_TRACE_DATA_EDGE_DETECTOR {0} \ + CONFIG.PCW_VALUE_SILVERSION {3} \ + CONFIG.PCW_WDT_PERIPHERAL_CLKSRC {CPU_1X} \ + CONFIG.PCW_WDT_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_WDT_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_WDT_PERIPHERAL_FREQMHZ {133.333333} \ + CONFIG.preset {ZC702} \ ] $processing_system7_0 - # Need to retain value_src of defaults + # Create instance: xlconcat_0, and set properties + set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] set_property -dict [ list \ -CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_APU_CLK_RATIO_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_APU_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_ARMPLL_CTRL_FBDIV.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_CAN0_CAN0_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_CAN0_GRP_CLK_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_CAN0_GRP_CLK_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_CAN0_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_CAN0_PERIPHERAL_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_CAN1_CAN1_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_CAN1_GRP_CLK_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_CAN1_GRP_CLK_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_CAN1_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_CAN1_PERIPHERAL_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_CAN_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_CAN_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_CAN_PERIPHERAL_VALID.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_CLK0_FREQ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_CLK1_FREQ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_CLK2_FREQ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_CLK3_FREQ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_CPU_CPU_PLL_FREQMHZ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_CPU_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_DCI_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_DDRPLL_CTRL_FBDIV.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_DDR_DDR_PLL_FREQMHZ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_DDR_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_DDR_PORT0_HPR_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_DDR_PORT1_HPR_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_DDR_PORT2_HPR_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_DDR_PORT3_HPR_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_DDR_PRIORITY_READPORT_0.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_DDR_PRIORITY_READPORT_1.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_DDR_PRIORITY_READPORT_2.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_DDR_PRIORITY_READPORT_3.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_DDR_PRIORITY_WRITEPORT_0.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_DDR_PRIORITY_WRITEPORT_1.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_DDR_PRIORITY_WRITEPORT_2.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_DDR_PRIORITY_WRITEPORT_3.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_ENET0_ENET0_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_ENET0_GRP_MDIO_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_ENET0_GRP_MDIO_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_ENET0_PERIPHERAL_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_ENET0_RESET_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_ENET0_RESET_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_ENET1_ENET1_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_ENET1_GRP_MDIO_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_ENET1_GRP_MDIO_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_ENET1_RESET_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_ENET1_RESET_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_ENET_RESET_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_ENET_RESET_POLARITY.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_ENET_RESET_SELECT.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_EN_4K_TIMER.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_EN_CAN0.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_EN_EMIO_GPIO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_EN_EMIO_TTC0.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_EN_ENET0.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_EN_I2C0.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_EN_QSPI.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_EN_SDIO0.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_EN_TTC0.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_EN_UART1.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_EN_USB0.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_FCLK3_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_FCLK_CLK0_BUF.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_FPGA_FCLK0_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_GPIO_MIO_GPIO_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_GPIO_MIO_GPIO_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_GPIO_PERIPHERAL_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_I2C0_GRP_INT_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_I2C0_GRP_INT_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_I2C0_I2C0_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_I2C0_PERIPHERAL_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_I2C0_RESET_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_I2C0_RESET_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_I2C1_GRP_INT_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_I2C1_GRP_INT_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_I2C1_I2C1_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_I2C1_PERIPHERAL_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_I2C1_RESET_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_I2C1_RESET_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_I2C_RESET_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_I2C_RESET_POLARITY.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_I2C_RESET_SELECT.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_IOPLL_CTRL_FBDIV.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_IO_IO_PLL_FREQMHZ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_0_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_0_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_0_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_0_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_10_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_10_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_10_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_10_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_11_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_11_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_11_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_11_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_12_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_12_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_12_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_12_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_13_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_13_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_13_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_13_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_14_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_14_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_14_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_14_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_15_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_15_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_15_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_15_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_16_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_16_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_16_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_16_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_17_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_17_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_17_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_17_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_18_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_18_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_18_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_18_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_19_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_19_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_19_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_19_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_1_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_1_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_1_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_1_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_20_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_20_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_20_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_20_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_21_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_21_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_21_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_21_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_22_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_22_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_22_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_22_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_23_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_23_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_23_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_23_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_24_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_24_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_24_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_24_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_25_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_25_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_25_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_25_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_26_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_26_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_26_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_26_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_27_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_27_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_27_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_27_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_28_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_28_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_28_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_28_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_29_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_29_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_29_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_29_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_2_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_2_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_2_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_2_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_30_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_30_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_30_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_30_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_31_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_31_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_31_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_31_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_32_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_32_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_32_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_32_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_33_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_33_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_33_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_33_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_34_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_34_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_34_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_34_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_35_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_35_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_35_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_35_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_36_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_36_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_36_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_36_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_37_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_37_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_37_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_37_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_38_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_38_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_38_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_38_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_39_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_39_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_39_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_39_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_3_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_3_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_3_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_3_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_40_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_40_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_40_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_40_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_41_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_41_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_41_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_41_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_42_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_42_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_42_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_42_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_43_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_43_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_43_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_43_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_44_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_44_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_44_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_44_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_45_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_45_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_45_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_45_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_46_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_46_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_46_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_46_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_47_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_47_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_47_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_47_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_48_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_48_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_48_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_48_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_49_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_49_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_49_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_49_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_4_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_4_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_4_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_4_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_50_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_50_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_50_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_50_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_51_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_51_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_51_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_51_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_52_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_52_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_52_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_52_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_53_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_53_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_53_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_53_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_5_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_5_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_5_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_5_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_6_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_6_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_6_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_6_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_7_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_7_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_7_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_7_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_8_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_8_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_8_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_8_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_9_DIRECTION.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_9_IOTYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_9_PULLUP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_9_SLEW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_TREE_PERIPHERALS.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_MIO_TREE_SIGNALS.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NAND_CYCLES_T_AR.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NAND_CYCLES_T_CLR.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NAND_CYCLES_T_RC.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NAND_CYCLES_T_REA.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NAND_CYCLES_T_RR.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NAND_CYCLES_T_WC.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NAND_CYCLES_T_WP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NAND_GRP_D8_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NAND_GRP_D8_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NAND_NAND_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NAND_PERIPHERAL_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NOR_CS0_T_CEOE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NOR_CS0_T_PC.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NOR_CS0_T_RC.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NOR_CS0_T_TR.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NOR_CS0_T_WC.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NOR_CS0_T_WP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NOR_CS0_WE_TIME.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NOR_CS1_T_CEOE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NOR_CS1_T_PC.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NOR_CS1_T_RC.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NOR_CS1_T_TR.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NOR_CS1_T_WC.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NOR_CS1_T_WP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NOR_CS1_WE_TIME.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NOR_GRP_A25_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NOR_GRP_A25_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NOR_GRP_CS0_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NOR_GRP_CS0_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NOR_GRP_CS1_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NOR_GRP_CS1_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NOR_GRP_SRAM_CS0_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NOR_GRP_SRAM_CS1_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NOR_GRP_SRAM_INT_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NOR_NOR_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NOR_PERIPHERAL_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NOR_SRAM_CS0_T_CEOE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NOR_SRAM_CS0_T_PC.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NOR_SRAM_CS0_T_RC.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NOR_SRAM_CS0_T_TR.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NOR_SRAM_CS0_T_WC.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NOR_SRAM_CS0_T_WP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NOR_SRAM_CS0_WE_TIME.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NOR_SRAM_CS1_T_CEOE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NOR_SRAM_CS1_T_PC.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NOR_SRAM_CS1_T_RC.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NOR_SRAM_CS1_T_TR.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NOR_SRAM_CS1_T_WC.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NOR_SRAM_CS1_T_WP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_NOR_SRAM_CS1_WE_TIME.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_PERIPHERAL_BOARD_PRESET.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_PJTAG_PJTAG_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_PLL_BYPASSMODE_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_PRESET_BANK0_VOLTAGE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_PRESET_BANK1_VOLTAGE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_QSPI_GRP_FBCLK_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_QSPI_GRP_IO1_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_QSPI_GRP_IO1_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_QSPI_GRP_SS1_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_QSPI_GRP_SS1_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_QSPI_PERIPHERAL_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_QSPI_QSPI_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_SD0_GRP_CD_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_SD0_GRP_CD_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_SD0_GRP_POW_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_SD0_GRP_POW_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_SD0_GRP_WP_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_SD0_GRP_WP_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_SD0_PERIPHERAL_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_SD0_SD0_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_SD1_GRP_CD_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_SD1_GRP_CD_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_SD1_GRP_POW_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_SD1_GRP_POW_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_SD1_GRP_WP_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_SD1_GRP_WP_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_SD1_PERIPHERAL_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_SD1_SD1_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_SDIO_PERIPHERAL_VALID.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_SMC_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_SPI0_GRP_SS0_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_SPI0_GRP_SS0_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_SPI0_GRP_SS1_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_SPI0_GRP_SS1_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_SPI0_GRP_SS2_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_SPI0_GRP_SS2_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_SPI0_PERIPHERAL_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_SPI0_SPI0_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_SPI1_GRP_SS0_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_SPI1_GRP_SS0_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_SPI1_GRP_SS1_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_SPI1_GRP_SS1_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_SPI1_GRP_SS2_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_SPI1_GRP_SS2_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_SPI1_PERIPHERAL_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_SPI1_SPI1_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_SPI_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_S_AXI_HP0_DATA_WIDTH.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_S_AXI_HP1_DATA_WIDTH.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_S_AXI_HP2_DATA_WIDTH.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_S_AXI_HP3_DATA_WIDTH.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_TRACE_GRP_16BIT_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_TRACE_GRP_16BIT_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_TRACE_GRP_2BIT_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_TRACE_GRP_2BIT_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_TRACE_GRP_32BIT_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_TRACE_GRP_32BIT_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_TRACE_GRP_4BIT_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_TRACE_GRP_4BIT_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_TRACE_GRP_8BIT_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_TRACE_GRP_8BIT_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_TRACE_INTERNAL_WIDTH.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_TRACE_PERIPHERAL_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_TRACE_TRACE_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_TTC0_CLK0_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_TTC0_CLK1_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_TTC0_CLK2_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_TTC1_CLK0_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_TTC1_CLK1_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_TTC1_CLK2_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_TTC1_PERIPHERAL_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_TTC1_TTC1_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_TTC_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UART0_BAUD_RATE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UART0_GRP_FULL_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UART0_GRP_FULL_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UART0_PERIPHERAL_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UART0_UART0_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UART1_BAUD_RATE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UART1_GRP_FULL_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UART1_GRP_FULL_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UART1_PERIPHERAL_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UART1_UART1_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UART_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UART_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UART_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UART_PERIPHERAL_VALID.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_AL.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_BL.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_CL.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_CWL.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_ECC.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_PARTNO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_SPEED_BIN.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_T_FAW.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_T_RC.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_T_RCD.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_T_RP.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_USB0_PERIPHERAL_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_USB0_RESET_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_USB0_RESET_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_USB0_USB0_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_USB1_PERIPHERAL_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_USB1_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_USB1_RESET_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_USB1_RESET_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_USB1_USB1_IO.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_USB_RESET_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_USB_RESET_POLARITY.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_USB_RESET_SELECT.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_USE_CROSS_TRIGGER.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_WDT_PERIPHERAL_CLKSRC.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_WDT_PERIPHERAL_DIVISOR0.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_WDT_PERIPHERAL_ENABLE.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_WDT_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \ -CONFIG.PCW_WDT_WDT_IO.VALUE_SRC {DEFAULT} \ - ] $processing_system7_0 + CONFIG.NUM_PORTS {1} \ + ] $xlconcat_0 # Create interface connections - connect_bd_intf_net -intf_net LEDS_6BIT_GPIO [get_bd_intf_ports LEDS_6BIT] [get_bd_intf_pins LEDS_6BIT/GPIO] connect_bd_intf_net -intf_net BENCHMARK_PIO_GPIO [get_bd_intf_ports BENCHMARK_PIO] [get_bd_intf_pins BENCHMARK_PIO/GPIO] connect_bd_intf_net -intf_net CLK_IN1_D_1 [get_bd_intf_ports clk_in] [get_bd_intf_pins clock_generator/CLK_IN1_D] connect_bd_intf_net -intf_net HOST_BENCHMARK_PIO_GPIO [get_bd_intf_ports HOST_BENCHMARK_PIO] [get_bd_intf_pins HOST_BENCHMARK_PIO/GPIO] - connect_bd_intf_net -intf_net pcp_M_AXI_DC [get_bd_intf_pins pcp/M_AXI_DC] [get_bd_intf_pins axi_0/S00_AXI] - connect_bd_intf_net -intf_net pcp_M_AXI_IC [get_bd_intf_pins pcp/M_AXI_IC] [get_bd_intf_pins axi_0/S01_AXI] + connect_bd_intf_net -intf_net LEDS_6BIT_GPIO [get_bd_intf_ports LEDS_6BIT] [get_bd_intf_pins LEDS_6BIT/GPIO] connect_bd_intf_net -intf_net Node_Switches_GPIO [get_bd_intf_ports NODE_SWITCHES] [get_bd_intf_pins Node_Switches/GPIO] connect_bd_intf_net -intf_net POWERLINK_Led_GPIO [get_bd_intf_ports POWERLINK_LED] [get_bd_intf_pins POWERLINK_Led/GPIO] connect_bd_intf_net -intf_net axi4lite_mb_0_M02_AXI [get_bd_intf_pins axi4lite_mb_0/M02_AXI] [get_bd_intf_pins axi_openmac_0/S_AXI_MAC_PKT] @@ -1747,13 +1328,15 @@ CONFIG.PCW_WDT_WDT_IO.VALUE_SRC {DEFAULT} \ connect_bd_intf_net -intf_net axi_openmac_0_MII [get_bd_intf_ports MII] [get_bd_intf_pins axi_openmac_0/MII] connect_bd_intf_net -intf_net axi_openmac_0_M_AXI_MAC_DMA [get_bd_intf_pins axi_0/S02_AXI] [get_bd_intf_pins axi_openmac_0/M_AXI_MAC_DMA] connect_bd_intf_net -intf_net axi_openmac_0_SMI [get_bd_intf_ports SMI] [get_bd_intf_pins axi_openmac_0/SMI] - connect_bd_intf_net -intf_net microblaze_0_axi_dp [get_bd_intf_pins pcp/M_AXI_DP] [get_bd_intf_pins axi4lite_mb_0/S00_AXI] - connect_bd_intf_net -intf_net microblaze_0_debug [get_bd_intf_pins pcp/DEBUG] [get_bd_intf_pins debug_module/MBDEBUG_0] + connect_bd_intf_net -intf_net microblaze_0_axi_dp [get_bd_intf_pins axi4lite_mb_0/S00_AXI] [get_bd_intf_pins pcp/M_AXI_DP] + connect_bd_intf_net -intf_net microblaze_0_debug [get_bd_intf_pins debug_module/MBDEBUG_0] [get_bd_intf_pins pcp/DEBUG] connect_bd_intf_net -intf_net microblaze_0_dlmb_1 [get_bd_intf_pins pcp/DLMB] [get_bd_intf_pins pcp_bram/DLMB] connect_bd_intf_net -intf_net microblaze_0_ilmb_1 [get_bd_intf_pins pcp/ILMB] [get_bd_intf_pins pcp_bram/ILMB] connect_bd_intf_net -intf_net microblaze_0_intc_axi [get_bd_intf_pins axi4lite_mb_0/M00_AXI] [get_bd_intf_pins pcp_intc/s_axi] connect_bd_intf_net -intf_net microblaze_0_interrupt [get_bd_intf_pins pcp/INTERRUPT] [get_bd_intf_pins pcp_intc/interrupt] connect_bd_intf_net -intf_net microblaze_0_mdm_axi [get_bd_intf_pins axi4lite_mb_0/M01_AXI] [get_bd_intf_pins debug_module/S_AXI] + connect_bd_intf_net -intf_net pcp_M_AXI_DC [get_bd_intf_pins axi_0/S00_AXI] [get_bd_intf_pins pcp/M_AXI_DC] + connect_bd_intf_net -intf_net pcp_M_AXI_IC [get_bd_intf_pins axi_0/S01_AXI] [get_bd_intf_pins pcp/M_AXI_IC] connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR] connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO] connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins axi4lite_0/S00_AXI] [get_bd_intf_pins processing_system7_0/M_AXI_GP0] @@ -1762,13 +1345,13 @@ CONFIG.PCW_WDT_WDT_IO.VALUE_SRC {DEFAULT} \ connect_bd_net -net S00_ARESETN_1 [get_bd_pins HOST_BENCHMARK_PIO/s_axi_aresetn] [get_bd_pins LEDS_6BIT/s_axi_aresetn] [get_bd_pins Node_Switches/s_axi_aresetn] [get_bd_pins axi4lite_0/M00_ARESETN] [get_bd_pins axi4lite_0/M01_ARESETN] [get_bd_pins axi4lite_0/M02_ARESETN] [get_bd_pins axi4lite_0/S00_ARESETN] [get_bd_pins proc_sys_rst1/peripheral_aresetn] connect_bd_net -net axi_openmac_0_MAC_IRQ [get_bd_pins axi_openmac_0/MAC_IRQ] [get_bd_pins pcp_xlconcat/In1] connect_bd_net -net axi_openmac_0_TIMER_IRQ [get_bd_pins axi_openmac_0/TIMER_IRQ] [get_bd_pins pcp_xlconcat/In0] - connect_bd_net -net axi_openmac_0_TIMER_PULSE_IRQ [get_bd_pins axi_openmac_0/TIMER_PULSE_IRQ] [get_bd_pins processing_system7_0/IRQ_F2P] + connect_bd_net -net axi_openmac_0_TIMER_PULSE_IRQ [get_bd_pins axi_openmac_0/TIMER_PULSE_IRQ] [get_bd_pins xlconcat_0/In0] connect_bd_net -net axi_openmac_0_oSmi_nPhyRst [get_bd_ports oSmi_nPhyRst] [get_bd_pins axi_openmac_0/oSmi_nPhyRst] connect_bd_net -net clock_generator_clk_out2 [get_bd_pins axi4lite_mb_0/M03_ACLK] [get_bd_pins axi_openmac_0/S_AXI_MAC_REG_ACLK] [get_bd_pins axi_openmac_0/iClk50] [get_bd_pins clock_generator/clk_out2] [get_bd_pins fit_timer_0/Clk] [get_bd_pins proc_sys_rst/slowest_sync_clk] connect_bd_net -net clock_generator_locked [get_bd_pins clock_generator/locked] [get_bd_pins proc_sys_rst/dcm_locked] connect_bd_net -net debug_module_Debug_SYS_Rst [get_bd_pins debug_module/Debug_SYS_Rst] [get_bd_pins proc_sys_rst/mb_debug_sys_rst] connect_bd_net -net fit_timer_0_Interrupt [get_bd_pins fit_timer_0/Interrupt] [get_bd_pins pcp_xlconcat/In2] - connect_bd_net -net microblaze_0_Clk [get_bd_pins BENCHMARK_PIO/s_axi_aclk] [get_bd_pins pcp/Clk] [get_bd_pins pcp_bram/LMB_Clk] [get_bd_pins POWERLINK_Led/s_axi_aclk] [get_bd_pins axi4lite_mb_0/ACLK] [get_bd_pins axi4lite_mb_0/M00_ACLK] [get_bd_pins axi4lite_mb_0/M01_ACLK] [get_bd_pins axi4lite_mb_0/M02_ACLK] [get_bd_pins axi4lite_mb_0/M04_ACLK] [get_bd_pins axi4lite_mb_0/M05_ACLK] [get_bd_pins axi4lite_mb_0/M06_ACLK] [get_bd_pins axi4lite_mb_0/S00_ACLK] [get_bd_pins axi_0/ACLK] [get_bd_pins axi_0/M00_ACLK] [get_bd_pins axi_0/S00_ACLK] [get_bd_pins axi_0/S01_ACLK] [get_bd_pins axi_0/S02_ACLK] [get_bd_pins axi_openmac_0/M_AXI_MAC_DMA_ACLK] [get_bd_pins axi_openmac_0/S_AXI_MAC_PKT_ACLK] [get_bd_pins clock_generator/clk_out1] [get_bd_pins debug_module/S_AXI_ACLK] [get_bd_pins pcp_intc/processor_clk] [get_bd_pins pcp_intc/s_axi_aclk] [get_bd_pins processing_system7_0/S_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] + connect_bd_net -net microblaze_0_Clk [get_bd_pins BENCHMARK_PIO/s_axi_aclk] [get_bd_pins POWERLINK_Led/s_axi_aclk] [get_bd_pins axi4lite_mb_0/ACLK] [get_bd_pins axi4lite_mb_0/M00_ACLK] [get_bd_pins axi4lite_mb_0/M01_ACLK] [get_bd_pins axi4lite_mb_0/M02_ACLK] [get_bd_pins axi4lite_mb_0/M04_ACLK] [get_bd_pins axi4lite_mb_0/M05_ACLK] [get_bd_pins axi4lite_mb_0/M06_ACLK] [get_bd_pins axi4lite_mb_0/S00_ACLK] [get_bd_pins axi_0/ACLK] [get_bd_pins axi_0/M00_ACLK] [get_bd_pins axi_0/S00_ACLK] [get_bd_pins axi_0/S01_ACLK] [get_bd_pins axi_0/S02_ACLK] [get_bd_pins axi_openmac_0/M_AXI_MAC_DMA_ACLK] [get_bd_pins axi_openmac_0/S_AXI_MAC_PKT_ACLK] [get_bd_pins clock_generator/clk_out1] [get_bd_pins debug_module/S_AXI_ACLK] [get_bd_pins pcp/Clk] [get_bd_pins pcp_bram/LMB_Clk] [get_bd_pins pcp_intc/processor_clk] [get_bd_pins pcp_intc/s_axi_aclk] [get_bd_pins processing_system7_0/S_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] connect_bd_net -net microblaze_0_intr [get_bd_pins pcp_intc/intr] [get_bd_pins pcp_xlconcat/dout] connect_bd_net -net net_vcc_phy0_dout [get_bd_ports axi_powerlink_0_PHY0_PWRDWN_INT_n_pin] [get_bd_pins net_vcc_phy0/dout] connect_bd_net -net net_vcc_phy1_dout [get_bd_ports axi_powerlink_0_PHY1_PWRDWN_INT_n_pin] [get_bd_pins net_vcc_phy1/dout] @@ -1781,8 +1364,11 @@ CONFIG.PCW_WDT_WDT_IO.VALUE_SRC {DEFAULT} \ connect_bd_net -net rst_clk_wiz_1_100M_bus_struct_reset [get_bd_pins pcp_bram/SYS_Rst] [get_bd_pins proc_sys_rst/bus_struct_reset] connect_bd_net -net rst_clk_wiz_1_100M_interconnect_aresetn [get_bd_pins axi4lite_mb_0/ARESETN] [get_bd_pins axi_0/ARESETN] [get_bd_pins proc_sys_rst/interconnect_aresetn] connect_bd_net -net rst_clk_wiz_1_100M_peripheral_aresetn [get_bd_pins BENCHMARK_PIO/s_axi_aresetn] [get_bd_pins POWERLINK_Led/s_axi_aresetn] [get_bd_pins axi4lite_mb_0/M00_ARESETN] [get_bd_pins axi4lite_mb_0/M01_ARESETN] [get_bd_pins axi4lite_mb_0/M02_ARESETN] [get_bd_pins axi4lite_mb_0/M03_ARESETN] [get_bd_pins axi4lite_mb_0/M04_ARESETN] [get_bd_pins axi4lite_mb_0/M05_ARESETN] [get_bd_pins axi4lite_mb_0/M06_ARESETN] [get_bd_pins axi4lite_mb_0/S00_ARESETN] [get_bd_pins axi_0/M00_ARESETN] [get_bd_pins axi_0/S00_ARESETN] [get_bd_pins axi_0/S01_ARESETN] [get_bd_pins axi_0/S02_ARESETN] [get_bd_pins axi_openmac_0/M_AXI_MAC_DMA_ARESETN] [get_bd_pins axi_openmac_0/S_AXI_MAC_PKT_ARESETN] [get_bd_pins axi_openmac_0/S_AXI_MAC_REG_ARESETN] [get_bd_pins debug_module/S_AXI_ARESETN] [get_bd_pins fit_timer_0/Rst] [get_bd_pins pcp_intc/s_axi_aresetn] [get_bd_pins proc_sys_rst/peripheral_aresetn] + connect_bd_net -net xlconcat_0_dout [get_bd_pins processing_system7_0/IRQ_F2P] [get_bd_pins xlconcat_0/dout] # Create address segments + create_bd_addr_seg -range 0x20000000 -offset 0x20000000 [get_bd_addr_spaces axi_openmac_0/M_AXI_MAC_DMA] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM + create_bd_addr_seg -range 0x00040000 -offset 0xFFFC0000 [get_bd_addr_spaces axi_openmac_0/M_AXI_MAC_DMA] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_HIGH_OCM] SEG_processing_system7_0_HP0_HIGH_OCM create_bd_addr_seg -range 0x00010000 -offset 0x40010000 [get_bd_addr_spaces pcp/Data] [get_bd_addr_segs BENCHMARK_PIO/S_AXI/Reg] SEG_BENCHMARK_PIO_Reg create_bd_addr_seg -range 0x00010000 -offset 0x40000000 [get_bd_addr_spaces pcp/Data] [get_bd_addr_segs POWERLINK_Led/S_AXI/Reg] SEG_POWERLINK_Led_Reg create_bd_addr_seg -range 0x00010000 -offset 0x60A00000 [get_bd_addr_spaces pcp/Data] [get_bd_addr_segs axi_openmac_0/S_AXI_MAC_PKT/MAC_PKT] SEG_axi_openmac_0_MAC_PKT @@ -1797,106 +1383,10 @@ CONFIG.PCW_WDT_WDT_IO.VALUE_SRC {DEFAULT} \ create_bd_addr_seg -range 0x20000000 -offset 0x20000000 [get_bd_addr_spaces pcp/Instruction] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM create_bd_addr_seg -range 0x00040000 -offset 0xFFFC0000 [get_bd_addr_spaces pcp/Data] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_HIGH_OCM] SEG_processing_system7_0_HP0_HIGH_OCM create_bd_addr_seg -range 0x00040000 -offset 0xFFFC0000 [get_bd_addr_spaces pcp/Instruction] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_HIGH_OCM] SEG_processing_system7_0_HP0_HIGH_OCM - create_bd_addr_seg -range 0x20000000 -offset 0x20000000 [get_bd_addr_spaces axi_openmac_0/M_AXI_MAC_DMA] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM - create_bd_addr_seg -range 0x00040000 -offset 0xFFFC0000 [get_bd_addr_spaces axi_openmac_0/M_AXI_MAC_DMA] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_HIGH_OCM] SEG_processing_system7_0_HP0_HIGH_OCM create_bd_addr_seg -range 0x00010000 -offset 0x41210000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs HOST_BENCHMARK_PIO/S_AXI/Reg] SEG_HOST_BENCHMARK_PIO_Reg create_bd_addr_seg -range 0x00010000 -offset 0x41200000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs LEDS_6BIT/S_AXI/Reg] SEG_LEDS_6BIT_Reg create_bd_addr_seg -range 0x00010000 -offset 0x41220000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs Node_Switches/S_AXI/Reg] SEG_Node_Switches_Reg - # Perform GUI Layout - regenerate_bd_layout -layout_string { - guistr: "# # String gsaved with Nlview 6.5.12 2016-01-29 bk=1.3547 VDI=39 GEI=35 GUI=JA:1.6 -# -string -flagsOSRD -preplace port DDR -pg 1 -y -330 -defaultsOSRD -preplace port LEDS_6BIT -pg 1 -y 130 -defaultsOSRD -preplace port MII -pg 1 -y -240 -defaultsOSRD -preplace port SMI -pg 1 -y -210 -defaultsOSRD -preplace port clk_in -pg 1 -y -340 -defaultsOSRD -preplace port BENCHMARK_PIO -pg 1 -y -10 -defaultsOSRD -preplace port HOST_BENCHMARK_PIO -pg 1 -y 30 -defaultsOSRD -preplace port POWERLINK_LED -pg 1 -y -50 -defaultsOSRD -preplace port FIXED_IO -pg 1 -y -280 -defaultsOSRD -preplace port NODE_SWITCHES -pg 1 -y 80 -defaultsOSRD -preplace port reset -pg 1 -y -320 -defaultsOSRD -preplace portBus oSmi_nPhyRst -pg 1 -y -170 -defaultsOSRD -preplace portBus axi_powerlink_0_PHY1_PWRDWN_INT_n_pin -pg 1 -y -70 -defaultsOSRD -preplace portBus axi_powerlink_0_PHY0_PWRDWN_INT_n_pin -pg 1 -y -90 -defaultsOSRD -preplace inst POWERLINK_Led -pg 1 -lvl 1 -y 1000 -defaultsOSRD -preplace inst LEDS_6BIT -pg 1 -lvl 2 -y 1290 -defaultsOSRD -preplace inst debug_module -pg 1 -lvl 1 -y -720 -defaultsOSRD -preplace inst axi4lite_0 -pg 1 -lvl 2 -y 470 -defaultsOSRD -preplace inst fit_timer_0 -pg 1 -lvl 1 -y 890 -defaultsOSRD -preplace inst pcp_xlconcat -pg 1 -lvl 2 -y 840 -defaultsOSRD -preplace inst BENCHMARK_PIO -pg 1 -lvl 1 -y 1120 -defaultsOSRD -preplace inst proc_sys_rst -pg 1 -lvl 1 -y 430 -defaultsOSRD -preplace inst pcp -pg 1 -lvl 1 -y -530 -defaultsOSRD -preplace inst net_vcc_phy0 -pg 1 -lvl 2 -y 660 -defaultsOSRD -preplace inst proc_sys_rst1 -pg 1 -lvl 1 -y 590 -defaultsOSRD -preplace inst HOST_BENCHMARK_PIO -pg 1 -lvl 1 -y 1290 -defaultsOSRD -preplace inst net_vcc_phy1 -pg 1 -lvl 2 -y 740 -defaultsOSRD -preplace inst axi_openmac_0 -pg 1 -lvl 1 -y 160 -defaultsOSRD -preplace inst axi4lite_mb_0 -pg 1 -lvl 2 -y -340 -defaultsOSRD -preplace inst axi_0 -pg 1 -lvl 2 -y 80 -defaultsOSRD -preplace inst Node_Switches -pg 1 -lvl 1 -y 1460 -defaultsOSRD -preplace inst clock_generator -pg 1 -lvl 1 -y 730 -defaultsOSRD -preplace inst pcp_bram -pg 1 -lvl 2 -y -700 -defaultsOSRD -preplace inst processing_system7_0 -pg 1 -lvl 1 -y -250 -defaultsOSRD -preplace inst pcp_intc -pg 1 -lvl 2 -y 1030 -defaultsOSRD -preplace netloc axi4lite_mb_0_M06_AXI 1 0 3 140 -620 NJ -620 1370 -preplace netloc processing_system7_0_DDR 1 1 2 NJ -590 NJ -preplace netloc HOST_BENCHMARK_PIO_GPIO 1 1 2 NJ 1360 NJ -preplace netloc axi4lite_mb_0_M02_AXI 1 0 3 NJ -100 NJ -100 1350 -preplace netloc microblaze_0_mdm_axi 1 0 3 NJ -640 NJ -600 NJ -preplace netloc processing_system7_0_GPIO_O 1 0 2 100 -400 770 -preplace netloc microblaze_0_intr 1 1 2 940 1160 1340 -preplace netloc processing_system7_0_M_AXI_GP0 1 1 1 880 -preplace netloc debug_module_Debug_SYS_Rst 1 0 2 140 -90 780 -preplace netloc microblaze_0_Clk 1 0 2 40 -80 910 -preplace netloc BENCHMARK_PIO_GPIO 1 1 2 NJ 1130 NJ -preplace netloc axi_interconnect_0_M02_AXI 1 1 2 920 920 1330 -preplace netloc microblaze_0_intc_axi 1 1 2 930 1150 1380 -preplace netloc microblaze_0_interrupt 1 0 3 NJ 1190 NJ 1190 NJ -preplace netloc clock_generator_locked 1 0 2 160 800 760 -preplace netloc processing_system7_0_FCLK_RESET0_N 1 0 2 150 340 770 -preplace netloc clock_generator_clk_out2 1 0 2 110 330 900 -preplace netloc axi_openmac_0_TIMER_IRQ 1 1 1 860 -preplace netloc axi_openmac_0_M_AXI_MAC_DMA 1 1 1 870 -preplace netloc microblaze_0_ilmb_1 1 1 1 NJ -preplace netloc axi_openmac_0_oSmi_nPhyRst 1 1 2 NJ 280 NJ -preplace netloc axi_openmac_0_TIMER_PULSE_IRQ 1 0 2 130 300 760 -preplace netloc POWERLINK_Led_GPIO 1 1 2 NJ 1140 NJ -preplace netloc CLK_IN1_D_1 1 0 1 NJ -preplace netloc axi4lite_mb_0_M04_AXI 1 0 3 NJ 310 NJ 310 1360 -preplace netloc pcp_M_AXI_DC 1 1 1 940 -preplace netloc pcp_M_AXI_IC 1 1 1 930 -preplace netloc microblaze_0_axi_dp 1 1 1 NJ -preplace netloc proc_sys_rst_mb_reset 1 0 2 80 810 780 -preplace netloc proc_sys_rst1_interconnect_aresetn 1 1 1 940 -preplace netloc fit_timer_0_Interrupt 1 1 1 940 -preplace netloc rst_clk_wiz_1_100M_interconnect_aresetn 1 1 1 790 -preplace netloc rst_clk_wiz_1_100M_bus_struct_reset 1 1 1 840 -preplace netloc BENCHMARK_PIO2_GPIO 1 2 1 NJ -preplace netloc POWERLINK_Led1_GPIO 1 1 2 NJ 1460 NJ -preplace netloc axi_openmac_0_MII 1 1 2 NJ 260 NJ -preplace netloc processing_system7_0_FIXED_IO 1 1 2 NJ -580 NJ -preplace netloc axi_0_M00_AXI 1 0 3 NJ 290 NJ 290 1330 -preplace netloc rst_clk_wiz_1_100M_peripheral_aresetn 1 0 2 50 820 810 -preplace netloc axi_openmac_0_SMI 1 1 2 NJ 270 NJ -preplace netloc axi_interconnect_0_M00_AXI 1 0 3 NJ 830 NJ 910 1350 -preplace netloc net_vcc_phy0_dout 1 2 1 NJ -preplace netloc axi_interconnect_0_M01_AXI 1 0 3 NJ 1370 NJ 1370 1360 -preplace netloc microblaze_0_dlmb_1 1 1 1 NJ -preplace netloc processing_system7_0_FCLK_CLK0 1 0 2 70 -70 820 -preplace netloc net_vcc_phy1_dout 1 2 1 NJ -preplace netloc axi4lite_mb_0_M03_AXI 1 0 3 NJ -630 NJ -610 1360 -preplace netloc microblaze_0_debug 1 0 2 NJ -650 NJ -preplace netloc reset_1 1 0 1 NJ -preplace netloc axi4lite_mb_0_M05_AXI 1 0 3 NJ 320 NJ 300 1340 -preplace netloc S00_ARESETN_1 1 0 2 150 1360 800 -preplace netloc axi_openmac_0_MAC_IRQ 1 1 1 830 -levelinfo -pg 1 0 540 1180 1500 -top -780 -bot 1530 -", -} # Restore current instance current_bd_instance $oldCurInst @@ -1911,3 +1401,5 @@ levelinfo -pg 1 0 540 1180 1500 -top -780 -bot 1530 ################################################################## create_root_design "" + + From 5c6813bd50f38124a4c4170f9b83322d8d028c4d Mon Sep 17 00:00:00 2001 From: Hassen Gassoumi Date: Wed, 12 Sep 2018 17:52:29 +0200 Subject: [PATCH 2/3] Upgrade to Vivado & SDK 2018.2 --- cmake/microblazeapppostactions.cmake | 2 +- ...ain-xilinx-vivado-arm-linux-eabi-gnu.cmake | 2 +- .../mn-dual-shmem-gpio/vivado/system.xdc | 236 +++++++----------- .../mn-dual-shmem-gpio/vivado/system_bd.tcl | 12 +- 4 files changed, 97 insertions(+), 155 deletions(-) diff --git a/cmake/microblazeapppostactions.cmake b/cmake/microblazeapppostactions.cmake index b73f8eded..ccf511d17 100644 --- a/cmake/microblazeapppostactions.cmake +++ b/cmake/microblazeapppostactions.cmake @@ -45,7 +45,7 @@ ADD_CUSTOM_COMMAND( TARGET ${EXECUTABLE_NAME} POST_BUILD COMMAND mb-size ${EXECUTABLE_NAME} | tee "${PROJECT_NAME}.size" - COMMAND arm-xilinx-eabi-objcopy -I elf32-little -O elf32-little -R .local_memory -R .vectors.* ${EXECUTABLE_NAME} ${PROJECT_BINARY_DIR}/oplkdrv_daemon_o.elf + COMMAND arm-none-eabi-objcopy -I elf32-little -O elf32-little -R .local_memory -R .vectors.* ${EXECUTABLE_NAME} ${PROJECT_BINARY_DIR}/oplkdrv_daemon_o.elf COMMAND make create-bit ) diff --git a/cmake/toolchain-xilinx-vivado-arm-linux-eabi-gnu.cmake b/cmake/toolchain-xilinx-vivado-arm-linux-eabi-gnu.cmake index d3753ed62..ca0ce742e 100644 --- a/cmake/toolchain-xilinx-vivado-arm-linux-eabi-gnu.cmake +++ b/cmake/toolchain-xilinx-vivado-arm-linux-eabi-gnu.cmake @@ -28,7 +28,7 @@ # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ################################################################################ -SET(XILINX_SDK_DIR /opt/Xilinx/SDK/2016.2 CACHE STRING "Xilinx SDK toolchain path") +SET(XILINX_SDK_DIR /opt/Xilinx/SDK/2018.2 CACHE STRING "Xilinx SDK toolchain path") ################################################################################ # Name of the target platform diff --git a/hardware/boards/xilinx-z702/mn-dual-shmem-gpio/vivado/system.xdc b/hardware/boards/xilinx-z702/mn-dual-shmem-gpio/vivado/system.xdc index ea2d55837..0f6f2e278 100644 --- a/hardware/boards/xilinx-z702/mn-dual-shmem-gpio/vivado/system.xdc +++ b/hardware/boards/xilinx-z702/mn-dual-shmem-gpio/vivado/system.xdc @@ -1,46 +1,105 @@ -###SYSTEM CLOCK and RESET -set_property PACKAGE_PIN F19 [get_ports reset] -set_property IOSTANDARD LVCMOS25 [get_ports reset] -set_property PIO_DIRECTION INPUT [get_ports reset] +#####PCP_BENCHMARK +set_property IOSTANDARD LVCMOS25 [get_ports {BENCHMARK_PIO_tri_io[7]}] +set_property IOSTANDARD LVCMOS25 [get_ports {BENCHMARK_PIO_tri_io[6]}] +set_property IOSTANDARD LVCMOS25 [get_ports {BENCHMARK_PIO_tri_io[5]}] +set_property IOSTANDARD LVCMOS25 [get_ports {BENCHMARK_PIO_tri_io[4]}] +set_property IOSTANDARD LVCMOS25 [get_ports {BENCHMARK_PIO_tri_io[3]}] +set_property IOSTANDARD LVCMOS25 [get_ports {BENCHMARK_PIO_tri_io[2]}] +set_property IOSTANDARD LVCMOS25 [get_ports {BENCHMARK_PIO_tri_io[1]}] +set_property IOSTANDARD LVCMOS25 [get_ports {BENCHMARK_PIO_tri_io[0]}] +set_property PACKAGE_PIN AB20 [get_ports {BENCHMARK_PIO_tri_io[7]}] +set_property PACKAGE_PIN AB19 [get_ports {BENCHMARK_PIO_tri_io[6]}] +set_property PACKAGE_PIN W13 [get_ports {BENCHMARK_PIO_tri_io[5]}] +set_property PACKAGE_PIN V13 [get_ports {BENCHMARK_PIO_tri_io[4]}] +set_property PACKAGE_PIN AB16 [get_ports {BENCHMARK_PIO_tri_io[3]}] +set_property PACKAGE_PIN AA16 [get_ports {BENCHMARK_PIO_tri_io[2]}] +set_property PACKAGE_PIN V15 [get_ports {BENCHMARK_PIO_tri_io[1]}] +set_property PACKAGE_PIN V14 [get_ports {BENCHMARK_PIO_tri_io[0]}] +set_property PIO_DIRECTION BIDIR [get_ports {benchmark_pio_tri_io[7]}] +set_property PIO_DIRECTION BIDIR [get_ports {benchmark_pio_tri_io[6]}] +set_property PIO_DIRECTION BIDIR [get_ports {benchmark_pio_tri_io[5]}] +set_property PIO_DIRECTION BIDIR [get_ports {benchmark_pio_tri_io[4]}] +set_property PIO_DIRECTION BIDIR [get_ports {benchmark_pio_tri_io[3]}] +set_property PIO_DIRECTION BIDIR [get_ports {benchmark_pio_tri_io[2]}] +set_property PIO_DIRECTION BIDIR [get_ports {benchmark_pio_tri_io[1]}] +set_property PIO_DIRECTION BIDIR [get_ports {benchmark_pio_tri_io[0]}] +######################################################################## + +#HOST_BENCHMARK +set_property IOSTANDARD LVCMOS25 [get_ports {HOST_BENCHMARK_PIO_tri_io[7]}] +set_property IOSTANDARD LVCMOS25 [get_ports {HOST_BENCHMARK_PIO_tri_io[6]}] +set_property IOSTANDARD LVCMOS25 [get_ports {HOST_BENCHMARK_PIO_tri_io[5]}] +set_property IOSTANDARD LVCMOS25 [get_ports {HOST_BENCHMARK_PIO_tri_io[4]}] +set_property IOSTANDARD LVCMOS25 [get_ports {HOST_BENCHMARK_PIO_tri_io[3]}] +set_property IOSTANDARD LVCMOS25 [get_ports {HOST_BENCHMARK_PIO_tri_io[2]}] +set_property IOSTANDARD LVCMOS25 [get_ports {HOST_BENCHMARK_PIO_tri_io[1]}] +set_property IOSTANDARD LVCMOS25 [get_ports {HOST_BENCHMARK_PIO_tri_io[0]}] +set_property PACKAGE_PIN U16 [get_ports {HOST_BENCHMARK_PIO_tri_io[7]}] +set_property PACKAGE_PIN U15 [get_ports {HOST_BENCHMARK_PIO_tri_io[6]}] +set_property PACKAGE_PIN AB17 [get_ports {HOST_BENCHMARK_PIO_tri_io[5]}] +set_property PACKAGE_PIN AA17 [get_ports {HOST_BENCHMARK_PIO_tri_io[4]}] +set_property PACKAGE_PIN U21 [get_ports {HOST_BENCHMARK_PIO_tri_io[3]}] +set_property PACKAGE_PIN T21 [get_ports {HOST_BENCHMARK_PIO_tri_io[2]}] +set_property PACKAGE_PIN V17 [get_ports {HOST_BENCHMARK_PIO_tri_io[1]}] +set_property PACKAGE_PIN U17 [get_ports {HOST_BENCHMARK_PIO_tri_io[0]}] +set_property PIO_DIRECTION BIDIR [get_ports {host_benchmark_pio_tri_io[7]}] +set_property PIO_DIRECTION BIDIR [get_ports {host_benchmark_pio_tri_io[6]}] +set_property PIO_DIRECTION BIDIR [get_ports {host_benchmark_pio_tri_io[5]}] +set_property PIO_DIRECTION BIDIR [get_ports {host_benchmark_pio_tri_io[4]}] +set_property PIO_DIRECTION BIDIR [get_ports {host_benchmark_pio_tri_io[3]}] +set_property PIO_DIRECTION BIDIR [get_ports {host_benchmark_pio_tri_io[2]}] +set_property PIO_DIRECTION BIDIR [get_ports {host_benchmark_pio_tri_io[1]}] +set_property PIO_DIRECTION BIDIR [get_ports {host_benchmark_pio_tri_io[0]}] ######################################################################## #####ON BOARD LEDS -set_property PACKAGE_PIN P17 [get_ports {leds_6bit_tri_o[0]}] -set_property IOSTANDARD LVCMOS25 [get_ports {leds_6bit_tri_o[0]}] -set_property PIO_DIRECTION OUTPUT [get_ports {leds_6bit_tri_o[0]}] -set_property PACKAGE_PIN P18 [get_ports {leds_6bit_tri_o[1]}] -set_property IOSTANDARD LVCMOS25 [get_ports {leds_6bit_tri_o[1]}] -set_property PIO_DIRECTION OUTPUT [get_ports {leds_6bit_tri_o[1]}] -set_property PACKAGE_PIN W10 [get_ports {leds_6bit_tri_o[2]}] -set_property IOSTANDARD LVCMOS25 [get_ports {leds_6bit_tri_o[2]}] -set_property PIO_DIRECTION OUTPUT [get_ports {leds_6bit_tri_o[2]}] -set_property PACKAGE_PIN V7 [get_ports {leds_6bit_tri_o[3]}] -set_property IOSTANDARD LVCMOS25 [get_ports {leds_6bit_tri_o[3]}] -set_property PIO_DIRECTION OUTPUT [get_ports {leds_6bit_tri_o[3]}] -set_property PACKAGE_PIN W5 [get_ports {leds_6bit_tri_o[4]}] -set_property IOSTANDARD LVCMOS25 [get_ports {leds_6bit_tri_o[4]}] -set_property PIO_DIRECTION OUTPUT [get_ports {leds_6bit_tri_o[4]}] -set_property PACKAGE_PIN W17 [get_ports {leds_6bit_tri_o[5]}] -set_property IOSTANDARD LVCMOS25 [get_ports {leds_6bit_tri_o[5]}] +set_property IOSTANDARD LVCMOS25 [get_ports {LEDS_6BIT_tri_o[5]}] +set_property IOSTANDARD LVCMOS25 [get_ports {LEDS_6BIT_tri_o[4]}] +set_property IOSTANDARD LVCMOS25 [get_ports {LEDS_6BIT_tri_o[3]}] +set_property IOSTANDARD LVCMOS25 [get_ports {LEDS_6BIT_tri_o[2]}] +set_property IOSTANDARD LVCMOS25 [get_ports {LEDS_6BIT_tri_o[1]}] +set_property IOSTANDARD LVCMOS25 [get_ports {LEDS_6BIT_tri_o[0]}] +set_property PACKAGE_PIN W17 [get_ports {LEDS_6BIT_tri_o[5]}] +set_property PACKAGE_PIN W5 [get_ports {LEDS_6BIT_tri_o[4]}] +set_property PACKAGE_PIN V7 [get_ports {LEDS_6BIT_tri_o[3]}] +set_property PACKAGE_PIN W10 [get_ports {LEDS_6BIT_tri_o[2]}] +set_property PACKAGE_PIN P18 [get_ports {LEDS_6BIT_tri_o[1]}] +set_property PACKAGE_PIN P17 [get_ports {LEDS_6BIT_tri_o[0]}] set_property PIO_DIRECTION OUTPUT [get_ports {leds_6bit_tri_o[5]}] +set_property PIO_DIRECTION OUTPUT [get_ports {leds_6bit_tri_o[4]}] +set_property PIO_DIRECTION OUTPUT [get_ports {leds_6bit_tri_o[3]}] +set_property PIO_DIRECTION OUTPUT [get_ports {leds_6bit_tri_o[2]}] +set_property PIO_DIRECTION OUTPUT [get_ports {leds_6bit_tri_o[1]}] +set_property PIO_DIRECTION OUTPUT [get_ports {leds_6bit_tri_o[0]}] +######################################################################## + +####POWERLINK NODESWITCH +set_property IOSTANDARD LVCMOS25 [get_ports {NODE_SWITCHES_tri_io[1]}] +set_property IOSTANDARD LVCMOS25 [get_ports {NODE_SWITCHES_tri_io[0]}] +set_property PACKAGE_PIN W6 [get_ports {NODE_SWITCHES_tri_io[1]}] +set_property PACKAGE_PIN W7 [get_ports {NODE_SWITCHES_tri_io[0]}] +set_property PIO_DIRECTION BIDIR [get_ports {node_switches_tri_io[1]}] +set_property PIO_DIRECTION BIDIR [get_ports {node_switches_tri_io[0]}] ######################################################################## ####POWERLINK STATUS LEDS -set_property PACKAGE_PIN D15 [get_ports {powerlink_led_tri_o[0]}] -set_property IOSTANDARD LVCMOS25 [get_ports {powerlink_led_tri_o[0]}] +set_property IOSTANDARD LVCMOS25 [get_ports {POWERLINK_LED_tri_o[1]}] +set_property IOSTANDARD LVCMOS25 [get_ports {POWERLINK_LED_tri_o[0]}] +set_property PACKAGE_PIN D15 [get_ports {POWERLINK_LED_tri_o[0]}] +set_property PACKAGE_PIN E15 [get_ports {POWERLINK_LED_tri_o[1]}] set_property PIO_DIRECTION OUTPUT [get_ports {powerlink_led_tri_o[0]}] -set_property PACKAGE_PIN E15 [get_ports {powerlink_led_tri_o[1]}] -set_property IOSTANDARD LVCMOS25 [get_ports {powerlink_led_tri_o[1]}] set_property PIO_DIRECTION OUTPUT [get_ports {powerlink_led_tri_o[1]}] ######################################################################## -####POWERLINK NODESWITCH -set_property PACKAGE_PIN W7 [get_ports {node_switches_tri_io[0]}] -set_property IOSTANDARD LVCMOS25 [get_ports {node_switches_tri_io[0]}] -set_property PIO_DIRECTION BIDIR [get_ports {node_switches_tri_io[0]}] -set_property PACKAGE_PIN W6 [get_ports {node_switches_tri_io[1]}] -set_property IOSTANDARD LVCMOS25 [get_ports {node_switches_tri_io[1]}] -set_property PIO_DIRECTION BIDIR [get_ports {node_switches_tri_io[1]}] +set_property PACKAGE_PIN N17 [get_ports {SMI_mdio_io[1]}] +set_property PACKAGE_PIN N15 [get_ports {SMI_mdio_io[0]}] +set_property IOSTANDARD LVCMOS25 [get_ports {SMI_mdio_io[1]}] +set_property IOSTANDARD LVCMOS25 [get_ports {SMI_mdio_io[0]}] + +###SYSTEM CLOCK and RESET +set_property PACKAGE_PIN F19 [get_ports reset] +set_property IOSTANDARD LVCMOS25 [get_ports reset] +set_property PIO_DIRECTION INPUT [get_ports reset] ######################################################################## ###########FMC (1) @@ -169,62 +228,6 @@ set_property IOSTANDARD LVCMOS25 [get_ports {MII_rxd[4]}] set_property PIO_DIRECTION INPUT [get_ports {MII_rxd[4]}] ######################################################################## -####FMC (2) -### Connector (FMC-105-DEBUG J1) -#HOST_BENCHMARK -set_property PACKAGE_PIN U17 [get_ports {host_benchmark_pio_tri_io[0]}] -set_property IOSTANDARD LVCMOS25 [get_ports {host_benchmark_pio_tri_io[0]}] -set_property PIO_DIRECTION BIDIR [get_ports {host_benchmark_pio_tri_io[0]}] -set_property PACKAGE_PIN V17 [get_ports {host_benchmark_pio_tri_io[1]}] -set_property IOSTANDARD LVCMOS25 [get_ports {host_benchmark_pio_tri_io[1]}] -set_property PIO_DIRECTION BIDIR [get_ports {host_benchmark_pio_tri_io[1]}] -set_property PACKAGE_PIN T21 [get_ports {host_benchmark_pio_tri_io[2]}] -set_property IOSTANDARD LVCMOS25 [get_ports {host_benchmark_pio_tri_io[2]}] -set_property PIO_DIRECTION BIDIR [get_ports {host_benchmark_pio_tri_io[2]}] -set_property PACKAGE_PIN U21 [get_ports {host_benchmark_pio_tri_io[3]}] -set_property IOSTANDARD LVCMOS25 [get_ports {host_benchmark_pio_tri_io[3]}] -set_property PIO_DIRECTION BIDIR [get_ports {host_benchmark_pio_tri_io[3]}] -set_property PACKAGE_PIN AA17 [get_ports {host_benchmark_pio_tri_io[4]}] -set_property IOSTANDARD LVCMOS25 [get_ports {host_benchmark_pio_tri_io[4]}] -set_property PIO_DIRECTION BIDIR [get_ports {host_benchmark_pio_tri_io[4]}] -set_property PACKAGE_PIN AB17 [get_ports {host_benchmark_pio_tri_io[5]}] -set_property IOSTANDARD LVCMOS25 [get_ports {host_benchmark_pio_tri_io[5]}] -set_property PIO_DIRECTION BIDIR [get_ports {host_benchmark_pio_tri_io[5]}] -set_property PACKAGE_PIN U15 [get_ports {host_benchmark_pio_tri_io[6]}] -set_property IOSTANDARD LVCMOS25 [get_ports {host_benchmark_pio_tri_io[6]}] -set_property PIO_DIRECTION BIDIR [get_ports {host_benchmark_pio_tri_io[6]}] -set_property PACKAGE_PIN U16 [get_ports {host_benchmark_pio_tri_io[7]}] -set_property IOSTANDARD LVCMOS25 [get_ports {host_benchmark_pio_tri_io[7]}] -set_property PIO_DIRECTION BIDIR [get_ports {host_benchmark_pio_tri_io[7]}] -######################################################################## - -#####PCP_BENCHMARK -set_property PACKAGE_PIN V14 [get_ports {benchmark_pio_tri_io[0]}] -set_property IOSTANDARD LVCMOS25 [get_ports {benchmark_pio_tri_io[0]}] -set_property PIO_DIRECTION BIDIR [get_ports {benchmark_pio_tri_io[0]}] -set_property PACKAGE_PIN V15 [get_ports {benchmark_pio_tri_io[1]}] -set_property IOSTANDARD LVCMOS25 [get_ports {benchmark_pio_tri_io[1]}] -set_property PIO_DIRECTION BIDIR [get_ports {benchmark_pio_tri_io[1]}] -set_property PACKAGE_PIN AA16 [get_ports {benchmark_pio_tri_io[2]}] -set_property IOSTANDARD LVCMOS25 [get_ports {benchmark_pio_tri_io[2]}] -set_property PIO_DIRECTION BIDIR [get_ports {benchmark_pio_tri_io[2]}] -set_property PACKAGE_PIN AB16 [get_ports {benchmark_pio_tri_io[3]}] -set_property IOSTANDARD LVCMOS25 [get_ports {benchmark_pio_tri_io[3]}] -set_property PIO_DIRECTION BIDIR [get_ports {benchmark_pio_tri_io[3]}] -set_property PACKAGE_PIN V13 [get_ports {benchmark_pio_tri_io[4]}] -set_property IOSTANDARD LVCMOS25 [get_ports {benchmark_pio_tri_io[4]}] -set_property PIO_DIRECTION BIDIR [get_ports {benchmark_pio_tri_io[4]}] -set_property PACKAGE_PIN W13 [get_ports {benchmark_pio_tri_io[5]}] -set_property IOSTANDARD LVCMOS25 [get_ports {benchmark_pio_tri_io[5]}] -set_property PIO_DIRECTION BIDIR [get_ports {benchmark_pio_tri_io[5]}] -set_property PACKAGE_PIN AB19 [get_ports {benchmark_pio_tri_io[6]}] -set_property IOSTANDARD LVCMOS25 [get_ports {benchmark_pio_tri_io[6]}] -set_property PIO_DIRECTION BIDIR [get_ports {benchmark_pio_tri_io[6]}] -set_property PACKAGE_PIN AB20 [get_ports {benchmark_pio_tri_io[7]}] -set_property IOSTANDARD LVCMOS25 [get_ports {benchmark_pio_tri_io[7]}] -set_property PIO_DIRECTION BIDIR [get_ports {benchmark_pio_tri_io[7]}] -######################################################################## - #VIRTUAL CLOCK create_clock -period 10.000 -name clock_out1 -add [get_nets system_i/clock_generator/clk_out1] create_clock -period 20.000 -name clock_out2 -add [get_nets system_i/clock_generator/clk_out2] @@ -333,60 +336,3 @@ set_false_path -reset_path -from [get_clocks clk_mii0_rx] -to [get_clocks clk_mi set_false_path -reset_path -from [get_clocks clk_mii1_rx] -to [get_clocks clk_mii1_rx] ######################################################################## -set_property IOSTANDARD LVCMOS25 [get_ports {BENCHMARK_PIO_tri_io[7]}] -set_property IOSTANDARD LVCMOS25 [get_ports {BENCHMARK_PIO_tri_io[6]}] -set_property IOSTANDARD LVCMOS25 [get_ports {BENCHMARK_PIO_tri_io[5]}] -set_property IOSTANDARD LVCMOS25 [get_ports {BENCHMARK_PIO_tri_io[4]}] -set_property IOSTANDARD LVCMOS25 [get_ports {BENCHMARK_PIO_tri_io[3]}] -set_property IOSTANDARD LVCMOS25 [get_ports {BENCHMARK_PIO_tri_io[2]}] -set_property IOSTANDARD LVCMOS25 [get_ports {BENCHMARK_PIO_tri_io[1]}] -set_property IOSTANDARD LVCMOS25 [get_ports {BENCHMARK_PIO_tri_io[0]}] -set_property IOSTANDARD LVCMOS25 [get_ports {HOST_BENCHMARK_PIO_tri_io[7]}] -set_property IOSTANDARD LVCMOS25 [get_ports {HOST_BENCHMARK_PIO_tri_io[6]}] -set_property IOSTANDARD LVCMOS25 [get_ports {HOST_BENCHMARK_PIO_tri_io[5]}] -set_property IOSTANDARD LVCMOS25 [get_ports {HOST_BENCHMARK_PIO_tri_io[4]}] -set_property IOSTANDARD LVCMOS25 [get_ports {HOST_BENCHMARK_PIO_tri_io[3]}] -set_property IOSTANDARD LVCMOS25 [get_ports {HOST_BENCHMARK_PIO_tri_io[2]}] -set_property IOSTANDARD LVCMOS25 [get_ports {HOST_BENCHMARK_PIO_tri_io[1]}] -set_property IOSTANDARD LVCMOS25 [get_ports {HOST_BENCHMARK_PIO_tri_io[0]}] -set_property PACKAGE_PIN AB20 [get_ports {BENCHMARK_PIO_tri_io[7]}] -set_property PACKAGE_PIN AB19 [get_ports {BENCHMARK_PIO_tri_io[6]}] -set_property PACKAGE_PIN W13 [get_ports {BENCHMARK_PIO_tri_io[5]}] -set_property PACKAGE_PIN V13 [get_ports {BENCHMARK_PIO_tri_io[4]}] -set_property PACKAGE_PIN AB16 [get_ports {BENCHMARK_PIO_tri_io[3]}] -set_property PACKAGE_PIN AA16 [get_ports {BENCHMARK_PIO_tri_io[2]}] -set_property PACKAGE_PIN V15 [get_ports {BENCHMARK_PIO_tri_io[1]}] -set_property PACKAGE_PIN V14 [get_ports {BENCHMARK_PIO_tri_io[0]}] -set_property PACKAGE_PIN U16 [get_ports {HOST_BENCHMARK_PIO_tri_io[7]}] -set_property PACKAGE_PIN U15 [get_ports {HOST_BENCHMARK_PIO_tri_io[6]}] -set_property PACKAGE_PIN AB17 [get_ports {HOST_BENCHMARK_PIO_tri_io[5]}] -set_property PACKAGE_PIN AA17 [get_ports {HOST_BENCHMARK_PIO_tri_io[4]}] -set_property PACKAGE_PIN U21 [get_ports {HOST_BENCHMARK_PIO_tri_io[3]}] -set_property PACKAGE_PIN T21 [get_ports {HOST_BENCHMARK_PIO_tri_io[2]}] -set_property PACKAGE_PIN V17 [get_ports {HOST_BENCHMARK_PIO_tri_io[1]}] -set_property PACKAGE_PIN U17 [get_ports {HOST_BENCHMARK_PIO_tri_io[0]}] -set_property IOSTANDARD LVCMOS25 [get_ports {LEDS_6BIT_tri_o[5]}] -set_property IOSTANDARD LVCMOS25 [get_ports {LEDS_6BIT_tri_o[4]}] -set_property IOSTANDARD LVCMOS25 [get_ports {LEDS_6BIT_tri_o[3]}] -set_property IOSTANDARD LVCMOS25 [get_ports {LEDS_6BIT_tri_o[2]}] -set_property IOSTANDARD LVCMOS25 [get_ports {LEDS_6BIT_tri_o[1]}] -set_property IOSTANDARD LVCMOS25 [get_ports {LEDS_6BIT_tri_o[0]}] -set_property PACKAGE_PIN W17 [get_ports {LEDS_6BIT_tri_o[5]}] -set_property PACKAGE_PIN W5 [get_ports {LEDS_6BIT_tri_o[4]}] -set_property PACKAGE_PIN V7 [get_ports {LEDS_6BIT_tri_o[3]}] -set_property PACKAGE_PIN W10 [get_ports {LEDS_6BIT_tri_o[2]}] -set_property PACKAGE_PIN P18 [get_ports {LEDS_6BIT_tri_o[1]}] -set_property PACKAGE_PIN P17 [get_ports {LEDS_6BIT_tri_o[0]}] -set_property IOSTANDARD LVCMOS25 [get_ports {NODE_SWITCHES_tri_io[1]}] -set_property IOSTANDARD LVCMOS25 [get_ports {NODE_SWITCHES_tri_io[0]}] -set_property PACKAGE_PIN W6 [get_ports {NODE_SWITCHES_tri_io[1]}] -set_property PACKAGE_PIN W7 [get_ports {NODE_SWITCHES_tri_io[0]}] -set_property IOSTANDARD LVCMOS25 [get_ports {POWERLINK_LED_tri_o[1]}] -set_property IOSTANDARD LVCMOS25 [get_ports {POWERLINK_LED_tri_o[0]}] -set_property PACKAGE_PIN D15 [get_ports {POWERLINK_LED_tri_o[0]}] -set_property PACKAGE_PIN E15 [get_ports {POWERLINK_LED_tri_o[1]}] -set_property PACKAGE_PIN N17 [get_ports {SMI_mdio_io[1]}] -set_property PACKAGE_PIN N15 [get_ports {SMI_mdio_io[0]}] -set_property IOSTANDARD LVCMOS25 [get_ports {SMI_mdio_io[1]}] -set_property IOSTANDARD LVCMOS25 [get_ports {SMI_mdio_io[0]}] - diff --git a/hardware/boards/xilinx-z702/mn-dual-shmem-gpio/vivado/system_bd.tcl b/hardware/boards/xilinx-z702/mn-dual-shmem-gpio/vivado/system_bd.tcl index 0c390159d..fcff9875a 100644 --- a/hardware/boards/xilinx-z702/mn-dual-shmem-gpio/vivado/system_bd.tcl +++ b/hardware/boards/xilinx-z702/mn-dual-shmem-gpio/vivado/system_bd.tcl @@ -55,6 +55,9 @@ set_property target_language VHDL [current_project] set proj_dir [get_property directory $obj] set_property ip_repo_paths $proj_dir/../../../../../ipcore/xilinx [current_project] update_ip_catalog + +# CHANGE DESIGN NAME HERE +variable design_name set design_name system # If you do not already have an existing IP Integrator design open, @@ -1303,12 +1306,6 @@ proc create_root_design { parentCell } { CONFIG.preset {ZC702} \ ] $processing_system7_0 - # Create instance: xlconcat_0, and set properties - set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] - set_property -dict [ list \ - CONFIG.NUM_PORTS {1} \ - ] $xlconcat_0 - # Create interface connections connect_bd_intf_net -intf_net BENCHMARK_PIO_GPIO [get_bd_intf_ports BENCHMARK_PIO] [get_bd_intf_pins BENCHMARK_PIO/GPIO] connect_bd_intf_net -intf_net CLK_IN1_D_1 [get_bd_intf_ports clk_in] [get_bd_intf_pins clock_generator/CLK_IN1_D] @@ -1345,7 +1342,7 @@ proc create_root_design { parentCell } { connect_bd_net -net S00_ARESETN_1 [get_bd_pins HOST_BENCHMARK_PIO/s_axi_aresetn] [get_bd_pins LEDS_6BIT/s_axi_aresetn] [get_bd_pins Node_Switches/s_axi_aresetn] [get_bd_pins axi4lite_0/M00_ARESETN] [get_bd_pins axi4lite_0/M01_ARESETN] [get_bd_pins axi4lite_0/M02_ARESETN] [get_bd_pins axi4lite_0/S00_ARESETN] [get_bd_pins proc_sys_rst1/peripheral_aresetn] connect_bd_net -net axi_openmac_0_MAC_IRQ [get_bd_pins axi_openmac_0/MAC_IRQ] [get_bd_pins pcp_xlconcat/In1] connect_bd_net -net axi_openmac_0_TIMER_IRQ [get_bd_pins axi_openmac_0/TIMER_IRQ] [get_bd_pins pcp_xlconcat/In0] - connect_bd_net -net axi_openmac_0_TIMER_PULSE_IRQ [get_bd_pins axi_openmac_0/TIMER_PULSE_IRQ] [get_bd_pins xlconcat_0/In0] + connect_bd_net -net axi_openmac_0_TIMER_PULSE_IRQ [get_bd_pins axi_openmac_0/TIMER_PULSE_IRQ] [get_bd_pins processing_system7_0/IRQ_F2P] connect_bd_net -net axi_openmac_0_oSmi_nPhyRst [get_bd_ports oSmi_nPhyRst] [get_bd_pins axi_openmac_0/oSmi_nPhyRst] connect_bd_net -net clock_generator_clk_out2 [get_bd_pins axi4lite_mb_0/M03_ACLK] [get_bd_pins axi_openmac_0/S_AXI_MAC_REG_ACLK] [get_bd_pins axi_openmac_0/iClk50] [get_bd_pins clock_generator/clk_out2] [get_bd_pins fit_timer_0/Clk] [get_bd_pins proc_sys_rst/slowest_sync_clk] connect_bd_net -net clock_generator_locked [get_bd_pins clock_generator/locked] [get_bd_pins proc_sys_rst/dcm_locked] @@ -1364,7 +1361,6 @@ proc create_root_design { parentCell } { connect_bd_net -net rst_clk_wiz_1_100M_bus_struct_reset [get_bd_pins pcp_bram/SYS_Rst] [get_bd_pins proc_sys_rst/bus_struct_reset] connect_bd_net -net rst_clk_wiz_1_100M_interconnect_aresetn [get_bd_pins axi4lite_mb_0/ARESETN] [get_bd_pins axi_0/ARESETN] [get_bd_pins proc_sys_rst/interconnect_aresetn] connect_bd_net -net rst_clk_wiz_1_100M_peripheral_aresetn [get_bd_pins BENCHMARK_PIO/s_axi_aresetn] [get_bd_pins POWERLINK_Led/s_axi_aresetn] [get_bd_pins axi4lite_mb_0/M00_ARESETN] [get_bd_pins axi4lite_mb_0/M01_ARESETN] [get_bd_pins axi4lite_mb_0/M02_ARESETN] [get_bd_pins axi4lite_mb_0/M03_ARESETN] [get_bd_pins axi4lite_mb_0/M04_ARESETN] [get_bd_pins axi4lite_mb_0/M05_ARESETN] [get_bd_pins axi4lite_mb_0/M06_ARESETN] [get_bd_pins axi4lite_mb_0/S00_ARESETN] [get_bd_pins axi_0/M00_ARESETN] [get_bd_pins axi_0/S00_ARESETN] [get_bd_pins axi_0/S01_ARESETN] [get_bd_pins axi_0/S02_ARESETN] [get_bd_pins axi_openmac_0/M_AXI_MAC_DMA_ARESETN] [get_bd_pins axi_openmac_0/S_AXI_MAC_PKT_ARESETN] [get_bd_pins axi_openmac_0/S_AXI_MAC_REG_ARESETN] [get_bd_pins debug_module/S_AXI_ARESETN] [get_bd_pins fit_timer_0/Rst] [get_bd_pins pcp_intc/s_axi_aresetn] [get_bd_pins proc_sys_rst/peripheral_aresetn] - connect_bd_net -net xlconcat_0_dout [get_bd_pins processing_system7_0/IRQ_F2P] [get_bd_pins xlconcat_0/dout] # Create address segments create_bd_addr_seg -range 0x20000000 -offset 0x20000000 [get_bd_addr_spaces axi_openmac_0/M_AXI_MAC_DMA] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM From 73e5a155655c5b1173948361eb3030b406c852ca Mon Sep 17 00:00:00 2001 From: Hassen Date: Thu, 11 Oct 2018 17:19:20 +0200 Subject: [PATCH 3/3] when data 0XFFFF, stucking at same port hEth->phyCount-1 --- hardware/drivers/openmac/src/omethlib.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hardware/drivers/openmac/src/omethlib.c b/hardware/drivers/openmac/src/omethlib.c index b0dde076d..6049ff2f1 100644 --- a/hardware/drivers/openmac/src/omethlib.c +++ b/hardware/drivers/openmac/src/omethlib.c @@ -545,7 +545,7 @@ static OMETH_H omethCreateInt hEth->phyCmdWrite[hEth->phyCount] = data | PHY_REG_WRITE; hEth->phyCount++; - omethPhyRead(hEth, hEth->phyCount-1, 1, &data); // get register 1 to count linked ports at startup + omethPhyRead(hEth, i, 1, &data); // get register 1 to count linked ports at startup if(data==0xFFFF) {