run dsp at 192kHz instead of 48kHz to prevent feedback in transparancy mode

Author: mkuettner97

src/drivers/ADAU1860.cpp

@@ -175,12 +175,33 @@ int ADAU1860::begin() {
                 // uint8_t spt0_route1 = 40; // DMIC Channel 1
                 // writeReg(registers::SPT0_ROUTE1, &spt0_route1, sizeof(spt0_route1));
 
-                uint8_t ascro0_route = 35; // DMIC Channel 0
+                uint8_t fdec_pwr = 0x03; // FDEC0_EN | FDEC1_EN
+                writeReg(registers::FDEC_PWR, &fdec_pwr, sizeof(fdec_pwr));
+
+                uint8_t fdec_ctrl1 = 0x24; // 192khz to 48kHz
+                writeReg(registers::FDEC_CTRL1, &fdec_ctrl1, sizeof(fdec_ctrl1));
+
+                uint8_t fdec_route0 = 39; // DMIC Channel 0
+                writeReg(registers::FDEC_ROUTE0, &fdec_route0, sizeof(fdec_route0));
+                
+                uint8_t fdec_route1 = 40; // DMIC Channel 1
+                writeReg(registers::FDEC_ROUTE1, &fdec_route1, sizeof(fdec_route1));
+
+                uint8_t ascro0_route = 39; // FDEC Channel 0
                 writeReg(registers::ASRCO_ROUTE0, &ascro0_route, sizeof(ascro0_route));
 
-                uint8_t ascro1_route = 36; // DMIC Channel 1
+                uint8_t ascro1_route = 40; // FDEC Channel 1
                 writeReg(registers::ASRCO_ROUTE1, &ascro1_route, sizeof(ascro1_route));
 
+                /*uint8_t fint_pwr = 0x01; // FINT0_EN
+                writeReg(registers::FINT_PWR, &fint_pwr, sizeof(fint_pwr));
+
+                uint8_t fint_ctrl1 = 0x42; // 48kHz to 192kHz
+                writeReg(registers::FINT_CTRL1, &fint_ctrl1, sizeof(fint_ctrl1));
+
+                uint8_t fint_route0 = 75; // EQ
+                writeReg(registers::FINT_ROUTE0, &fint_route0, sizeof(fint_route0));*/
+
                 uint8_t spt0_route0 = 32; // ASCRO 0
                 writeReg(registers::SPT0_ROUTE0, &spt0_route0, sizeof(spt0_route0));
 
@@ -195,7 +216,7 @@ int ADAU1860::begin() {
                 uint8_t dmic_ctrl1 = 0x34; // ... | 6.144 MHz
                 writeReg(registers::DMIC_CTRL1, &dmic_ctrl1, sizeof(dmic_ctrl1));
 
-                uint8_t dmic_ctrl2 = 0x02; // 48kHz
+                uint8_t dmic_ctrl2 = 0x04; // 192kHz
                 writeReg(registers::DMIC_CTRL2, &dmic_ctrl2, sizeof(dmic_ctrl2));
         } else {
                 // I2S_IN enable
@@ -244,6 +265,9 @@ int ADAU1860::setup_DAC() {
         uint8_t hpldo_ctrl = 0x01;
         writeReg(registers::HPLDO_CTRL, &hpldo_ctrl, sizeof(hpldo_ctrl));
 
+        uint8_t dac_ctrl1 = 0x04; // 192kz
+        writeReg(registers::DAC_CTRL1, &dac_ctrl1, sizeof(dac_ctrl1));
+
         // DAC_NOISE_CTRL1&2
         uint8_t dac_noise_1 = 0x10;
         uint8_t dac_noise_2 = 0x02;

src/drivers/Lark-fdsp.c

@@ -42,18 +42,18 @@ uint32_t fdsp_param_bank_a[5][10] =
 
 uint32_t fdsp_param_bank_b[5][10] =
 {
-    {0x07D19614, 0x0856E0D4, 0x05BE7F17, 0x08000C80, 0x17F00000, 0xC9F00000, 0xD1A40000, 0xC8000000, 0x00000000, 0x00000000},
-    {0xF06710F4, 0xF22267DA, 0xF70710E3, 0x04000D00, 0x00000000, 0x00000000, 0x05000000, 0x00000000, 0x00000000, 0x00000000},
-    {0x07C75D41, 0x0603EEA5, 0x053E298E, 0x00010000, 0x02014700, 0x00014700, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
-    {0x0F981AA1, 0x0DDD9826, 0x08F8EF1D, 0x00004000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
-    {0xF866383F, 0xF9A53086, 0xFD03575A, 0x82080000, 0x04000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}
+    {0x07F44096, 0x0817C80D, 0x0738E023, 0x08000C80, 0x17F00000, 0xC9F00000, 0xD1A40000, 0xC8000000, 0x00000000, 0x00000000},
+    {0xF01A19E9, 0xF07BD10B, 0xF1E5A0E2, 0x04000D00, 0x00000000, 0x00000000, 0x04800000, 0x00000000, 0x00000000, 0x00000000},
+    {0x07F1A5C6, 0x0774ECCA, 0x070CA02B, 0x00010000, 0x02014700, 0x00014700, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
+    {0x0FE5D88E, 0x0F842EF5, 0x0E1A5F1E, 0x00004000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+    {0xF81A0C1B, 0xF8734B28, 0xF9BA7FB1, 0x82080000, 0x04000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}
 };
 
 uint32_t fdsp_param_bank_c[5][10] =
 {
-    {0x0014F474, 0x0014F474, 0x0014F474, 0x00000C80, 0x17F00000, 0xC9F00000, 0xD1A40000, 0xC8000000, 0x00000000, 0x00000000},
-    {0xFFD7273C, 0xFFD7273C, 0xFFD7273C, 0x00000D00, 0x00000000, 0x00000000, 0xFB000000, 0x00000000, 0x00000000, 0x00000000},
-    {0x0013E8B4, 0x0013E8B4, 0x0013E8B4, 0x00000300, 0x02014700, 0x00014700, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
-    {0x0FF5861A, 0x0FF5861A, 0x0FF5861A, 0x00000300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
-    {0xF80A7582, 0xF80A7582, 0xF80A7582, 0x80000000, 0x04000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}
+    {0x00149920, 0x00149920, 0x00149920, 0x00000C80, 0x17F00000, 0xC9F00000, 0xD1A40000, 0xC8000000, 0x00000000, 0x00000000},
+    {0xFFD71116, 0xFFD71116, 0xFFD71116, 0x00000D00, 0x00000000, 0x00000000, 0xFC000000, 0x00000000, 0x00000000, 0x00000000},
+    {0x0014560F, 0x0014560F, 0x0014560F, 0x00000300, 0x02014700, 0x00014700, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
+    {0x0FFD6111, 0x0FFD6111, 0x0FFD6111, 0x00000300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+    {0xF8029EA9, 0xF8029EA9, 0xF8029EA9, 0x80000000, 0x04000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}
 };