frontend: Add zero register constraint annotation

Author: Jozott00

vadl/main/vadl/ast/AnnotationTable.java

@@ -40,7 +40,9 @@
 import vadl.utils.WithLocation;
 import vadl.utils.functionInterfaces.TriConsumer;
 import vadl.viam.AssemblyDescription;
+import vadl.viam.Constant;
 import vadl.viam.MemoryRegion;
+import vadl.viam.RegisterTensor;
 import vadl.viam.Relocation;
 import vadl.viam.annotations.AsmParserCaseSensitive;
 import vadl.viam.annotations.AsmParserCommentString;
@@ -73,9 +75,13 @@ class AnnotationTable {
         // FIXME: Apply to AST
         .build();
 
-    annotationOn(RegisterFileDefinition.class, "zero", ExprAnnotation::new)
-        // FIXME: Typecheck
-        // FIXME: Apply to VIAM
+    annotationOn(RegisterFileDefinition.class, "zero", ZeroConstraintAnnotation::new)
+        .applyViam((def, annotation, lowering) -> {
+          var viamDef = (RegisterTensor) def;
+          var indices = annotation.indices.stream().map(ConstantValue::toViamConstant).toList();
+          var zero = Constant.Value.of(0, viamDef.resultType(indices.size()));
+          viamDef.addConstraint(new RegisterTensor.Constraint(indices, zero));
+        })
         .build();
 
     groupOn(RelocationDefinition.class)
@@ -1045,4 +1051,63 @@ void typeCheck(AnnotationDefinition definition, TypeChecker typeChecker) {
   public String usageString() {
     return "[ " + name + " : <expr> ]";
   }
+
 }
+
+/**
+ * The {@code [ zero : <register>(<expr>) ]} annotation.
+ * This is its own class, as the typechecking is rather complex and determines
+ * new properties.
+ */
+class ZeroConstraintAnnotation extends ExprAnnotation {
+  @LazyInit
+  List<ConstantValue> indices;
+
+  @Override
+  void typeCheck(AnnotationDefinition definition, TypeChecker typeChecker) {
+    super.typeCheck(definition, typeChecker);
+    var def = definition.target;
+    if (!(node instanceof CallIndexExpr callExpr)) {
+      throw error("Invalid zero annotation", this)
+          .locationDescription(this, "Zero annotation must be of form %s", usageString())
+          .build();
+    }
+    if (!(callExpr.computedTarget == def)) {
+      throw error("Invalid zero annotation", callExpr.target)
+          .locationDescription(callExpr.target,
+              "Zero annotation target must be the annotated register.")
+          .locationNote(def, "This is the register to target.")
+          .build();
+    }
+
+
+    var args = callExpr.argIndicesFlatten();
+    // FIXME: Ones we have multi dimensional registers,
+    //   we must loose this restriction, so that there can be multiple indices set.
+    if (args.size() != 1) {
+      throw error("Invalid zero annotation", callExpr)
+          .locationDescription(callExpr, "Exactly one register index was expected, but found %s.",
+              args.size())
+          .note("In the future it will be possible to have constraints on multiple dimensions.")
+          .build();
+    }
+
+    this.indices = args.stream().map(expr -> {
+      try {
+        return typeChecker.constantEvaluator.eval(expr);
+      } catch (EvaluationError e) {
+        throw error("Invalid zero annotation", expr)
+            .locationDescription(expr, "Index must be a constant expression.")
+            .locationNote(def, "%s", requireNonNull(e.getMessage()))
+            .build();
+      }
+    }).toList();
+
+  }
+
+  @Override
+  public String usageString() {
+    return "[" + name + " : " + "<register>( <expr> ) ]";
+  }
+}
+

vadl/main/vadl/ast/Expr.java

@@ -1586,6 +1586,10 @@ void replaceArgsFor(int index, List<Expr> newArgs) {
     args.values.addAll(newArgs);
   }
 
+  List<Expr> argIndicesFlatten() {
+    return argsIndices.stream().flatMap(a -> a.values.stream()).toList();
+  }
+
 
   @Override
   public IsId path() {

vadl/main/vadl/ast/ViamLowering.java

@@ -782,8 +782,7 @@ public Optional<vadl.viam.Definition> visit(CounterDefinition definition) {
 
     // FIXME: Further research for the parameters (probably don't apply to counter)
     var reg = new RegisterTensor(identifier,
-        List.of(dimFromType(0, resultType)),
-        new RegisterTensor.Constraint[] {}
+        List.of(dimFromType(0, resultType))
     );
 
     var counter = new Counter(identifier,
@@ -1388,8 +1387,7 @@ public Optional<vadl.viam.Definition> visit(RegisterDefinition definition) {
     var resultType = (DataType) getViamType(definition.type());
     var reg = new RegisterTensor(
         generateIdentifier(definition.viamId, definition.identifier()),
-        List.of(dimFromType(0, resultType)),
-        new RegisterTensor.Constraint[] {}
+        List.of(dimFromType(0, resultType))
     );
     return Optional.of(reg);
   }
@@ -1399,18 +1397,12 @@ public Optional<vadl.viam.Definition> visit(RegisterFileDefinition definition) {
     var addrType = (DataType) getViamType(requireNonNull(definition.type).argTypes().get(0));
     var resultType = (DataType) getViamType(requireNonNull(definition.type).resultType());
 
-    // FIXME: Add proper constraints. This is currently only temporarily hardcoded to
-    //    fix the riscv iss simulation.
-    var zeroConstraint = new RegisterTensor.Constraint(List.of(Constant.Value.of(0, addrType)),
-        Constant.Value.of(0, resultType));
-
     var regFile = new RegisterTensor(
         generateIdentifier(definition.viamId, definition.identifier()),
         List.of(
             dimFromMappingType(0, addrType),
             dimFromType(1, resultType)
-        ),
-        new RegisterTensor.Constraint[] {zeroConstraint}
+        )
     );
     return Optional.of(regFile);
   }

vadl/main/vadl/lcb/template/lib/Target/EmitISelLoweringCppFilePass.java

@@ -23,7 +23,6 @@
 import java.util.HashMap;
 import java.util.List;
 import java.util.Map;
-import java.util.Objects;
 import java.util.function.Supplier;
 import javax.annotation.Nullable;
 import vadl.configuration.LcbConfiguration;
@@ -78,8 +77,10 @@ static class LlvmRegisterFile extends RegisterTensor {
      **/
     public LlvmRegisterFile(RegisterTensor registerFile) {
       super(registerFile.identifier,
-          registerFile.dimensions(),
-          registerFile.constraints());
+          registerFile.dimensions());
+      for (var c : registerFile.constraints()) {
+        addConstraint(c);
+      }
     }
 
     public String llvmResultType() {

vadl/main/vadl/viam/RegisterTensor.java

@@ -17,6 +17,7 @@
 package vadl.viam;
 
 import com.google.common.collect.Streams;
+import java.util.ArrayList;
 import java.util.Arrays;
 import java.util.List;
 import java.util.Optional;
@@ -75,16 +76,16 @@ public record Dimension(int index, DataType indexType, int size) {
   }
 
   private final List<Dimension> dimensions;
-  private final Constraint[] constraints;
+  private final List<Constraint> constraints;
 
   /**
    * Constructs the register tensor.
    */
-  public RegisterTensor(Identifier identifier, List<Dimension> dimensions,
-                        Constraint[] constraints) {
+  public RegisterTensor(Identifier identifier,
+                        List<Dimension> dimensions) {
     super(identifier);
     this.dimensions = dimensions;
-    this.constraints = constraints;
+    this.constraints = new ArrayList<>();
   }
 
   public int dimCount() {
@@ -103,6 +104,7 @@ public List<Dimension> indexDimensions() {
     return dimensions.subList(0, maxNumberOfAccessIndices());
   }
 
+
   public int maxNumberOfAccessIndices() {
     return dimCount() - 1;
   }
@@ -131,8 +133,13 @@ public Dimension innermostDim() {
     return dimensions.getLast();
   }
 
+  // TODO: Refactor this to return a list instead of an array
   public Constraint[] constraints() {
-    return constraints;
+    return constraints.toArray(new Constraint[0]);
+  }
+
+  public void addConstraint(Constraint constraint) {
+    constraints.add(constraint);
   }
 
   @Override