sys/risc-v: Conditionally omit EBREAK and ECALL

This allows us to "overwrite" them in the Zicsr extension.

Author: Jozott00

vadl/test/resources/testSource/sys/risc-v/rv3264im.vadl

@@ -27,6 +27,11 @@ instruction set architecture RV3264I = {
   constant Arch32 = 32                    // 32 bit architecture
   constant Arch64 = 64                    // 64 bit architecture
 
+ // use `with("DoEBreakCall=EBreakCallDisabled")` to omit EBREAK and ECALL
+  model DoEBreakCall(): Id = { EBreakCallEnabled }
+  constant EBreakCallEnabled = true
+  constant EBreakCallDisabled = false
+
   constant MLen   = $ArchSize()           // MLen = 32 or 64 depending on ArchSize
   constant SftLen = (MLen / 32) + 4       // number of bits needed for shift amount (5 or 6)
   constant WLen   = 32                    // 32 bit word length in 64 bit mode
@@ -250,8 +255,10 @@ instruction set architecture RV3264I = {
   $JLinkInstr (JALR ; Itype ; X(rs1) ; opcode = 0b110'0111,               // jump and link register
                                        funct3 = 0b000 ; imm as SInt<12> ; ("(", register(rs1), ")"))
 
-  $ECallInstr (ECALL ; 0)                              // environment (sys) call
-  //   $ECallInstr (EBREAK; 1)                              // environment (sys) break
+  match : IsaDefs ($DoEBreakCall() = EBreakCallEnabled =>
+    $ECallInstr (ECALL ; 0)  // environment (sys) call
+    $ECallInstr (EBREAK; 1)  // environment (sys) break
+  ; _  => )
 
 $Arch3264 ( // ((((((((((((((((((((((((((((((((((((((((
 

vadl/test/resources/testSource/sys/risc-v/rv32csr.vadl

@@ -3,7 +3,7 @@
 
 // RISC-V 32 IM Zicsr instruction set (CSR - Control and Status Registers)
 
-import rv3264im::RV3264IM
+import rv3264im::RV3264IM with ("DoEBreakCall=EBreakCallDisabled") // omit EBREAK and ECALL as we define them here
 
 instruction set architecture RV32IM extending RV3264IM = {}
 
@@ -136,17 +136,19 @@ instruction set architecture RV32Zicsr extending RV32IM = {
     // mstatus.mpp  := PRV::M // we only support machine mode at the moment
     // mstatus.mie  := 0
     // clear two lsb
-    PC := mtvec & ~0x3
+    PC := mtvec
   }
 
   //// INSTRUCTIONS ////
 
-  // Environment Breakpoint
-  instruction EBREAK : Itype =
-    raise Exc(ExcCode::BREAKPOINT)
+  model ECallInstr (name : Id, imm : Lit, excCode: Id) : IsaDefs = {
+    instruction $name : Itype = raise Exc(ExcCode::$excCode)                    // ecall / ebreak instructions
+    encoding $name = {opcode = 0b111'0011, funct3 = 0b000, rd = 0b0'0000, rs1 = 0b0'0000, imm = $imm}
+    assembly $name = (mnemonic)
+    }
 
-  encoding EBREAK = { opcode = 0b111'0011, funct3 = 0b000, imm = 0b0000'0000'0001, rs1 = 0b00000, rd = 0b00000 }
-  assembly EBREAK = mnemonic
+  $ECallInstr (ECALL ; 0; M_ECALL)        // environment (sys) call
+  $ECallInstr (EBREAK; 1; BREAKPOINT)     // environment (sys) break
 
   // return from trap
   instruction MRET: Itype = {