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- .github/workflows/main.yml+4-8
- HuanCun+1-1
- Makefile+4
- build.sc+8-9
- rocket-chip+1-1
- src/main/scala/coupledL2/Common.scala+5-2
- src/main/scala/coupledL2/CoupledL2.scala+44-16
- src/main/scala/coupledL2/DataStorage.scala+5-4
- src/main/scala/coupledL2/Directory.scala+48-27
- src/main/scala/coupledL2/GrantBuffer.scala+3-1
- src/main/scala/coupledL2/L2Param.scala+9-1
- src/main/scala/coupledL2/RequestArb.scala+46-13
- src/main/scala/coupledL2/SinkC.scala+2-1
- src/main/scala/coupledL2/prefetch/BestOffsetPrefetch.scala+16-7
- src/main/scala/coupledL2/prefetch/TemporalPrefetch.scala+33-14
- src/main/scala/coupledL2/tl2chi/MMIOBridge.scala+30-6
- src/main/scala/coupledL2/tl2chi/MSHR.scala+57-40
- src/main/scala/coupledL2/tl2chi/MSHRCtl.scala+21-17
- src/main/scala/coupledL2/tl2chi/MainPipe.scala+50-9
- src/main/scala/coupledL2/tl2chi/RXDAT.scala+1
- src/main/scala/coupledL2/tl2chi/TL2CHICoupledL2.scala+13-4
- src/main/scala/coupledL2/tl2chi/TXDAT.scala+2-2
- src/main/scala/coupledL2/tl2chi/TXRSP.scala+1
- src/main/scala/coupledL2/tl2chi/chi/LinkLayer.scala+85-39
- src/main/scala/coupledL2/tl2chi/chi/Message.scala+36-6
- src/main/scala/coupledL2/tl2tl/RefillUnit.scala+1
- src/main/scala/coupledL2/utils/GatedSplittedSRAM.scala+4-3
- src/main/scala/coupledL2/utils/SplittedSRAM.scala+5-5
- src/test/scala/TestProbeQueue.scala+1-2
- src/test/scala/TestSplittedSRAM.scala+19-7
- src/test/scala/TestWritebackQueue.scala+8-9
- src/test/scala/chi/TestTop.scala+43-10
- utility+1-1
Submodule rocket-chip updated 16 files
- src/main/scala/devices/debug/Debug.scala+3-4
- src/main/scala/devices/tilelink/CLINT.scala-1
- src/main/scala/devices/tilelink/Plic.scala-1
- src/main/scala/diplomacy/LazyModule.scala+2-5
- src/main/scala/rocket/BTB.scala+2-4
- src/main/scala/rocket/DCache.scala+1-3
- src/main/scala/rocket/Instructions.scala+30
- src/main/scala/rocket/Multiplier.scala+1-1
- src/main/scala/rocket/RVC.scala+7-4
- src/main/scala/subsystem/BaseSubsystem.scala+2-4
- src/main/scala/tile/FPU.scala+4-4
- src/main/scala/tile/RocketTile.scala-1
- src/main/scala/tilelink/RegisterRouter.scala-7
- src/main/scala/util/Annotations.scala-242
- src/main/scala/util/DescribedSRAM.scala-10
- src/main/scala/util/ElaborationArtefactAnnotation.scala-155
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