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Tang-HaojinTang-Haojin
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ChiselDB: dynamically append hartid for table name and site name
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3 files changed

+111
-38
lines changed

3 files changed

+111
-38
lines changed

‎src/main/scala/utility/ChiselDB.scala‎

Lines changed: 55 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@
1717
package utility
1818

1919
import chisel3._
20-
import chisel3.experimental.StringParam
20+
import chisel3.experimental.{IntParam, StringParam}
2121
import chisel3.util._
2222

2323
trait HasTableUtils {
@@ -79,45 +79,55 @@ trait HasTableUtils {
7979
}
8080
}
8181

82-
class Table[T <: Record](val envInFPGA: Boolean, val tableName: String, val hw: T) extends HasTableUtils {
82+
class Table[T <: Record](val envInFPGA: Boolean, val tableName: String, val hw: T, val tablePerHart: Boolean) extends HasTableUtils {
83+
84+
val hartIdNum = if (tablePerHart) HartIdHelper.getHartNum else 0
8385

8486
def genCpp: (String, String) = {
8587
val cols = get_columns(hw, "").map(_.field)
88+
val names = if (tablePerHart) (0 until hartIdNum).map(i => s"${tableName}_${i}") else IndexedSeq(tableName)
89+
def InitBody(name: String): String =
90+
s"""|const char *sql_${name} = "CREATE TABLE $name(" \\
91+
| "ID INTEGER PRIMARY KEY AUTOINCREMENT," \\
92+
| ${cols.map(c => "\"" + c.toUpperCase + " INT NOT NULL,\" \\").mkString("", "\n ", "")}
93+
| "STAMP INT NOT NULL," \\
94+
| "SITE TEXT);";
95+
| rc = sqlite3_exec(mem_db, sql_${name}, callback, 0, &zErrMsg);
96+
| if(rc != SQLITE_OK) {
97+
| printf("SQL error: %s\\n", zErrMsg);
98+
| exit(0);
99+
| } else {
100+
| printf("%s table created successfully!\\n", "$name");
101+
| }
102+
|""".stripMargin
86103
val init =
87104
s"""
88105
|void init_db_$tableName() {
89106
| // create table
90107
| if (!enable_dump_$tableName) return;
91108
|
92-
| const char *sql = "CREATE TABLE $tableName(" \\
93-
| "ID INTEGER PRIMARY KEY AUTOINCREMENT," \\
94-
| ${cols.map(c => "\"" + c.toUpperCase + " INT NOT NULL,\" \\").mkString("", "\n ", "")}
95-
| "STAMP INT NOT NULL," \\
96-
| "SITE TEXT);";
97-
| rc = sqlite3_exec(mem_db, sql, callback, 0, &zErrMsg);
98-
| if(rc != SQLITE_OK) {
99-
| printf("SQL error: %s\\n", zErrMsg);
100-
| exit(0);
101-
| } else {
102-
| printf("%s table created successfully!\\n", "$tableName");
103-
| }
109+
| ${names.map(InitBody).mkString("", " ", "")}
104110
|}
105111
|""".stripMargin
106112
val insert =
107113
s"""
108114
|extern "C" void ${tableName}_write(
109115
| ${cols.map(c => "uint64_t " + c).mkString("", ",\n ", ",")}
110116
| uint64_t stamp,
111-
| char *site
117+
| char *site,
118+
| uint64_t hartId,
119+
| bool site_need_id
112120
|) {
113121
| if(!dump || !enable_dump_$tableName) return;
114122
|
115-
| const char *format = "INSERT INTO $tableName(${cols.map(_.toUpperCase).mkString(",")}, STAMP, SITE) " \\
116-
| "VALUES(${cols.map(_ => "%ld").mkString(", ")}, %ld, '%s');";
123+
| const char *format = "INSERT INTO ${tableName}${if (tablePerHart) "_%ld" else ""}(${cols.map(_.toUpperCase).mkString(",")}, STAMP, SITE) " \\
124+
| "VALUES(${cols.map(_ => "%ld").mkString(", ")}, %ld, '%s%s');";
117125
| char *sql = (char *)malloc(${cols.size + 1} * sizeof(uint64_t) + (strlen(format)+strlen(site)) * sizeof(char));
126+
| char site_id[8];
127+
| sprintf(site_id, "_%ld", hartId);
118128
| sprintf(sql,
119-
| format,
120-
| ${cols.mkString(",")}, stamp, site
129+
| format,${if (tablePerHart) " hartId," else ""}
130+
| ${cols.mkString(",")}, stamp, site, site_need_id ? site_id : ""
121131
| );
122132
| rc = sqlite3_exec(mem_db, sql, callback, 0, &zErrMsg);
123133
| free(sql);
@@ -136,15 +146,16 @@ class Table[T <: Record](val envInFPGA: Boolean, val tableName: String, val hw:
136146
|extern "C" void ${tableName}_write(
137147
| ${cols.map(c => "uint64_t " + c).mkString("", ",\n ", ",")}
138148
| uint64_t stamp,
139-
| char *site
149+
| char *site,
150+
| uint64_t hartId
140151
|) {}
141152
|""".stripMargin
142153
if (envInFPGA) (init_dummy, insert_dummy) else (init, insert)
143154
}
144155

145-
def log(data: T, en: Bool, site: String = "", clock: Clock, reset: Reset): Unit = {
156+
def log(data: T, en: Bool, site: String = "", clock: Clock, reset: Reset, siteNeedId: Boolean = false): Unit = {
146157
if(!envInFPGA){
147-
val writer = Module(new TableWriteHelper[T](tableName, hw, site))
158+
val writer = Module(new TableWriteHelper[T](tableName, hw, site, tablePerHart, siteNeedId))
148159
val cnt = RegInit(0.U(64.W))
149160
cnt := cnt + 1.U
150161
writer.io.clock := clock
@@ -156,19 +167,28 @@ class Table[T <: Record](val envInFPGA: Boolean, val tableName: String, val hw:
156167
}
157168

158169
def log(data: Valid[T], site: String, clock: Clock, reset: Reset): Unit = {
159-
log(data.bits, data.valid, site, clock, reset)
170+
log(data, site, clock, reset, false)
171+
}
172+
173+
def log(data: Valid[T], site: String, clock: Clock, reset: Reset, siteNeedId: Boolean): Unit = {
174+
log(data.bits, data.valid, site, clock, reset, siteNeedId)
160175
}
161176

162177
def log(data: DecoupledIO[T], site: String, clock: Clock, reset: Reset): Unit = {
163-
log(data.bits, data.fire, site, clock, reset)
178+
log(data, site, clock, reset, false)
179+
}
180+
181+
def log(data: DecoupledIO[T], site: String, clock: Clock, reset: Reset, siteNeedId: Boolean): Unit = {
182+
log(data.bits, data.fire, site, clock, reset, siteNeedId)
164183
}
165184

166185
}
167186

168-
private class TableWriteHelper[T <: Record](tableName: String, hw: T, site: String)
187+
private class TableWriteHelper[T <: Record](tableName: String, hw: T, site: String, tablePerHart: Boolean, siteNeedId: Boolean)
169188
extends BlackBox(
170189
Map(
171-
"site" -> StringParam(site)
190+
"site" -> StringParam(site),
191+
"site_need_id" -> IntParam(if (siteNeedId) 1 else 0)
172192
)
173193
)
174194
with HasBlackBoxInline
@@ -195,7 +215,9 @@ private class TableWriteHelper[T <: Record](tableName: String, hw: T, site: Stri
195215
|(
196216
|${dpicInputs.map(x => "input longint " + x).mkString(" ", ",\n ", ",")}
197217
| input longint stamp,
198-
| input string site
218+
| input string site,
219+
| input longint hartId,
220+
| input bit site_need_id
199221
|);
200222
|
201223
|module $moduleName(
@@ -206,10 +228,13 @@ private class TableWriteHelper[T <: Record](tableName: String, hw: T, site: Stri
206228
| input [63:0] stamp
207229
|);
208230
| parameter string site;
231+
| parameter site_need_id;
232+
|
233+
| wire [63:0] hartId = ${if (tablePerHart || siteNeedId) "_hartIdDeclareModule.hartId" else "64'h0"};
209234
|
210235
| always@(posedge clock) begin
211236
| if(en && !reset) begin
212-
| $dpicFunc(${table.map(_.vExpr).mkString("", ", ", ", stamp, site")});
237+
| $dpicFunc(${table.map(_.vExpr).mkString("", ", ", ", stamp, site, hartId, site_need_id")});
213238
| end
214239
| end
215240
|endmodule
@@ -231,10 +256,10 @@ object ChiselDB {
231256
this.enable = enable
232257
}
233258

234-
def createTable[T <: Record](tableName: String, hw: T, basicDB: Boolean = this.enable): Table[T] = {
259+
def createTable[T <: Record](tableName: String, hw: T, basicDB: Boolean = this.enable, tablePerHart: Boolean = false): Table[T] = {
235260
getTable(tableName, hw)
236261
.getOrElse({
237-
val t = new Table[T](!basicDB, tableName, hw)
262+
val t = new Table[T](!basicDB, tableName, hw, tablePerHart)
238263
table_map += (tableName -> t)
239264
t
240265
})

‎src/main/scala/utility/HartIdHelper.scala‎

Lines changed: 48 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,48 @@
1+
/***************************************************************************************
2+
* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3+
* Copyright (c) 2020-2021 Peng Cheng Laboratory
4+
*
5+
* XiangShan is licensed under Mulan PSL v2.
6+
* You can use this software according to the terms and conditions of the Mulan PSL v2.
7+
* You may obtain a copy of Mulan PSL v2 at:
8+
* http://license.coscl.org.cn/MulanPSL2
9+
*
10+
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11+
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12+
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13+
*
14+
* See the Mulan PSL v2 for more details.
15+
***************************************************************************************/
16+
17+
package utility
18+
19+
import chisel3._
20+
import chisel3.util._
21+
22+
object HartIdHelper {
23+
private var hartIdNum = 1
24+
def setHartNum(num: Int): Unit = (hartIdNum = num)
25+
def getHartNum: Int = hartIdNum
26+
}
27+
28+
private class HartIdDeclare extends BlackBox with HasBlackBoxInline {
29+
val io = IO(new Bundle {
30+
val hartId = Input(UInt(64.W))
31+
})
32+
33+
val verilog =
34+
"""
35+
|module HartIdDeclare(
36+
| input [63:0] hartId
37+
|);
38+
|
39+
|endmodule
40+
|""".stripMargin
41+
setInline("HartIdDeclare.v", verilog)
42+
}
43+
44+
trait DeclareHartId {
45+
private val _hartIdDeclareModule = Module(new HartIdDeclare)
46+
val declaredHartId = Wire(UInt(64.W))
47+
_hartIdDeclareModule.io.hartId := declaredHartId
48+
}

‎src/main/scala/utility/TLUtils/TLLogger.scala‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -44,12 +44,12 @@ class TLLog extends Bundle with HasCLikeTypes {
4444
val echo = uint64_t
4545
}
4646

47-
class TLLogWriter(prefix: String) extends Module {
47+
class TLLogWriter(prefix: String, siteNeedId: Boolean) extends Module {
4848
val io = IO(Flipped(ValidIO(new TLLog)))
49-
TLLogger.table.log(io, prefix, this.clock, this.reset)
49+
TLLogger.table.log(io, prefix, this.clock, this.reset, siteNeedId)
5050
}
5151

52-
class TLLogger(name: String)(implicit p: Parameters) extends LazyModule {
52+
class TLLogger(name: String, val siteNeedId: Boolean)(implicit p: Parameters) extends LazyModule {
5353
val node = TLAdapterNode()
5454
lazy val module = new TLLoggerImp(this, name)
5555
}
@@ -58,7 +58,7 @@ class TLLoggerImp(outer: TLLogger, name: String) extends LazyModuleImp(outer) {
5858
val node = outer.node
5959
for (((in, edgeIn), (out, edgeOut)) <- node.in.zip(node.out)) {
6060
out <> in
61-
TLLogger.track(in, edgeIn, this.clock, this.reset)(name)
61+
TLLogger.track(in, edgeIn, this.clock, this.reset, outer.siteNeedId)(name)
6262
}
6363
}
6464

@@ -127,15 +127,15 @@ object TLLogger {
127127
log.data := d.data.asTypeOf(log.data)
128128
}
129129

130-
def track(in: TLBundle, edge: TLEdgeIn, clock: Clock, reset: Reset)(name: String) = {
130+
def track(in: TLBundle, edge: TLEdgeIn, clock: Clock, reset: Reset, siteNeedId: Boolean)(name: String) = {
131131
val numClients = edge.client.endSourceId
132132

133133
// Acquire/Get -> Grant
134134
val a_d_addrs = Reg(Vec(numClients, UInt(edge.bundle.addressBits.W)))
135135
// Release -> ReleaseAck
136136
val c_d_addrs = Reg(Vec(numClients, UInt(edge.bundle.addressBits.W)))
137137
val a_log, b_log, c_log, d_log = WireInit(0.U.asTypeOf(new TLLog))
138-
val a_writer, b_writer, c_writer, d_writer = Module(new TLLogWriter(name))
138+
val a_writer, b_writer, c_writer, d_writer = Module(new TLLogWriter(name, siteNeedId))
139139

140140
def connect(writer: TLLogWriter, log: TLLog, wen: Bool) = {
141141
writer.io.bits.channel := log.channel
@@ -178,9 +178,9 @@ object TLLogger {
178178

179179
}
180180

181-
def apply(name: String, enable: Boolean = true)(implicit p: Parameters) = {
181+
def apply(name: String, enable: Boolean = true, needHartId: Boolean = false)(implicit p: Parameters) = {
182182
if (enable) {
183-
val logger = LazyModule(new TLLogger(name))
183+
val logger = LazyModule(new TLLogger(name, needHartId))
184184
logger.node
185185
} else {
186186
TLTempNode()

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