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119 | 119 | dante_osc_mclk: dante-osc-mclk { |
120 | 120 | compatible = "fixed-clock"; |
121 | 121 | #clock-cells = <0>; |
122 | | - clock-frequency = <12288000>; |
| 122 | + clock-frequency = <24576000>; |
123 | 123 | clock-output-names = "dante_osc_mclk"; |
124 | 124 | }; |
125 | 125 |
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451 | 451 | pinctrl-names = "default"; |
452 | 452 | pinctrl-0 = <&pinctrl_sai3>; |
453 | 453 | clocks = <&clk IMX8MM_CLK_SAI3_IPG>, <&clk IMX8MM_CLK_DUMMY>, |
454 | | - <&dante_osc_sclk>, |
| 454 | + <&dante_osc_mclk>, |
455 | 455 | <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; |
456 | 456 | clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; |
457 | 457 | fsl,dataline = <1 0x00 0x01>; /*I2S mode enabled, 0 RX lines, 1 TX lines*/ |
458 | 458 | fsl,txs-rxs; |
| 459 | + fsl,sai-mclk-direction-output; |
459 | 460 | status = "okay"; |
460 | 461 | }; |
461 | 462 |
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462 | 463 | &sai1 { |
463 | 464 | pinctrl-names = "default"; |
464 | 465 | pinctrl-0 = <&pinctrl_sai1>; |
465 | 466 | clocks = <&clk IMX8MM_CLK_SAI1_IPG>, <&clk IMX8MM_CLK_DUMMY>, |
466 | | - <&dante_osc_sclk>, |
| 467 | + <&dante_osc_mclk>, |
467 | 468 | <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; |
468 | 469 | clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; |
469 | 470 | fsl,dataline = <1 0x0F 0x0F>; /*I2S mode enabled, 4 RX lines, 4 TX lines*/ |
470 | 471 | fsl,txs-rxs; |
| 472 | + fsl,sai-multi-lane; |
| 473 | + fsl,sai-mclk-direction-output; |
471 | 474 | status = "okay"; |
472 | 475 | }; |
473 | 476 |
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