continued work on saes

Author: theonlytruealex

capsules/extra/src/test/aes256.rs

@@ -207,6 +207,7 @@ impl<'a, A: AES<'a, AES256> + AESCBC> TestAES256Cbc<'a, A> {
 
         let (start, stop) = chunk_range(step);
         run_crypt(self.aes, in_place, &self.source, &self.data, start, stop);
+        debug!("ran");
     }
 }
 

chips/stm32u5xx/src/chip.rs

@@ -77,9 +77,10 @@ impl<'a> Stm32u5xxDefaultPeripherals<'a> {
         self.rcc.enable_gpioc();
         self.rcc.enable_usart1();
         self.rcc.enable_aes();
+        self.rcc.enable_trng();
+        self.trng.init();
         self.rcc.enable_saes();
         self.rcc.enable_syscfg();
-        self.rcc.enable_trng();
         self.rcc.set_usart1_source_pclk();
         // Link DMA to USART1
         let usart1_channel_tx = self.dma1.request_channel();
@@ -99,7 +100,6 @@ impl<'a> Stm32u5xxDefaultPeripherals<'a> {
         if let (Some(tx), Some(rx)) = (usart1_channel_tx, usart1_channel_rx) {
             usart::Usart::set_dma(self.usart1, self.dma1, tx, rx);
         }
-        self.trng.init();
     }
 }
 

chips/stm32u5xx/src/entropy.rs

@@ -138,7 +138,9 @@ impl<'a> Trng<'a> {
             .nscr
             .modify(NSCR::NSCFG.val(NOISE_SOURCE_CONTROL_CONFIG));
         self.registers.cr.modify(CR::CONFIGLOCK::SET);
-        self.registers.cr.modify(CR::CONDRST::CLEAR);
+        self.registers
+            .cr
+            .modify(CR::CONDRST::CLEAR + CR::RNGEN::SET);
         self.register();
     }
 
@@ -148,9 +150,7 @@ impl<'a> Trng<'a> {
             .client
             .map(|client| client.entropy_available(&mut TrngIter(self), Ok(())));
         match response {
-            Some(Continue::Done) | None => {
-                self.registers.cr.modify(CR::RNGEN::CLEAR);
-            }
+            Some(Continue::Done) | None => {}
             _ => {
                 self.entropy_needed.set(true);
                 self.deferred_call.set();
@@ -162,7 +162,6 @@ impl<'a> Trng<'a> {
 impl<'a> Entropy32<'a> for Trng<'a> {
     fn get(&self) -> Result<(), kernel::ErrorCode> {
         let regs = self.registers;
-        regs.cr.modify(CR::RNGEN::SET);
         if regs.sr.any_matching_bits_set(SR::CECS::SET + SR::SECS::SET) {
             return Err(kernel::ErrorCode::FAIL);
         }

chips/stm32u5xx/src/saes.rs

@@ -327,7 +327,7 @@ impl<'a, K: AESKeySize> Saes<'a, K> {
         buf[..slice.len()].copy_from_slice(slice);
 
         for chunk in buf.chunks_exact(4) {
-            let word = u32::from_le_bytes(chunk.try_into().unwrap());
+            let word = u32::from_be_bytes(chunk.try_into().unwrap());
             self.registers.dinr.set(word);
         }
     }
@@ -365,6 +365,9 @@ impl<'a, K: AESKeySize> Saes<'a, K> {
             self.registers.cr.modify(CR::EN::SET);
         }
         self.write_input(ctx);
+        debug!("wrote input");
+        debug!("CR: {:02x?}", self.registers.cr.get());
+        debug!("SR: {:02x?}", self.registers.sr.get());
     }
 
     fn start_key_wrapping(&self, ctx: CryptoContext, key_id: KeyID) {
@@ -441,6 +444,9 @@ impl<'a, K: AESKeySize> Saes<'a, K> {
     }
 
     pub fn handle_interrupt(&self) {
+        debug!("INTERRUPT");
+        debug!("CR: {:02x?}", self.registers.cr.get());
+        debug!("SR: {:02x?}", self.registers.sr.get());
         if self.registers.isr.is_set(ISR::CCF) {
             debug!("CCF");
             self.registers.icr.write(ICR::CCF::SET);
@@ -471,6 +477,7 @@ impl<'a, K: AESKeySize> kernel::hil::symmetric_encryption::AES<'a, K> for Saes<'
         self.registers.cr.modify(CR::DATATYPE::Byte);
         self.state.set(State::Idle);
         self.enable_interrupts();
+        debug!("ENABLE");
         debug!("CR: {:02x?}", self.registers.cr.get());
         debug!("SR: {:02x?}", self.registers.sr.get());
     }
@@ -487,6 +494,9 @@ impl<'a, K: AESKeySize> kernel::hil::symmetric_encryption::AES<'a, K> for Saes<'
     }
 
     fn set_key(&self, key: AESKey) -> Result<(), ErrorCode> {
+        debug!("KEY");
+        debug!("CR: {:02x?}", self.registers.cr.get());
+        debug!("SR: {:02x?}", self.registers.sr.get());
         if self.registers.cr.any_matching_bits_set(CR::EN::SET)
             || self.registers.sr.any_matching_bits_set(SR::BUSY::SET)
         {
@@ -532,6 +542,9 @@ impl<'a, K: AESKeySize> kernel::hil::symmetric_encryption::AES<'a, K> for Saes<'
     }
 
     fn set_iv(&self, iv: &[u8]) -> Result<(), ErrorCode> {
+        debug!("IV");
+        debug!("CR: {:02x?}", self.registers.cr.get());
+        debug!("SR: {:02x?}", self.registers.sr.get());
         if iv.len() != AES_IV_SIZE {
             return Err(ErrorCode::INVAL);
         }
@@ -565,6 +578,9 @@ impl<'a, K: AESKeySize> kernel::hil::symmetric_encryption::AES<'a, K> for Saes<'
         Option<&'static mut [u8]>,
         &'static mut [u8],
     )> {
+        debug!("CRYPT");
+        debug!("CR: {:02x?}", self.registers.cr.get());
+        debug!("SR: {:02x?}", self.registers.sr.get());
         let state = self.state.get();
 
         //  Hardware busy check