Merge pull request tock#4427 from tock/cortexm-mpu-address-per-arch

arch: Cortex-M: Set MPU address per arch

Author: ppannuto

arch/cortex-m/src/mpu.rs

@@ -129,9 +129,6 @@ register_bitfields![u32,
     ]
 ];
 
-const MPU_BASE_ADDRESS: StaticRef<MpuRegisters> =
-    unsafe { StaticRef::new(0xE000ED90 as *const MpuRegisters) };
-
 /// State related to the real physical MPU.
 ///
 /// There should only be one instantiation of this object as it represents
@@ -149,9 +146,9 @@ pub struct MPU<const NUM_REGIONS: usize, const MIN_REGION_SIZE: usize> {
 }
 
 impl<const NUM_REGIONS: usize, const MIN_REGION_SIZE: usize> MPU<NUM_REGIONS, MIN_REGION_SIZE> {
-    pub const unsafe fn new() -> Self {
+    pub const unsafe fn new(registers: StaticRef<MpuRegisters>) -> Self {
         Self {
-            registers: MPU_BASE_ADDRESS,
+            registers,
             config_count: Cell::new(NonZeroUsize::MIN),
             hardware_is_configured_for: OptionalCell::empty(),
         }

arch/cortex-m0p/src/lib.rs

@@ -9,7 +9,16 @@
 use core::fmt::Write;
 
 pub mod mpu {
+    use kernel::utilities::StaticRef;
+
     pub type MPU = cortexm::mpu::MPU<8, 256>;
+
+    const MPU_BASE_ADDRESS: StaticRef<cortexm::mpu::MpuRegisters> =
+        unsafe { StaticRef::new(0xE000ED90 as *const cortexm::mpu::MpuRegisters) };
+
+    pub unsafe fn new() -> MPU {
+        MPU::new(MPU_BASE_ADDRESS)
+    }
 }
 
 // Re-export the base generic cortex-m functions here as they are

arch/cortex-m3/src/lib.rs

@@ -9,7 +9,16 @@
 use core::fmt::Write;
 
 pub mod mpu {
+    use kernel::utilities::StaticRef;
+
     pub type MPU = cortexm::mpu::MPU<8, 32>;
+
+    const MPU_BASE_ADDRESS: StaticRef<cortexm::mpu::MpuRegisters> =
+        unsafe { StaticRef::new(0xE000ED90 as *const cortexm::mpu::MpuRegisters) };
+
+    pub unsafe fn new() -> MPU {
+        MPU::new(MPU_BASE_ADDRESS)
+    }
 }
 
 pub use cortexm::initialize_ram_jump_to_main;

arch/cortex-m4/src/lib.rs

@@ -9,7 +9,16 @@
 use core::fmt::Write;
 
 pub mod mpu {
+    use kernel::utilities::StaticRef;
+
     pub type MPU = cortexm::mpu::MPU<8, 32>;
+
+    const MPU_BASE_ADDRESS: StaticRef<cortexm::mpu::MpuRegisters> =
+        unsafe { StaticRef::new(0xE000ED90 as *const cortexm::mpu::MpuRegisters) };
+
+    pub unsafe fn new() -> MPU {
+        MPU::new(MPU_BASE_ADDRESS)
+    }
 }
 
 pub use cortexm::dwt;

arch/cortex-m4f/src/lib.rs

@@ -9,7 +9,16 @@
 use core::fmt::Write;
 
 pub mod mpu {
+    use kernel::utilities::StaticRef;
+
     pub type MPU = cortexm::mpu::MPU<8, 32>;
+
+    const MPU_BASE_ADDRESS: StaticRef<cortexm::mpu::MpuRegisters> =
+        unsafe { StaticRef::new(0xE000ED90 as *const cortexm::mpu::MpuRegisters) };
+
+    pub unsafe fn new() -> MPU {
+        MPU::new(MPU_BASE_ADDRESS)
+    }
 }
 
 pub use cortexm::dwt;

arch/cortex-m7/src/lib.rs

@@ -9,7 +9,16 @@
 use core::fmt::Write;
 
 pub mod mpu {
+    use kernel::utilities::StaticRef;
+
     pub type MPU = cortexm::mpu::MPU<16, 32>; // Cortex-M7 MPU has 16 regions
+
+    const MPU_BASE_ADDRESS: StaticRef<cortexm::mpu::MpuRegisters> =
+        unsafe { StaticRef::new(0xE000ED90 as *const cortexm::mpu::MpuRegisters) };
+
+    pub unsafe fn new() -> MPU {
+        MPU::new(MPU_BASE_ADDRESS)
+    }
 }
 
 pub use cortexm::initialize_ram_jump_to_main;

chips/apollo3/src/chip.rs

@@ -18,7 +18,7 @@ pub struct Apollo3<I: InterruptService + 'static> {
 impl<I: InterruptService + 'static> Apollo3<I> {
     pub unsafe fn new(interrupt_service: &'static I) -> Self {
         Self {
-            mpu: cortexm4f::mpu::MPU::new(),
+            mpu: cortexm4f::mpu::new(),
             userspace_kernel_boundary: cortexm4f::syscall::SysCall::new(),
             interrupt_service,
         }

chips/imxrt10xx/src/chip.rs

@@ -20,7 +20,7 @@ pub struct Imxrt10xx<I: InterruptService + 'static> {
 impl<I: InterruptService + 'static> Imxrt10xx<I> {
     pub unsafe fn new(interrupt_service: &'static I) -> Self {
         Imxrt10xx {
-            mpu: cortexm7::mpu::MPU::new(),
+            mpu: cortexm7::mpu::new(),
             userspace_kernel_boundary: cortexm7::syscall::SysCall::new(),
             interrupt_service,
         }

chips/msp432/src/chip.rs

@@ -97,7 +97,7 @@ impl kernel::platform::chip::InterruptService for Msp432DefaultPeripherals<'_> {
 impl<'a, I: InterruptService + 'a> Msp432<'a, I> {
     pub unsafe fn new(interrupt_service: &'a I) -> Self {
         Self {
-            mpu: cortexm4::mpu::MPU::new(),
+            mpu: cortexm4::mpu::new(),
             userspace_kernel_boundary: cortexm4::syscall::SysCall::new(),
             interrupt_service,
         }

chips/nrf52/src/chip.rs

@@ -15,7 +15,7 @@ pub struct NRF52<'a, I: InterruptService + 'a> {
 impl<'a, I: InterruptService + 'a> NRF52<'a, I> {
     pub unsafe fn new(interrupt_service: &'a I) -> Self {
         Self {
-            mpu: cortexm4f::mpu::MPU::new(),
+            mpu: cortexm4f::mpu::new(),
             userspace_kernel_boundary: cortexm4f::syscall::SysCall::new(),
             interrupt_service,
         }