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changed enum from chips/earlgrey/src back, updated documentation
1 parent 8341736 commit 8471eaa

3 files changed

Lines changed: 10 additions & 10 deletions

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chips/README.md

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -54,11 +54,11 @@ HIL Support
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| sensors::TemperatureDriver | | | | | | | | | | |||| | | | | | | | | | | | |
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| spi::SpiMaster || | | | | | | || |||| ||| |||||| | | |
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| spi::SpiSlave | | | | | | | | | | | | | | | || | | | | | | | | |
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| symmetric_encryption::AES128 | | | | || | | | | |||| | || | | | | | | | | |
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| symmetric_encryption::AES128CBC | | | | || | | | | |||| | || | | | | | | | | |
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| symmetric_encryption::AES128CCM | | | | | | | | | | |||| | | | | | | | | | | | |
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| symmetric_encryption::AES128Ctr | | | | || | | | | |||| | || | | | | | | | | |
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| symmetric_encryption::AES128ECB | | | | || | | | | |||| | || | | | | | | | |
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| symmetric_encryption::AES | | | | || | | | | |||| | || | | | | | | | | |
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| symmetric_encryption::AESCBC | | | | || | | | | |||| | || | | | | | | | | |
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| symmetric_encryption::AESCCM | | | | | | | | | | |||| | | | | | | | | | | | |
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| symmetric_encryption::AESCtr | | | | || | | | | |||| | || | | | | | | | | |
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| symmetric_encryption::AESECB | | | | || | | | | |||| | || | | | | | | | |
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| time::Alarm |||||||| | |||||||||||||| | ||
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| time::Counter || | | ||| | | ||||| | || |||||| | ||
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| time::Frequency | |||||||| || | | || | | | | | | | | | ||

chips/earlgrey/src/aes.rs

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -109,8 +109,8 @@ register_bitfields![u32,
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enum Mode {
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IDLE,
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AES128CTR,
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AESCBC,
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AESECB,
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AES128CBC,
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AES128ECB,
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}
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// https://docs.opentitan.org/hw/top_earlgrey/doc/
@@ -462,7 +462,7 @@ impl kernel::hil::symmetric_encryption::AESCtr for Aes<'_> {
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impl kernel::hil::symmetric_encryption::AESECB for Aes<'_> {
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fn set_mode_aesecb(&self, encrypting: bool) -> Result<(), ErrorCode> {
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self.wait_on_idle_ready()?;
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self.mode.set(Mode::AESECB);
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self.mode.set(Mode::AES128ECB);
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let mut ctrl = if encrypting {
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CTRL::OPERATION::Encrypting
@@ -485,7 +485,7 @@ impl kernel::hil::symmetric_encryption::AESECB for Aes<'_> {
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impl kernel::hil::symmetric_encryption::AESCBC for Aes<'_> {
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fn set_mode_aescbc(&self, encrypting: bool) -> Result<(), ErrorCode> {
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self.wait_on_idle_ready()?;
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self.mode.set(Mode::AESCBC);
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self.mode.set(Mode::AES128CBC);
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let mut ctrl = if encrypting {
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CTRL::OPERATION::Encrypting

kernel/src/hil/symmetric_encryption.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@
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use crate::ErrorCode;
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/// Implement this trait and use `set_client()` in order to receive callbacks from an `AES128`
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/// Implement this trait and use `set_client()` in order to receive callbacks from an `AES`
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/// instance.
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pub trait Client<'a> {
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fn crypt_done(&'a self, source: Option<&'static mut [u8]>, dest: &'static mut [u8]);

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