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Commit 25014a4

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add register pass
1 parent 14d4cd1 commit 25014a4

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2 files changed

+8
-2
lines changed

2 files changed

+8
-2
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Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,8 @@
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from .apply_transform_sequence import ApplyTransformSequence
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from .apply_transform_sequence import ApplyTransformSequence, register_pass
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from .transform_interpreter import TransformInterpreterPass
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__all__ = [
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"ApplyTransformSequence",
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"TransformInterpreterPass",
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"register_pass",
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]

pennylane/compiler/python_compiler/transforms/apply_transform_sequence.py

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,11 @@
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from .transform_interpreter import TransformInterpreterPass
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available_passes = {}
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def register_pass(name, _callable):
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available_passes[name] = _callable
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@dataclass(frozen=True)
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class ApplyTransformSequence(ModulePass):
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name = "apply-transform-sequence"
@@ -18,7 +23,7 @@ def apply(self, ctx: MLContext, module: builtin.ModuleOp) -> None:
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if isinstance(op, builtin.ModuleOp):
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nested_modules.append(op)
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pipeline = PipelinePass((TransformInterpreterPass(passes={}),))
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pipeline = PipelinePass((TransformInterpreterPass(passes=available_passes),))
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for op in nested_modules:
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pipeline.apply(ctx, op)
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