Enable a multi-IR pipeline for bicycle compilation

[Cryoris]

Summary

The planned FTQC demo for v2.5 is an end-to-end pipeline using Qiskit's StagedPassManager system for a compilation from a high-level FT input, via Qiskit's DAGCircuit, down to bicycle ISA with a compiler. Each of these stages use their own IRs. Qiskit's job is to produce the StagedPassManager framework, and the "middle layer" which compiles the circuits into PBC representation, suitable for the bicycle compiler to consume.

On the Qiskit side, this pipeline requires 2 main features:

• a StagedPassManager that can handle pass managers with different IRs
• a preset PBC pass manager, based on DAGCircuit, that produces PBC instructions

Tasks

• Generalize StagedPassManager to handle multiple IRs
• Preset PBC staged pass manager (PBC staged pass manager #15861)
• Integration testing (this will depend on the other IRs and might end up in a separate repo)

Optional

• Litinski transformation on PBC format (Extend litinski transformation for all Pauli rotations #15974)
• PBC-friendly synthesis functions for HLS
• Benchmarks for PBC pipeline itself