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‎3rd_party/CMSIS/Include/cachel1_armv7.h‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -48,7 +48,7 @@
4848

4949
#ifndef __SCB_ICACHE_LINE_SIZE
5050
#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
51-
#endif
51+
#endif
5252

5353
/**
5454
\brief Enable I-Cache
@@ -328,10 +328,10 @@ __STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
328328
__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize)
329329
{
330330
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
331-
if ( dsize > 0 ) {
331+
if ( dsize > 0 ) {
332332
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
333333
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
334-
334+
335335
__DSB();
336336

337337
do {
@@ -358,10 +358,10 @@ __STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsiz
358358
__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
359359
{
360360
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
361-
if ( dsize > 0 ) {
361+
if ( dsize > 0 ) {
362362
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
363363
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
364-
364+
365365
__DSB();
366366

367367
do {
@@ -388,10 +388,10 @@ __STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize
388388
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
389389
{
390390
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
391-
if ( dsize > 0 ) {
391+
if ( dsize > 0 ) {
392392
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
393393
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
394-
394+
395395
__DSB();
396396

397397
do {

‎3rd_party/CMSIS/Include/cmsis_armcc.h‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -63,9 +63,9 @@
6363
#ifndef __STATIC_INLINE
6464
#define __STATIC_INLINE static __inline
6565
#endif
66-
#ifndef __STATIC_FORCEINLINE
66+
#ifndef __STATIC_FORCEINLINE
6767
#define __STATIC_FORCEINLINE static __forceinline
68-
#endif
68+
#endif
6969
#ifndef __NO_RETURN
7070
#define __NO_RETURN __declspec(noreturn)
7171
#endif
@@ -461,7 +461,7 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
461461
*/
462462
#define __DMB() __dmb(0xF)
463463

464-
464+
465465
/**
466466
\brief Reverse byte order (32 bit)
467467
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.

‎3rd_party/CMSIS/Include/cmsis_armclang.h‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -597,7 +597,7 @@ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
597597
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
598598
Stack Pointer Limit register hence zero is returned always in non-secure
599599
mode.
600-
600+
601601
\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
602602
\return PSPLIM Register value
603603
*/
@@ -645,7 +645,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
645645
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
646646
Stack Pointer Limit register hence the write is silently ignored in non-secure
647647
mode.
648-
648+
649649
\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
650650
\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
651651
*/
@@ -1228,7 +1228,7 @@ __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
12281228
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
12291229
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
12301230
(defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
1231-
1231+
12321232
/**
12331233
\brief Load-Acquire (8 bit)
12341234
\details Executes a LDAB instruction for 8 bit value.

‎3rd_party/CMSIS/Include/cmsis_armclang_ltm.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -595,7 +595,7 @@ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
595595
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
596596
Stack Pointer Limit register hence zero is returned always in non-secure
597597
mode.
598-
598+
599599
\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
600600
\return PSPLIM Register value
601601
*/
@@ -641,7 +641,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
641641
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
642642
Stack Pointer Limit register hence the write is silently ignored in non-secure
643643
mode.
644-
644+
645645
\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
646646
\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
647647
*/

‎3rd_party/CMSIS/Include/cmsis_gcc.h‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -46,9 +46,9 @@
4646
#ifndef __STATIC_INLINE
4747
#define __STATIC_INLINE static inline
4848
#endif
49-
#ifndef __STATIC_FORCEINLINE
49+
#ifndef __STATIC_FORCEINLINE
5050
#define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
51-
#endif
51+
#endif
5252
#ifndef __NO_RETURN
5353
#define __NO_RETURN __attribute__((__noreturn__))
5454
#endif
@@ -126,23 +126,23 @@
126126
\details This default implementations initialized all data and additional bss
127127
sections relying on .copy.table and .zero.table specified properly
128128
in the used linker script.
129-
129+
130130
*/
131131
__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
132132
{
133133
extern void _start(void) __NO_RETURN;
134-
134+
135135
typedef struct {
136136
uint32_t const* src;
137137
uint32_t* dest;
138138
uint32_t wlen;
139139
} __copy_table_t;
140-
140+
141141
typedef struct {
142142
uint32_t* dest;
143143
uint32_t wlen;
144144
} __zero_table_t;
145-
145+
146146
extern const __copy_table_t __copy_table_start__;
147147
extern const __copy_table_t __copy_table_end__;
148148
extern const __zero_table_t __zero_table_start__;
@@ -153,16 +153,16 @@ __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
153153
pTable->dest[i] = pTable->src[i];
154154
}
155155
}
156-
156+
157157
for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) {
158158
for(uint32_t i=0u; i<pTable->wlen; ++i) {
159159
pTable->dest[i] = 0u;
160160
}
161161
}
162-
162+
163163
_start();
164164
}
165-
165+
166166
#define __PROGRAM_START __cmsis_start
167167
#endif
168168

@@ -652,7 +652,7 @@ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
652652
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
653653
Stack Pointer Limit register hence zero is returned always in non-secure
654654
mode.
655-
655+
656656
\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
657657
\return PSPLIM Register value
658658
*/
@@ -697,7 +697,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
697697
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
698698
Stack Pointer Limit register hence the write is silently ignored in non-secure
699699
mode.
700-
700+
701701
\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
702702
\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
703703
*/
@@ -834,7 +834,7 @@ __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
834834
{
835835
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
836836
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
837-
#if __has_builtin(__builtin_arm_get_fpscr)
837+
#if __has_builtin(__builtin_arm_get_fpscr)
838838
// Re-enable using built-in when GCC has been fixed
839839
// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
840840
/* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */

‎3rd_party/CMSIS/Include/cmsis_iccarm.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@
88
//------------------------------------------------------------------------------
99
//
1010
// Copyright (c) 2017-2019 IAR Systems
11-
// Copyright (c) 2017-2019 Arm Limited. All rights reserved.
11+
// Copyright (c) 2017-2019 Arm Limited. All rights reserved.
1212
//
1313
// SPDX-License-Identifier: Apache-2.0
1414
//

‎3rd_party/CMSIS/Include/core_armv81mml.h‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -210,14 +210,14 @@
210210
#define __FPU_PRESENT 0U
211211
#warning "__FPU_PRESENT not defined in device header file; using default!"
212212
#endif
213-
213+
214214
#if __FPU_PRESENT != 0U
215215
#ifndef __FPU_DP
216216
#define __FPU_DP 0U
217217
#warning "__FPU_DP not defined in device header file; using default!"
218218
#endif
219219
#endif
220-
220+
221221
#ifndef __MPU_PRESENT
222222
#define __MPU_PRESENT 0U
223223
#warning "__MPU_PRESENT not defined in device header file; using default!"
@@ -232,7 +232,7 @@
232232
#define __DCACHE_PRESENT 0U
233233
#warning "__DCACHE_PRESENT not defined in device header file; using default!"
234234
#endif
235-
235+
236236
#ifndef __PMU_PRESENT
237237
#define __PMU_PRESENT 0U
238238
#warning "__PMU_PRESENT not defined in device header file; using default!"
@@ -261,7 +261,7 @@
261261
#define __VTOR_PRESENT 1U
262262
#warning "__VTOR_PRESENT not defined in device header file; using default!"
263263
#endif
264-
264+
265265
#ifndef __NVIC_PRIO_BITS
266266
#define __NVIC_PRIO_BITS 3U
267267
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"

‎3rd_party/CMSIS/Include/core_armv8mbl.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2043,7 +2043,7 @@ __STATIC_INLINE void TZ_SAU_Disable(void)
20432043
@{
20442044
*/
20452045

2046-
2046+
20472047
/**
20482048
\brief Set Debug Authentication Control Register
20492049
\details writes to Debug Authentication Control register.
@@ -2110,7 +2110,7 @@ __STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
21102110
@{
21112111
*/
21122112

2113-
2113+
21142114
/**
21152115
\brief Get Debug Authentication Status Register
21162116
\details Reads Debug Authentication Status register.

‎3rd_party/CMSIS/Include/core_armv8mml.h‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -254,7 +254,7 @@
254254
#define __VTOR_PRESENT 1U
255255
#warning "__VTOR_PRESENT not defined in device header file; using default!"
256256
#endif
257-
257+
258258
#ifndef __NVIC_PRIO_BITS
259259
#define __NVIC_PRIO_BITS 3U
260260
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
@@ -2939,7 +2939,7 @@ __STATIC_INLINE void TZ_SAU_Disable(void)
29392939
@{
29402940
*/
29412941

2942-
2942+
29432943
/**
29442944
\brief Set Debug Authentication Control Register
29452945
\details writes to Debug Authentication Control register.
@@ -3006,7 +3006,7 @@ __STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
30063006
@{
30073007
*/
30083008

3009-
3009+
30103010
/**
30113011
\brief Get Debug Authentication Status Register
30123012
\details Reads Debug Authentication Status register.

‎3rd_party/CMSIS/Include/core_cm0.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -61,7 +61,7 @@
6161
*/
6262

6363
#include "cmsis_version.h"
64-
64+
6565
/* CMSIS CM0 definitions */
6666
#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
6767
#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */

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