Changed structure to add a new interface and make programmer facing code easier

Author: DannyCato

CMakeLists.txt

@@ -24,7 +24,8 @@ project(EVT
     LANGUAGES CXX C ASM
 )
 
-add_library(${PROJECT_NAME} STATIC)
+add_library(${PROJECT_NAME} STATIC
+        include/core/io/types/SDRAM_Device.hpp)
 
 # Add sources
 target_sources(${PROJECT_NAME} PRIVATE

include/core/io/SDRAM.hpp

@@ -6,7 +6,7 @@
     #include <HALf4/stm32f4xx_hal.h>
 
 namespace core::io {
-
+    class SDRAMDevice;
 /**
  * Interface for configuring and accessing external SDRAM.
  * Provides clock frequency functions
@@ -104,9 +104,10 @@ class SDRAM {
      * @param pins the pins for use by the SDRAM Controller
      * @param initConfig HAL-level SDRAM parameters for how initialization works
      * @param timingConfig HAL-level SDRAM parameters for properly orchestrating hardware timing
+     * @param device interface class with abstract function that is overridden with a specific implementation
      */
     SDRAM(uint32_t* memoryAddress, SDRAMPinGroup& pins, const SDRAMInitConfig& initConfig,
-          const SDRAMTimingConfig& timingConfig);
+          const SDRAMTimingConfig& timingConfig, const SDRAMDevice& device);
 
     /**
      * Gets the Frequency of the SDRAM CLK
@@ -195,12 +196,19 @@ class SDRAM {
     SDRAMPinGroup& pins;
     SDRAMInitConfig initConfig;
     SDRAMTimingConfig timingConfig;
+    const SDRAMDevice& device;
 
     static constexpr Status HALStatusToSDRAMStatus(uint32_t hal_status) {
         return static_cast<Status>(hal_status);
     }
 };
 
+class SDRAMDevice {
+public:
+    virtual ~SDRAMDevice()                      = default;
+    virtual SDRAM::Status sendStartUpCommands(SDRAM& controller) = 0;
+};
+
 } // namespace core::io
 
 #endif

include/core/io/platform/f4xx/SDRAMf4xx.hpp

@@ -24,8 +24,8 @@ namespace core::io {
  */
 class SDRAMf4xx : public SDRAM {
 public:
-#define SDRAM_BANK1 0xC0000000
-#define SDRAM_BANK2 0xD0000000
+      static constexpr auto SDRAM_BANK1 = 0xC0000000;
+      static constexpr auto SDRAM_BANK2 = 0xD0000000;
 
     /**
      * Initializes an FMC device by enabling the specific peripheral clock,
@@ -34,9 +34,11 @@ class SDRAMf4xx : public SDRAM {
      * @param[in] pins a struct containing an array of pins and their length for use by the SDRAM Controller.
      * @param[in] sdramInitConfig SDRAM controller configuration parameters.
      * @param[in] sdramTimingConfig SDRAM timing configuration parameters.
+     * @param[in] device interface class with abstract function that is overridden with a specific implementation
      *
      */
-    SDRAMf4xx(SDRAMPinGroup& pins, const SDRAMInitConfig& sdramInitConfig, const SDRAMTimingConfig& sdramTimingConfig);
+    SDRAMf4xx(SDRAMPinGroup& pins, const SDRAMInitConfig& sdramInitConfig, const SDRAMTimingConfig& sdramTimingConfig,
+      SDRAMDevice& device);
 
     /**
      * Enable write protection for the sdram

include/core/manager.hpp

@@ -338,9 +338,10 @@ SPI& getSPI(GPIO* CSPins[], uint8_t pinLength) {
  */
 #ifdef SDRAM_SUPPORTED
 template<SDRAM::SDRAMPinGroup& pins>
-SDRAM& getSDRAM(const SDRAM::SDRAMInitConfig& initConfig, const SDRAM::SDRAMTimingConfig& timingConfig) {
+SDRAM& getSDRAM(const SDRAM::SDRAMInitConfig& initConfig, const SDRAM::SDRAMTimingConfig& timingConfig,
+    SDRAMDevice& device) {
     #ifdef STM32F4xx
-    static SDRAMf4xx fmc(pins, initConfig, timingConfig);
+    static SDRAMf4xx fmc(pins, initConfig, timingConfig, device);
     return fmc;
     #endif
 }

src/core/io/SDRAM.cpp

@@ -3,8 +3,8 @@
 namespace core::io {
 
 SDRAM::SDRAM(uint32_t* memoryAddress, SDRAMPinGroup& pins, const SDRAMInitConfig& initConfig,
-             const SDRAMTimingConfig& timingConfig)
-    : memoryAddress(memoryAddress), pins(pins), initConfig(initConfig), timingConfig(timingConfig) {}
+             const SDRAMTimingConfig& timingConfig, const SDRAMDevice& device)
+    : memoryAddress(memoryAddress), pins(pins), initConfig(initConfig), timingConfig(timingConfig), device(device) {}
 
 uint32_t SDRAM::getSdramClockFrequency() {
     return HAL_RCC_GetSysClockFreq() / 2;

src/core/io/platform/f4xx/SDRAMf4xx.cpp

@@ -5,10 +5,10 @@
 namespace core::io {
 
 SDRAMf4xx::SDRAMf4xx(SDRAMPinGroup& pins, const SDRAMInitConfig& sdramInitConfig,
-                     const SDRAMTimingConfig& sdramTimingConfig)
+                     const SDRAMTimingConfig& sdramTimingConfig, SDRAMDevice& device)
     : SDRAM((sdramInitConfig.sdBank == FMC_SDRAM_BANK1) ? reinterpret_cast<uint32_t*>(SDRAM_BANK1)
                                                         : reinterpret_cast<uint32_t*>(SDRAM_BANK2),
-            pins, sdramInitConfig, sdramTimingConfig),
+            pins, sdramInitConfig, sdramTimingConfig, device),
       sdramDevice(FMC_SDRAM_DEVICE), sdram(), sdramTiming() {
 
     // map the class init structs to the hal structs
@@ -33,8 +33,8 @@ SDRAMf4xx::SDRAMf4xx(SDRAMPinGroup& pins, const SDRAMInitConfig& sdramInitConfig
     sdramTiming.RCDDelay             = sdramTimingConfig.rcdDelay;
 
     InitHardware(pins);
-    HAL_StatusTypeDef status = HAL_SDRAM_Init(&sdram, &sdramTiming);
-    log::LOGGER.log(log::Logger::LogLevel::DEBUG, "%d status \r\n", status);
+    HAL_SDRAM_Init(&sdram, &sdramTiming);
+    device.sendStartUpCommands(*this);
 }
 
 SDRAM::Status SDRAMf4xx::EnableWriteProtection() {