Merge branch 'feature/ChongOscar/fmc-support' of https://github.com/RIT-EVT/EVT-core into feature/ChongOscar/fmc-support

Author: DannyCato

include/core/io/SDRAM.hpp

@@ -68,16 +68,16 @@ class SDRAM {
      * Must be initialized before passing into the constructor
      */
     struct SDRAMInitConfig {
-        uint32_t sdBank; // Bank number for the controller (0 or 1 usually)
-        uint32_t columnBitsNumber; // number of Horizontal Addressing Cells
-        uint32_t rowBitsNumber; // number of Vertical Addressing Cells
-        uint32_t memoryDataWidth; // How large the data is: 8, 16, or 32 bit
+        uint32_t sdBank;             // Bank number for the controller (0 or 1 usually)
+        uint32_t columnBitsNumber;   // number of Horizontal Addressing Cells
+        uint32_t rowBitsNumber;      // number of Vertical Addressing Cells
+        uint32_t memoryDataWidth;    // How large the data is: 8, 16, or 32 bit
         uint32_t internalBankNumber; // How many layers of columns and rows there are. Usually 1, 2, or 4
         uint32_t casLatency; // How many SDRAM CLK Cycles from data fetch received to data available from the output
         uint32_t writeProtection; // If you want bank protection on at initialization
-        uint32_t sdClockPeriod; // How many MCU controller clock cycles per SDRAM CLK Cycle. Usually 1, 2, or 3
-        uint32_t readBurst; // How many bytes to expect per read request.
-        uint32_t readPipeDelay; // Number of SDRAM CLK Cycles until data is available from read. Usually 1
+        uint32_t sdClockPeriod;   // How many MCU controller clock cycles per SDRAM CLK Cycle. Usually 1, 2, or 3
+        uint32_t readBurst;       // How many bytes to expect per read request.
+        uint32_t readPipeDelay;   // Number of SDRAM CLK Cycles until data is available from read. Usually 1
     };
 
     /**
@@ -86,13 +86,13 @@ class SDRAM {
      * Must be initialized before passing into the constructor
      */
     struct SDRAMTimingConfig {
-        uint32_t loadToActiveDelay; // Time to update the load/operation register to SDRAM being read for commands
+        uint32_t loadToActiveDelay;    // Time to update the load/operation register to SDRAM being read for commands
         uint32_t exitSelfRefreshDelay; // How long to exit the self-refresh mode
-        uint32_t selfRefreshTime; // SDRAM CLK Cycles a row will be unavailable for while refreshing
-        uint32_t rowCycleDelay; // Number of SDRAM CLK Cycles until a new active command can be submitted to a bank
+        uint32_t selfRefreshTime;      // SDRAM CLK Cycles a row will be unavailable for while refreshing
+        uint32_t rowCycleDelay;     // Number of SDRAM CLK Cycles until a new active command can be submitted to a bank
         uint32_t writeRecoveryTime; // SDRAM CLK Cycles from write until a precharge can be given
         uint32_t readToPrechargeDelay; // SDRAM CLK Cycles from read until a precharge
-        uint32_t rcdDelay; // SDRAM CLK Cycles from an active to read/write
+        uint32_t rcdDelay;             // SDRAM CLK Cycles from an active to read/write
     };
 
     struct SDRAMPinGroup {

src/core/io/SDRAM.cpp

@@ -3,52 +3,50 @@
 
 namespace core::io {
 
-
-    SDRAM::SDRAM(uint32_t* memoryAddress, SDRAMPinGroup& pins, const SDRAMInitConfig& initConfig,
-                 const SDRAMTimingConfig& timingConfig, const SDRAMDevice& device)
-        : memoryAddress(memoryAddress), pins(pins), initConfig(initConfig), timingConfig(timingConfig), device(device) {}
-
-    uint32_t SDRAM::getSdramClockFrequency(uint8_t mcuClkPerSdramClk) {
-        return HAL_RCC_GetSysClockFreq() / mcuClkPerSdramClk;
-    }
-
-    uint8_t SDRAM::getMCUClkPerSdramClk(uint32_t sdClockPeriod) {
-        switch (sdClockPeriod) {
-            default:
-            case FMC_SDRAM_CLOCK_PERIOD_2:
-                return 2;
-                break;
-            case FMC_SDRAM_CLOCK_PERIOD_3:
-                return 3;
-                break;
-        }
-
-    }
-
-    uint32_t SDRAM::getSdramClockPeriodFS(uint32_t mcuClkPerSdramClk) {
-        return 1000000000UL / (getSdramClockFrequency(mcuClkPerSdramClk) / 1000000);
-
-        /**
-        1,000,000,000 / (getSdramClockFrequency(mcuClkPerSdramClk) / 1000000)
-        1,000,000,000 / ((HAL_RCC_GetSysClockFreq() / mcuClkPerSdramClk) / 1000000
-        Assume HAL_RCC_GetSysClockFreq() returns 100,000,000 Hz and mcuClkPerSdramClk = 2
-        1,000,000,000 / ((100,000,000Hz / 2) / 1000000)
-        1,000,000,000 / (50,000,000Hz / 1000000)
-        1,000,000,000 / 50Hz   (1 / Hz = s)
-        20,000,000 fs
-
-        Why put 1 billion as the numerator? It is the largest base 10 number that would fit in a
-        32-bit number. This gives maximum resolution for the following
-        function that uses it and keeps the calculation clean.
-
-        Why divide getSdramClockFrequency(...) by 1 million? This gives us how many megahertz
-        the clock is running at, which is the most imporant part of the clock speed in our case.
-        This makes the denominator of the outer division as small as possible, allowing us to get a high
-        amount of accuracy for femtoseconds per SDRAM clock period
-        */
+SDRAM::SDRAM(uint32_t* memoryAddress, SDRAMPinGroup& pins, const SDRAMInitConfig& initConfig,
+             const SDRAMTimingConfig& timingConfig, const SDRAMDevice& device)
+    : memoryAddress(memoryAddress), pins(pins), initConfig(initConfig), timingConfig(timingConfig), device(device) {}
+
+uint32_t SDRAM::getSdramClockFrequency(uint8_t mcuClkPerSdramClk) {
+    return HAL_RCC_GetSysClockFreq() / mcuClkPerSdramClk;
+}
+
+uint8_t SDRAM::getMCUClkPerSdramClk(uint32_t sdClockPeriod) {
+    switch (sdClockPeriod) {
+    default:
+    case FMC_SDRAM_CLOCK_PERIOD_2:
+        return 2;
+        break;
+    case FMC_SDRAM_CLOCK_PERIOD_3:
+        return 3;
+        break;
     }
-
-    uint32_t SDRAM::NSToSdramClockCycles(uint32_t nanoseconds, uint8_t mcuClkPerSdramClk) {
-        return (nanoseconds * 1000000) / (getSdramClockPeriodFS(mcuClkPerSdramClk) + 1);
-    } // Multiplied by 1,000,000 to get from nanoseconds to femtoseconds
+}
+
+uint32_t SDRAM::getSdramClockPeriodFS(uint32_t mcuClkPerSdramClk) {
+    return 1000000000UL / (getSdramClockFrequency(mcuClkPerSdramClk) / 1000000);
+
+    /**
+    1,000,000,000 / (getSdramClockFrequency(mcuClkPerSdramClk) / 1000000)
+    1,000,000,000 / ((HAL_RCC_GetSysClockFreq() / mcuClkPerSdramClk) / 1000000
+    Assume HAL_RCC_GetSysClockFreq() returns 100,000,000 Hz and mcuClkPerSdramClk = 2
+    1,000,000,000 / ((100,000,000Hz / 2) / 1000000)
+    1,000,000,000 / (50,000,000Hz / 1000000)
+    1,000,000,000 / 50Hz   (1 / Hz = s)
+    20,000,000 fs
+
+    Why put 1 billion as the numerator? It is the largest base 10 number that would fit in a
+    32-bit number. This gives maximum resolution for the following
+    function that uses it and keeps the calculation clean.
+
+    Why divide getSdramClockFrequency(...) by 1 million? This gives us how many megahertz
+    the clock is running at, which is the most imporant part of the clock speed in our case.
+    This makes the denominator of the outer division as small as possible, allowing us to get a high
+    amount of accuracy for femtoseconds per SDRAM clock period
+    */
+}
+
+uint32_t SDRAM::NSToSdramClockCycles(uint32_t nanoseconds, uint8_t mcuClkPerSdramClk) {
+    return (nanoseconds * 1000000) / (getSdramClockPeriodFS(mcuClkPerSdramClk) + 1);
+} // Multiplied by 1,000,000 to get from nanoseconds to femtoseconds
 } // namespace core::io

src/core/io/platform/f4xx/SDRAMf4xx.cpp

@@ -64,9 +64,10 @@ SDRAM::Status SDRAMf4xx::SendCommand(SDRAMCommand type, SDRAMCommandTarget targe
 }
 
 SDRAM::Status SDRAMf4xx::ProgramRefreshRate(uint32_t rowCount, uint32_t refreshTime) {
-    uint8_t clockPeriodNumber = getMCUClkPerSdramClk(sdram.Init.SDClockPeriod);
+    uint8_t clockPeriodNumber   = getMCUClkPerSdramClk(sdram.Init.SDClockPeriod);
     HAL_StatusTypeDef halStatus = FMC_SDRAM_ProgramRefreshRate(
-        this->sdramDevice, (((refreshTime * 1000) / rowCount) * (getSdramClockFrequency(clockPeriodNumber) / 1000000)) - 20);
+        this->sdramDevice,
+        (((refreshTime * 1000) / rowCount) * (getSdramClockFrequency(clockPeriodNumber) / 1000000)) - 20);
 
     return SDRAM::HALStatusToSDRAMStatus(halStatus);
 }