replaced private vars with structs stored in class

Author: oc6723

include/core/io/FMC.hpp

@@ -1,19 +1,17 @@
 #ifndef EVT_FMC_HPP
 #define EVT_FMC_HPP
 
-#ifdef __cplusplus
-
-extern "C" {
-    #endif
-
+#ifdef STM32F4xx
     #include "HALf4/stm32f4xx_hal.h"
     #include "HALf4/stm32f4xx_ll_fmc.h"
     #include "HALf4/stm32f4xx_hal_sdram.h"
-
-    #ifdef __cplusplus
-}
+#else
+    #include "HALf3/stm32f3xx_hal.h"
+    #include "HALf3/stm32f3xx_ll_fmc.h"
+    #include "HALf3/stm32f3xx_hal_sdram.h"
 #endif
 
+
 #define SDRAM_TIMEOUT (0x0000FFFFUL)
 
 typedef struct {
@@ -79,7 +77,7 @@ typedef FMC_GPIO 	FMC_CMD;
 // #define FMC_ 		((GPIO) {GPIO_PIN_x, GPIOx})
 
 #define SDRAM_CLK_SPEED ((uint32_t)(HAL_RCC_GetSysClockFreq() / 2))
-#define SDRAM_CLK_PERIOD_US (1000000000UL / (SDRAM_CLK_SPEED / 1000)) // LOSES SOME RESOLUTION, BUT ITS NEEDED TO FIT WITHIN 32-BITS
+#define SDRAM_CLK_PERIOD_US (1000000000UL / (SDRAM_CLK_SPEED / 1000)) // LOSES SOME RESOLUTION, BUT IT'S NEEDED TO FIT WITHIN 32-BITS
 #define NS_TO_SDRAM_CLK_CYCLES(NS) ((NS * 1000 + SDRAM_CLK_PERIOD_US) / (SDRAM_CLK_PERIOD_US))
 
 // All of these can be found in the datasheet of the Ram chip
@@ -179,15 +177,15 @@ class FMC {
      * Structure to hold an array of GPIO byte enable pins for the FMC
      */
     struct FMCByteEnablePins {
-        FMC_BE* pins;
+        FMC_BE *pins;
         uint8_t count;
     };
 
     /**
      * Structure to hold an array of GPIO bank pins for the FMC
      */
     struct FMCBankPins {
-        FMC_BANK* pins;
+        FMC_BANK *pins;
         uint8_t count;
     };
 
@@ -224,7 +222,7 @@ class FMC {
      *
      * @param[in] offset Byte offset from the SDRAM base address
      */
-    uint32_t read32(uint32_t offset) const;
+    [[nodiscard]] uint32_t read32(uint32_t offset) const;
 
 private:
     /**
@@ -242,32 +240,13 @@ class FMC {
      */
     void InitPinGroup(const FMC_GPIO* pins, uint8_t count);
 
-
-
-    FMC_SDRAM_TypeDef sdramDevice;
-    uint32_t sdBank;
-    uint32_t columnBitsNumber;
-    uint32_t rowBitsNumber;
-    uint32_t memoryDataWidth;
-    uint32_t internalBankNumber;
-    uint32_t casLatency;
-    uint32_t writeProtection;
-    uint32_t sdClockPeriod;
-    uint32_t readBurst;
-    uint32_t readPipeDelay;
-
-    uint32_t loadToActiveDelay;
-    uint32_t exitSelfRefreshDelay;
-    uint32_t selfRefreshTime;
-    uint32_t rowCycleDelay;
-    uint32_t writeRecoveryTime;
-    uint32_t rpDelay;
-    uint32_t rcdDelay;
+    SdramInitConfig sdramInitConfig;
+    SdramTimingConfig sdramTimingConfig;
 
     SDRAM_HandleTypeDef sdram;
     FMC_SDRAM_TimingTypeDef sdramTiming;
 
-    uint32_t baseAddress; //address to read and write to
+    uint32_t sdramMemoryAddress; //address to read and write to
 };
 
 }

src/core/io/FMC.cpp

@@ -2,81 +2,64 @@
 
 namespace core::io {
 
-FMC::FMC(const FMCPinConfig& pin_config, const SdramInitConfig& sdramInitConfig, const SdramTimingConfig& sdramTimingConfig) :
-sdramDevice(*sdramInitConfig.sdramDevice),
-sdBank(sdramInitConfig.sdBank),
-columnBitsNumber(sdramInitConfig.columnBitsNumber),
-rowBitsNumber(sdramInitConfig.rowBitsNumber),
-memoryDataWidth(sdramInitConfig.memoryDataWidth),
-internalBankNumber(sdramInitConfig.internalBankNumber),
-casLatency(sdramInitConfig.casLatency),
-writeProtection(sdramInitConfig.writeProtection),
-sdClockPeriod(sdramInitConfig.sdClockPeriod),
-readBurst(sdramInitConfig.readBurst),
-readPipeDelay(sdramInitConfig.readPipeDelay),
-loadToActiveDelay(sdramTimingConfig.loadToActiveDelay),
-exitSelfRefreshDelay(sdramTimingConfig.exitSelfRefreshDelay),
-selfRefreshTime(sdramTimingConfig.selfRefreshTime),
-rowCycleDelay(sdramTimingConfig.rowCycleDelay),
-writeRecoveryTime(sdramTimingConfig.writeRecoveryTime),
-rpDelay(sdramTimingConfig.rpDelay),
-rcdDelay(sdramTimingConfig.rcdDelay) {
-    InitHardware(pin_config);
-
-    sdram = {0};
-    sdramTiming = {0};
+FMC::FMC(const FMCPinConfig& pinConfig, const SdramInitConfig& sdramInitConfig, const SdramTimingConfig& sdramTimingConfig) :
+sdramInitConfig(sdramInitConfig),
+sdramTimingConfig(sdramTimingConfig),
+sdram({nullptr}),
+sdramTiming({0}) {
+    InitHardware(pinConfig);
 
     // map the class init structs to the hal structs
     sdram.Instance = sdramInitConfig.sdramDevice;
     sdram.Init.SDBank = sdramInitConfig.sdBank;
-    sdram.Init.ColumnBitsNumber = columnBitsNumber;
-    sdram.Init.RowBitsNumber = rowBitsNumber;
-    sdram.Init.MemoryDataWidth = memoryDataWidth;
-    sdram.Init.InternalBankNumber = internalBankNumber;
-    sdram.Init.WriteProtection = writeProtection;
-    sdram.Init.ReadBurst = readBurst;
-    sdram.Init.ReadPipeDelay = readPipeDelay;
-
-    sdramTiming.LoadToActiveDelay = loadToActiveDelay;
-    sdramTiming.ExitSelfRefreshDelay = exitSelfRefreshDelay;
-    sdramTiming.SelfRefreshTime = selfRefreshTime;
-    sdramTiming.RowCycleDelay = rowCycleDelay;
-    sdramTiming.WriteRecoveryTime = writeRecoveryTime;
-    sdramTiming.RPDelay = rpDelay;
-    sdramTiming.RCDDelay = rcdDelay;
+    sdram.Init.ColumnBitsNumber = sdramInitConfig.columnBitsNumber;
+    sdram.Init.RowBitsNumber = sdramInitConfig.rowBitsNumber;
+    sdram.Init.MemoryDataWidth = sdramInitConfig.memoryDataWidth;
+    sdram.Init.InternalBankNumber = sdramInitConfig.internalBankNumber;
+    sdram.Init.WriteProtection = sdramInitConfig.writeProtection;
+    sdram.Init.ReadBurst = sdramInitConfig.readBurst;
+    sdram.Init.ReadPipeDelay = sdramInitConfig.readPipeDelay;
+
+    sdramTiming.LoadToActiveDelay = sdramTimingConfig.loadToActiveDelay;
+    sdramTiming.ExitSelfRefreshDelay = sdramTimingConfig.exitSelfRefreshDelay;
+    sdramTiming.SelfRefreshTime = sdramTimingConfig.selfRefreshTime;
+    sdramTiming.RowCycleDelay = sdramTimingConfig.rowCycleDelay;
+    sdramTiming.WriteRecoveryTime = sdramTimingConfig.writeRecoveryTime;
+    sdramTiming.RPDelay = sdramTimingConfig.rpDelay;
+    sdramTiming.RCDDelay = sdramTimingConfig.rcdDelay;
 
     HAL_SDRAM_Init(&sdram, &sdramTiming);
 
-    if (sdBank == FMC_SDRAM_BANK1)
-        baseAddress = 0xC0000000;
+    if (sdramInitConfig.sdBank == FMC_SDRAM_BANK1) //determine read write memory address
+        sdramMemoryAddress = 0xC0000000;
     else
-        baseAddress = 0xD0000000;
+        sdramMemoryAddress = 0xD0000000;
 }
 
 void FMC::write32(uint32_t offset, uint32_t value) const
 {
-    volatile uint32_t* ptr =
-        reinterpret_cast<volatile uint32_t*>(baseAddress + offset);
+    volatile auto* ptr =
+        reinterpret_cast<volatile uint32_t*>(sdramMemoryAddress + offset);
 
     *ptr = value;
 }
 
 uint32_t FMC::read32(uint32_t offset) const
 {
-    volatile uint32_t* ptr =
-        reinterpret_cast<volatile uint32_t*>(baseAddress + offset);
+    volatile auto* ptr =
+        reinterpret_cast<volatile uint32_t*>(sdramMemoryAddress + offset);
 
     return *ptr;
 }
 
-void FMC::InitHardware(const FMCPinConfig& pin_config) {
+void FMC::InitHardware(const FMCPinConfig& pinConfig) {
     __HAL_RCC_FMC_CLK_ENABLE();
 
-    InitPinGroup(pin_config.address.pins, pin_config.address.count);
-    InitPinGroup(pin_config.data.pins, pin_config.data.count);
-    InitPinGroup(pin_config.byteEnable.pins, pin_config.byteEnable.count);
-    InitPinGroup(pin_config.bank.pins, pin_config.bank.count);
-    InitPinGroup(pin_config.command.pins, pin_config.command.count);
+    InitPinGroup(pinConfig.address.pins, pinConfig.address.count);
+    InitPinGroup(pinConfig.data.pins, pinConfig.data.count);
+    InitPinGroup(pinConfig.byteEnable.pins, pinConfig.byteEnable.count);
+    InitPinGroup(pinConfig.bank.pins, pinConfig.bank.count);
+    InitPinGroup(pinConfig.command.pins, pinConfig.command.count);
 }
 
 void FMC::InitPinGroup(const FMC_GPIO* pins, uint8_t count) {