created generic FMC interface

Author: oc6723

CMakeLists.txt

@@ -44,7 +44,8 @@ target_sources(${PROJECT_NAME} PRIVATE
         src/core/dev/RTCTimer.cpp
         src/core/dev/storage/M24C32.cpp
         src/core/dev/Thermistor.cpp
-        src/core/utils/log.cpp)
+        src/core/utils/log.cpp
+        src/core/io/FMC.cpp)
 
 get_directory_property(COMPDEFS COMPILE_DEFINITIONS)
 if(COMPDEFS MATCHES "(.*)STM32F3xx(.*)")
@@ -74,7 +75,8 @@ elseif(COMPDEFS MATCHES "(.*)STM32F4xx(.*)")
     src/core/io/platform/f4xx/SPIf4xx.cpp
     src/core/dev/platform/f4xx/IWDGf4xx.cpp
     src/core/dev/platform/f4xx/RTCf4xx.cpp
-    src/core/dev/platform/f4xx/Timerf4xx.cpp)
+    src/core/dev/platform/f4xx/Timerf4xx.cpp
+    src/core/io/platform/f4xx/FMCf4xx.cpp)
 else()
     message(FATAL_ERROR "the HAL didnt compile in top level CMake")
 endif()

include/core/io/FMC.hpp

@@ -0,0 +1,37 @@
+#ifndef EVT_FMC_HPP
+#define EVT_FMC_HPP
+
+#include <cstdint>
+
+namespace core::io {
+
+class FMC {
+public:
+    /**
+     * Initializes an FMC device
+     */
+    FMC(uint32_t sdramMemoryAddress);
+
+    /**
+     * Write a value to SDRAM at the specified byte offset.
+     *
+     * @param[in] offset Byte offset from the SDRAM base address
+     * @param[in] value Value to write to memory
+     */
+    void write32(uint32_t offset, uint32_t value) const;
+
+    /**
+     * Read a value SDRAM at the specified byte offset.
+     *
+     * @param[in] offset Byte offset from the SDRAM base address
+     */
+    uint32_t read32(uint32_t offset) const;
+protected:
+    uint32_t sdramMemoryAddress;
+};
+
+}
+
+#endif // EVT_FMC_HPP
+
+

include/core/io/platform/f4xx/FMCf4xx.hpp

@@ -19,6 +19,8 @@
 #include "HALf4/stm32f4xx_ll_fmc.h"
 #include "HALf4/stm32f4xx_hal_sdram.h"
 
+#include "core/io/FMC.hpp"
+
 #define SDRAM_TIMEOUT (0x0000FFFFUL)
 
 typedef struct {
@@ -127,7 +129,7 @@ namespace core::io {
  * configures SDRAM timing parameters, and provides simple 32-bit
  * memory read/write access methods.
  */
-class FMCf4xx {
+class FMCf4xx : public FMC {
 public:
     /**
      * Structure to simplify SDRAM initialization, pre-filled with default values
@@ -236,20 +238,9 @@ class FMCf4xx {
      */
     FMCf4xx(FMCPinConfig pinConfig, SdramInitConfig sdramInitConfig, SdramTimingConfig sdramTimingConfig);
 
-    /**
-     * Write a value to SDRAM at the specified byte offset.
-     *
-     * @param[in] offset Byte offset from the SDRAM base address
-     * @param[in] value Value to write to memory
-     */
     void write32(uint32_t offset, uint32_t value) const;
 
-    /**
-     * Read a value SDRAM at the specified byte offset.
-     *
-     * @param[in] offset Byte offset from the SDRAM base address
-     */
-    [[nodiscard]] uint32_t read32(uint32_t offset) const;
+    uint32_t read32(uint32_t offset) const;
 
 private:
     /**
@@ -267,14 +258,17 @@ class FMCf4xx {
      */
     void InitPinGroup(const FMC_GPIO* pins, uint8_t count);
 
+    /**
+     * @return the base address depending on the bank number
+     */
+    uint32_t getSdramBaseAddress();
+
     SdramInitConfig sdramInitConfig;
     SdramTimingConfig sdramTimingConfig;
     FMCPinConfig fmcPinConfig;
 
     SDRAM_HandleTypeDef sdram;
     FMC_SDRAM_TimingTypeDef sdramTiming;
-
-    uint32_t sdramMemoryAddress; //address to read and write to
 };
 
 }

libs/HALf4/src/stm32f4xx_hal_sdram.c

@@ -1212,7 +1212,7 @@ uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram)
   *                the configuration information for SDRAM module.
   * @retval HAL state
   */
-HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(const SDRAM_HandleTypeDef *hsdram)
+HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram)
 {
   return hsdram->State;
 }

src/core/io/FMC.cpp

@@ -0,0 +1,9 @@
+#include "core/io/FMC.hpp"
+
+namespace core::io {
+
+FMC::FMC(uint32_t sdramMemoryAddress) {
+    this->sdramMemoryAddress = sdramMemoryAddress;
+}
+
+} // namespace core::io

src/core/io/platform/f4xx/FMCf4xx.cpp

@@ -1,13 +1,17 @@
 #include <core/io/platform/f4xx/FMCf4xx.hpp>
+#include <core/io/FMC.hpp>
 
 namespace core::io {
 
-FMCf4xx::FMCf4xx(const FMCPinConfig pinConfig, const SdramInitConfig sdramInitConfig, const SdramTimingConfig sdramTimingConfig) :
+FMCf4xx::FMCf4xx(FMCPinConfig pinConfig, SdramInitConfig sdramInitConfig, SdramTimingConfig sdramTimingConfig) :
+FMC(0xC0000000),
 sdramInitConfig(sdramInitConfig),
 sdramTimingConfig(sdramTimingConfig),
 fmcPinConfig(pinConfig),
 sdram({nullptr}),
 sdramTiming({0}) {
+    // FMC(getSdramBaseAddress());
+
     InitHardware(pinConfig);
 
     // map the class init structs to the hal structs
@@ -30,11 +34,6 @@ sdramTiming({0}) {
     sdramTiming.RCDDelay = sdramTimingConfig.rcdDelay;
 
     HAL_SDRAM_Init(&sdram, &sdramTiming);
-
-    if (sdramInitConfig.sdBank == FMC_SDRAM_BANK1) //determine read write memory address
-        sdramMemoryAddress = 0xC0000000;
-    else
-        sdramMemoryAddress = 0xD0000000;
 }
 
 void FMCf4xx::write32(uint32_t offset, uint32_t value) const {
@@ -67,6 +66,13 @@ uint32_t FMCf4xx::read32(uint32_t offset) const {
     return *ptr;
 }
 
+uint32_t FMCf4xx::getSdramBaseAddress() {
+    if (sdramInitConfig.sdBank == FMC_SDRAM_BANK1) //determine read write memory address
+        return 0xC0000000;
+
+    return 0xD0000000; //else
+}
+
 void FMCf4xx::InitHardware(const FMCPinConfig& pinConfig) {
     __HAL_RCC_FMC_CLK_ENABLE();