diff --git a/CMakeLists.txt b/CMakeLists.txt
index a59b8047..76e3f3dc 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -66,6 +66,7 @@ elseif(COMPDEFS MATCHES "(.*)STM32F4xx(.*)")
     target_sources(${PROJECT_NAME} PRIVATE
     src/core/utils/platform/f4xx/timef4xx.cpp
     src/core/platform/f4xx/stm32f446xx.cpp
+    src/core/platform/f4xx/stm32f469xx.cpp
     src/core/io/platform/f4xx/ADCf4xx.cpp
     src/core/io/platform/f4xx/CANf4xx.cpp
     src/core/io/platform/f4xx/GPIOf4xx.cpp
diff --git a/include/core/manager.hpp b/include/core/manager.hpp
index 0d26e4ad..b960f5ae 100644
--- a/include/core/manager.hpp
+++ b/include/core/manager.hpp
@@ -61,7 +61,6 @@
     #include <core/io/platform/f4xx/SPIf4xx.hpp>
     #include <core/io/platform/f4xx/UARTf4xx.hpp>
     #include <core/platform/f4xx/stm32f4xx.hpp>
-
 #endif
 
 namespace core::platform {
diff --git a/src/core/platform/f4xx/stm32f446xx.cpp b/src/core/platform/f4xx/stm32f446xx.cpp
index 6cb566cd..671e0950 100644
--- a/src/core/platform/f4xx/stm32f446xx.cpp
+++ b/src/core/platform/f4xx/stm32f446xx.cpp
@@ -4,6 +4,8 @@
 
 #include <core/platform/f4xx/stm32f4xx.hpp>
 
+#ifdef STM32F446xx
+
 using namespace std;
 namespace core::platform {
 
@@ -68,3 +70,5 @@ void Error_Handler(void) {
 }
 
 } // namespace core::platform
+
+#endif
\ No newline at end of file
diff --git a/src/core/platform/f4xx/stm32f469xx.cpp b/src/core/platform/f4xx/stm32f469xx.cpp
new file mode 100644
index 00000000..6f096ac9
--- /dev/null
+++ b/src/core/platform/f4xx/stm32f469xx.cpp
@@ -0,0 +1,65 @@
+#include <HALf4/stm32f4xx.h>
+#include <HALf4/stm32f4xx_hal.h>
+
+#include <core/platform/f4xx/stm32f4xx.hpp>
+
+#ifdef STM32F469xx
+
+using namespace std;
+namespace core::platform {
+
+void stm32f4xx_init() {
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+    /** Configure the main internal regulator output voltage
+     */
+    __HAL_RCC_PWR_CLK_ENABLE();
+    __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+    /** Initializes the RCC Oscillators according to the specified parameters
+     * in the RCC_OscInitTypeDef structure.
+     */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI;
+    RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
+    RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
+    RCC_OscInitStruct.PLL.PLLM            = 8;
+    RCC_OscInitStruct.PLL.PLLN            = 180;
+    RCC_OscInitStruct.PLL.PLLP            = RCC_PLLP_DIV2;
+    RCC_OscInitStruct.PLL.PLLQ            = 4;
+    RCC_OscInitStruct.PLL.PLLR            = 2;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        Error_Handler();
+    }
+
+    /** Activate the Over-Drive mode
+     */
+    if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
+        Error_Handler();
+    }
+
+    /** Initializes the CPU, AHB and APB buses clocks
+     */
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK;
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
+        Error_Handler();
+    }
+}
+
+void Error_Handler(void) {
+    /* USER CODE BEGIN Error_Handler_Debug */
+    /* User can add his own implementation to report the HAL error return state */
+    __disable_irq();
+    /* USER CODE END Error_Handler_Debug */
+}
+
+} // namespace core::platform
+
+#endif
\ No newline at end of file