update amd-develop with amd-staging (#8)

* Absorb upstream carnage around `Triple`. (#6)

* Re-sync with upstream, fix BitCast noise (#7)

* Update after llvm::Triple changes (#3046)

Update after llvm-project commit `979c275097a6 ("[IR] Store Triple in
Module (NFC) (#129868)", 2025-03-06)`.

* Corrected subnormal checking logic issubnormal(V) ==> unsigned(abs(V) -1) (#3036)

Corrected sunormal checking logic in is_fpclass intrinsic issubnormal(V)
==> unsigned(abs(V) - 1) < (all mantissa bits set)
corrected the testfile to check the corrected logic

* properly handle LOD values when nontemporal image operand is present (#3050)

Instead of checking that the image operands are equal to the LOD mask,
check that the LOD bit is in the image operands. This way an LOD value
of zero may be ignored even when image operands contains bits other than
the LOD bit, such as for the SPIR-V 1.6 nontemporal image operand.

fixes #3049

* [NFC] Add some missing includes (#3045)

llvm-spirv.cpp was relying on transitive includes for these.

Also remove an unneeded `<set>` include.

* Emit error for LLVM bfloat type (#3047)

Signed-off-by: Arvind Sudarsanam <[email protected]>

* Update DebugInfo test after LLVM change (#3060)

Update the pattern after llvm-project commit da0f9e75d858 ("Reland: [MC]
output inlined-at debug info (#106230) (#130306)", 2025-03-11).

---------

Signed-off-by: Arvind Sudarsanam <[email protected]>
Co-authored-by: Sven van Haastregt <[email protected]>
Co-authored-by: sumesh-s-mcw <[email protected]>
Co-authored-by: Ben Ashbaugh <[email protected]>
Co-authored-by: Arvind Sudarsanam <[email protected]>

---------

Signed-off-by: Arvind Sudarsanam <[email protected]>
Co-authored-by: Alex Voicu <[email protected]>
Co-authored-by: Sven van Haastregt <[email protected]>
Co-authored-by: sumesh-s-mcw <[email protected]>
Co-authored-by: Ben Ashbaugh <[email protected]>
Co-authored-by: Arvind Sudarsanam <[email protected]>

Author: 6 people

lib/SPIRV/OCLToSPIRV.cpp

@@ -316,7 +316,8 @@ void OCLToSPIRVBase::visitCallInst(CallInst &CI) {
       DemangledName == kOCLBuiltinName::Barrier ||
       DemangledName == kOCLBuiltinName::SubGroupBarrier) {
     if (F->arg_size() != 1 && F->arg_size() != 2 &&
-        F->getParent()->getTargetTriple() == "spirv64-amd-amdhsa")
+        F->getParent()->getTargetTriple().getVendor()
+          == Triple::VendorType::AMD)
       return; // Somebody used the name.
     visitCallBarrier(&CI);
     return;

lib/SPIRV/SPIRVReader.cpp

@@ -239,7 +239,7 @@ void SPIRVToOCLBase::visitCastInst(CastInst &Cast) {
       !isa<UIToFPInst>(Cast) && !isa<SIToFPInst>(Cast))
     return;
 
-  if (M->getTargetTriple() == "amdgcn-amd-amdhsa")
+  if (M->getTargetTriple().getVendor() == Triple::VendorType::AMD)
     return;
 
   Type const *SrcTy = Cast.getSrcTy();
@@ -755,8 +755,10 @@ SPIRVToOCLBase::mutateCallImageOperands(CallInst *CI, StringRef NewFuncName,
       ConstantFP *LodVal = dyn_cast<ConstantFP>(Mutator.getArg(ImOpArgIndex));
       // If the image operand is LOD and its value is zero, drop it too.
       if (LodVal && LodVal->isNullValue() &&
-          ImOpValue == ImageOperandsMask::ImageOperandsLodMask)
+          ImOpValue & ImageOperandsMask::ImageOperandsLodMask) {
         Mutator.removeArgs(ImOpArgIndex, Mutator.arg_size() - ImOpArgIndex);
+        ImOpValue &= ~ImageOperandsMask::ImageOperandsLodMask;
+      }
     }
   }
   return Mutator;

lib/SPIRV/SPIRVToOCL.cpp

@@ -184,7 +184,7 @@ static void visitCallLLVMFence(CallInst *CI) { // TODO: AMDSPV JANK, this is inc
 }
 
 void SPIRVToOCL20Base::visitCallSPIRVMemoryBarrier(CallInst *CI) {
-  if (M->getTargetTriple() == "amdgcn-amd-amdhsa")
+  if (M->getTargetTriple().getVendor() == Triple::VendorType::AMD)
     return visitCallLLVMFence(CI);
 
   Value *MemScope =
@@ -245,7 +245,7 @@ void SPIRVToOCL20Base::mutateAtomicName(CallInst *CI, Op OC) {
 void SPIRVToOCL20Base::visitCallSPIRVAtomicBuiltin(CallInst *CI, Op OC) {
   CallInst *CIG = mutateCommonAtomicArguments(CI, OC);
 
-  if (M->getTargetTriple() == "amdgcn-amd-amdhsa")
+  if (M->getTargetTriple().getVendor() == Triple::VendorType::AMD)
     return translateSPIRVAtomicBuiltinToLLVMAtomicOp(CIG, OC);
 
   switch (OC) {
@@ -289,8 +289,9 @@ CallInst *SPIRVToOCL20Base::mutateCommonAtomicArguments(CallInst *CI, Op OC) {
 
   Mutator.mapArgs([=](IRBuilder<> &Builder, Value *PtrArg, Type *PtrArgTy) {
     if (auto *TypedPtrTy = dyn_cast<TypedPointerType>(PtrArgTy)) {
-      unsigned AS = M->getTargetTriple() == "amdgcn-amd-amdhsa" ?
-          mapSPIRVAddrSpaceToAMDGPU(StorageClassGeneric) : SPIRAS_Generic;
+      unsigned AS = M->getTargetTriple().getVendor() == Triple::VendorType::AMD
+          ? mapSPIRVAddrSpaceToAMDGPU(StorageClassGeneric)
+          : SPIRAS_Generic;
       if (TypedPtrTy->getAddressSpace() != AS) {
         Type *ElementTy = TypedPtrTy->getElementType();
         Type *FixedPtr = PointerType::get(ElementTy, AS);
@@ -338,9 +339,10 @@ void SPIRVToOCL20Base::visitCallSPIRVAtomicCmpExchg(CallInst *CI) {
       .mapArg(1,
               [=](IRBuilder<> &Builder, Value *Expected) {
                 Builder.CreateStore(Expected, PExpected);
-                unsigned AddrSpc = M->getTargetTriple() == "amdgcn-amd-amdhsa" ?
-                    mapSPIRVAddrSpaceToAMDGPU(StorageClassGeneric) :
-                    SPIRAS_Generic;
+                unsigned AddrSpc =
+                    M->getTargetTriple().getVendor() == Triple::VendorType::AMD
+                      ? mapSPIRVAddrSpaceToAMDGPU(StorageClassGeneric)
+                      : SPIRAS_Generic;
                 Type *PtrTyAS = PointerType::get(PExpected->getType(), AddrSpc);
                 Value *V = Builder.CreateAddrSpaceCast(
                     PExpected, PtrTyAS, PExpected->getName() + ".as");
@@ -382,7 +384,7 @@ void SPIRVToOCL20Base::visitCallSPIRVEnqueueKernel(CallInst *CI, Op OC) {
 
   auto Mutator = mutateCallInst(CI, FName.str());
   Mutator.mapArg(6, [=](IRBuilder<> &Builder, Value *Invoke) {
-    unsigned AS = M->getTargetTriple() == "amdgcn-amd-amdhsa" ?
+    unsigned AS = M->getTargetTriple().getVendor() == Triple::VendorType::AMD ?
         mapSPIRVAddrSpaceToAMDGPU(StorageClassGeneric) : SPIRAS_Generic;
     Value *Replace = CastInst::CreatePointerBitCastOrAddrSpaceCast(
         Invoke, Builder.getPtrTy(AS), "", CI->getIterator());

lib/SPIRV/SPIRVToOCL20.cpp

@@ -303,7 +303,7 @@ Function *getOrCreateFunction(Module *M, Type *RetTy, ArrayRef<Type *> ArgTypes,
     if (F)
       NewF->setDSOLocal(F->isDSOLocal());
     F = NewF;
-    if (M->getTargetTriple() == "amdgcn-amd-amdhsa")
+    if (M->getTargetTriple().getVendor() == Triple::VendorType::AMD)
       F->setCallingConv(CallingConv::C);
     else
       F->setCallingConv(CallingConv::SPIR_FUNC);

lib/SPIRV/SPIRVUtil.cpp

@@ -397,6 +397,9 @@ SPIRVType *LLVMToSPIRVBase::transType(Type *T) {
     }
   }
 
+  // Emit error if type is bfloat. LLVM native bfloat type is not supported.
+  BM->getErrorLog().checkError(!T->isBFloatTy(),
+                               SPIRVEC_UnsupportedLLVMBFloatType);
   if (T->isFloatingPointTy())
     return mapType(T, BM->addFloatType(T->getPrimitiveSizeInBits()));
 
@@ -441,7 +444,8 @@ SPIRVType *LLVMToSPIRVBase::transType(Type *T) {
     //                     It must be at least 1.
     const auto ArraySize =
         T->getArrayNumElements() ? T->getArrayNumElements() :
-            (M->getTargetTriple() == "spirv64-amd-amdhsa" ? UINT32_MAX : 1);
+            (M->getTargetTriple().getVendor() == Triple::VendorType::AMD
+              ? UINT32_MAX : 1);
 
     Type *ElTy = T->getArrayElementType();
     SPIRVType *TransType = BM->addArrayType(
@@ -753,7 +757,7 @@ SPIRVType *LLVMToSPIRVBase::transPointerType(SPIRVType *ET, unsigned AddrSpc) {
     return transPointerType(ET, SPIRAS_Private);
   if (BM->isAllowedToUseExtension(ExtensionID::SPV_KHR_untyped_pointers) &&
       !(ET->isTypeArray() || ET->isTypeVector() || ET->isSPIRVOpaqueType() ||
-        (M->getTargetTriple() == "spirv64-amd-amdhsa" &&
+        (M->getTargetTriple().getVendor() == Triple::VendorType::AMD &&
          ET->getOpCode() == OpTypeFunction))) {
     TranslatedTy = BM->addUntypedPointerKHRType(
         SPIRSPIRVAddrSpaceMap::map(static_cast<SPIRAddressSpace>(AddrSpc)));
@@ -842,12 +846,12 @@ SPIRVType *LLVMToSPIRVBase::transScavengedType(Value *V) {
     // error. To be on the safe side, an assertion is added to check printf
     // never reaches this point.
     assert(F->getName() != "printf");
-    if (M->getTargetTriple() != "spirv64-amd-amdhsa")
+    if (M->getTargetTriple().getVendor() != Triple::VendorType::AMD)
       BM->getErrorLog().checkError(!FnTy->isVarArg(),
                                    SPIRVEC_UnsupportedVarArgFunction);
 
     SPIRVType *RT = transType(FnTy->getReturnType());
-    if (M->getTargetTriple() == "spirv64-amd-amdhsa" &&
+    if (M->getTargetTriple().getVendor() == Triple::VendorType::AMD &&
         F->hasName() && F->getName().contains("dispatch.ptr"))
       RT = transType(PointerType::get(F->getContext(), SPIRAS_Constant));
 
@@ -1596,7 +1600,8 @@ SPIRVValue *LLVMToSPIRVBase::transUnaryInst(UnaryInstruction *U,
       return BM->addUndef(ExpectedTy);
     }
   }
-  if (isa<VAArgInst>(U) && M->getTargetTriple() == "spirv64-amd-amdhsa") {
+  if (isa<VAArgInst>(U) &&
+      M->getTargetTriple().getVendor() == Triple::VendorType::AMD) {
     SPIRVType *ExpectedTy = transScavengedType(U);
     return BM->addUndef(ExpectedTy);
   }
@@ -1606,7 +1611,7 @@ SPIRVValue *LLVMToSPIRVBase::transUnaryInst(UnaryInstruction *U,
     const auto SrcAddrSpace = Cast->getSrcTy()->getPointerAddressSpace();
     const auto DestAddrSpace = Cast->getDestTy()->getPointerAddressSpace();
     if (DestAddrSpace == SPIRAS_Generic) {
-      if (M->getTargetTriple() != "spirv64-amd-amdhsa")
+      if (M->getTargetTriple().getVendor() != Triple::VendorType::AMD)
         getErrorLog().checkError(
             SrcAddrSpace != SPIRAS_Constant, SPIRVEC_InvalidModule, U,
             "Casts from constant address space to generic are illegal\n");
@@ -1649,7 +1654,7 @@ SPIRVValue *LLVMToSPIRVBase::transUnaryInst(UnaryInstruction *U,
           SrcAddrSpace == SPIRAS_Generic, SPIRVEC_InvalidModule, U,
           "Casts from private/local/global address space are allowed only to "
           "generic\n");
-      if (M->getTargetTriple() != "spirv64-amd-amdhsa")
+      if (M->getTargetTriple().getVendor() != Triple::VendorType::AMD)
         getErrorLog().checkError(
             DestAddrSpace != SPIRAS_Constant, SPIRVEC_InvalidModule, U,
             "Casts from generic address space to constant are illegal\n");
@@ -2131,7 +2136,7 @@ LLVMToSPIRVBase::transValueWithoutDecoration(Value *V, SPIRVBasicBlock *BB,
         GV->isConstant(), transLinkageType(GV), BVarInit, GV->getName().str(),
         StorageClass, nullptr));
     if (GV->isExternallyInitialized() &&
-        M->getTargetTriple() == "spirv64-amd-amdhsa")
+        M->getTargetTriple().getVendor() == Triple::VendorType::AMD)
       BVar->addDecorate(DecorationUserTypeGOOGLE,
                         BM->getString("externally_initialized")->getId());
 
@@ -2320,10 +2325,11 @@ LLVMToSPIRVBase::transValueWithoutDecoration(Value *V, SPIRVBasicBlock *BB,
             BB));
 
   if (AllocaInst *Alc = dyn_cast<AllocaInst>(V)) {
-    SPIRVType *TranslatedTy = M->getTargetTriple() != "spirv64-amd-amdhsa" ?
-        transScavengedType(V) :
-        BM->addPointerType(StorageClassFunction,
-                           transType(Alc->getAllocatedType()));
+    SPIRVType *TranslatedTy =
+        M->getTargetTriple().getVendor() != Triple::VendorType::AMD
+          ? transScavengedType(V)
+          : BM->addPointerType(StorageClassFunction,
+                               transType(Alc->getAllocatedType()));
     if (Alc->isArrayAllocation()) {
       SPIRVValue *Length = transValue(Alc->getArraySize(), BB);
       assert(Length && "Couldn't translate array size!");
@@ -3140,7 +3146,7 @@ bool LLVMToSPIRVBase::transDecoration(Value *V, SPIRVValue *BV) {
         ((Opcode == Instruction::FNeg || Opcode == Instruction::FCmp ||
           BV->isExtInst()) &&
          BM->isAllowedToUseVersion(VersionNumber::SPIRV_1_6)) ||
-        (M->getTargetTriple() == "spirv64-amd-amdhsa" &&
+        (M->getTargetTriple().getVendor() == Triple::VendorType::AMD &&
          Opcode == Instruction::Call)) {
       FastMathFlags FMF = BVF->getFastMathFlags();
       SPIRVWord M{0};
@@ -3260,7 +3266,8 @@ void LLVMToSPIRVBase::transMemAliasingINTELDecorations(Instruction *Inst,
   if (!BM->isAllowedToUseExtension(
           ExtensionID::SPV_INTEL_memory_access_aliasing))
     return;
-  if (!BV->hasId() && M->getTargetTriple() == "spirv64-amd-amdhsa") // Fences
+  if (!BV->hasId() &&
+      M->getTargetTriple().getVendor() == Triple::VendorType::AMD) // Fences
     return;
   if (MDNode *AliasingListMD = Inst->getMetadata(LLVMContext::MD_alias_scope)) {
     auto *MemAliasList = addMemAliasingINTELInstructions(BM, AliasingListMD);
@@ -5074,7 +5081,7 @@ SPIRVValue *LLVMToSPIRVBase::transIntrinsicInst(IntrinsicInst *II,
     const APInt Inf = APFloat::getInf(Semantics).bitcastToAPInt();
     const APInt AllOneMantissa =
         APFloat::getLargest(Semantics).bitcastToAPInt() & ~Inf;
-
+    const APInt OneValue = APInt(BitSize, 1);
     // Some checks can be inverted tests for simple cases, for example
     // simultaneous check for inf, normal, subnormal and zero is a check for
     // non nan.
@@ -5183,8 +5190,10 @@ SPIRVValue *LLVMToSPIRVBase::transIntrinsicInst(IntrinsicInst *II,
           BM->addUnaryInst(OpBitcast, OpSPIRVTy, InputFloat, BB);
       auto *MantissaConst = transValue(
           Constant::getIntegerValue(IntOpLLVMTy, AllOneMantissa), BB);
+      auto *ConstOne =
+          transValue(Constant::getIntegerValue(IntOpLLVMTy, OneValue), BB);
       auto *MinusOne =
-          BM->addBinaryInst(OpISub, OpSPIRVTy, BitCastToInt, MantissaConst, BB);
+          BM->addBinaryInst(OpISub, OpSPIRVTy, BitCastToInt, ConstOne, BB);
       auto *TestIsSubnormal =
           BM->addCmpInst(OpULessThan, ResTy, MinusOne, MantissaConst, BB);
       if (FPClass & fcPosSubnormal && FPClass & fcNegSubnormal)
@@ -5529,7 +5538,7 @@ SPIRVValue *LLVMToSPIRVBase::transAsmINTEL(InlineAsm *IA) {
   // TODO: intention here is to provide information about actual target
   //       but in fact spir-64 is substituted as triple when translator works
   //       eventually we need to fix it (not urgent)
-  StringRef TripleStr(M->getTargetTriple());
+  StringRef TripleStr(M->getTargetTriple().str());
   auto *AsmTarget = static_cast<SPIRVAsmTargetINTEL *>(
       BM->getOrAddAsmTargetINTEL(TripleStr.str()));
   auto *SIA = BM->addAsmINTEL(
@@ -5980,7 +5989,7 @@ bool isEmptyLLVMModule(Module *M) {
 }
 
 bool LLVMToSPIRVBase::translate() {
-  if (M->getTargetTriple() == "spirv64-amd-amdhsa")
+  if (M->getTargetTriple().getVendor() == Triple::VendorType::AMD)
     BM->setGeneratorVer(UINT16_MAX);
   else
     BM->setGeneratorVer(KTranslatorVer);
@@ -7043,7 +7052,8 @@ bool isValidLLVMModule(Module *M, SPIRVErrorLog &ErrorLog) {
 
   Triple TT(M->getTargetTriple());
   if (!ErrorLog.checkError(isSupportedTriple(TT), SPIRVEC_InvalidTargetTriple,
-                           "Actual target triple is " + M->getTargetTriple()))
+                           "Actual target triple is " +
+                               M->getTargetTriple().str()))
     return false;
 
   return true;
@@ -7144,7 +7154,7 @@ bool runSpirvBackend(Module *M, std::string &Result, std::string &ErrMsg,
                              ? Triple::spirv64
                              : Triple::spirv32,
                          TargetTriple.getSubArch());
-    M->setTargetTriple(TargetTriple.str());
+    M->setTargetTriple(TargetTriple);
     // We need to reset Data Layout to conform with the TargetMachine
     M->setDataLayout("");
   }
@@ -7153,7 +7163,7 @@ bool runSpirvBackend(Module *M, std::string &Result, std::string &ErrMsg,
       TargetTriple.setTriple(DefaultTriple);
     TargetTriple.setArch(TargetTriple.getArch(),
                          spirvVersionToSubArch(TranslatorOpts.getMaxVersion()));
-    M->setTargetTriple(TargetTriple.str());
+    M->setTargetTriple(TargetTriple);
   }
 
   // Translate the Module into SPIR-V

lib/SPIRV/SPIRVWriter.cpp

@@ -28,6 +28,8 @@ _SPIRV_OP(UnspecifiedMemoryModel, "Unspecified Memory Model.")
 _SPIRV_OP(RepeatedMemoryModel, "Expects a single OpMemoryModel instruction.")
 _SPIRV_OP(UnsupportedVarArgFunction,
           "Variadic functions other than 'printf' are not supported in SPIR-V.")
+_SPIRV_OP(UnsupportedLLVMBFloatType,
+          "LLVM bfloat type is not supported in SPIR-V.")
 
 /* This is the last error code to have a maximum valid value to compare to */
 _SPIRV_OP(InternalMaxErrorCode, "Unknown error code")

lib/SPIRV/libSPIRV/SPIRVErrorEnum.h

@@ -0,0 +1,22 @@
+; Check that translator emits error for LLVM bfloat type
+; RUN: llvm-as %s -o %t.bc
+; RUN: not amd-llvm-spirv --spirv-ext=+all %t.bc -o %t.spv 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
+
+; CHECK-ERROR: UnsupportedLLVMBFloatType: LLVM bfloat type is not supported in SPIR-V
+
+target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
+target triple = "spir-unknown-unknown"
+
+; Function Attrs: nounwind
+define spir_kernel void @testBFloat(bfloat %a, bfloat %b) {
+entry:
+  %r1 = fmul bfloat %a, %b
+  ret void
+}
+
+!llvm.module.flags = !{!0}
+!opencl.ocl.version = !{!1}
+!opencl.spir.version = !{!1}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 2, i32 0}

test/bfloat.ll

@@ -0,0 +1,45 @@
+; Tests the Nontemporal image operand that was added for SPIR-V 1.6.
+
+; REQUIRES: spirv-as
+; RUN: spirv-as --target-env spv1.6 -o %t.spv %s
+; RUN: spirv-val %t.spv
+; RUN: amd-llvm-spirv -r %t.spv -o %t.rev.bc
+; RUN: llvm-dis %t.rev.bc
+; RUN: FileCheck < %t.rev.ll %s --check-prefix=CHECK-LLVM
+
+               OpCapability Addresses
+               OpCapability Kernel
+               OpCapability ImageBasic
+               OpCapability LiteralSampler
+               OpMemoryModel Physical64 OpenCL
+               OpEntryPoint Kernel %kernel "read_write_image_nontemporal"
+       %uint = OpTypeInt 32 0
+       %void = OpTypeVoid
+ %read_image2d_t = OpTypeImage %void 2D 0 0 0 0 Unknown ReadOnly
+%write_image2d_t = OpTypeImage %void 2D 0 0 0 0 Unknown WriteOnly
+  %sampler_t = OpTypeSampler
+ %kernel_sig = OpTypeFunction %void %read_image2d_t %write_image2d_t
+%sampledimage_t = OpTypeSampledImage %read_image2d_t
+     %v2uint = OpTypeVector %uint 2
+      %float = OpTypeFloat 32
+    %v4float = OpTypeVector %float 4
+    %sampler = OpConstantSampler %sampler_t None 0 Nearest
+  %coord_0_0 = OpConstantNull %v2uint
+    %float_0 = OpConstant %float 0
+     %kernel = OpFunction %void None %kernel_sig
+        %src = OpFunctionParameter %read_image2d_t
+        %dst = OpFunctionParameter %write_image2d_t
+      %entry = OpLabel
+         %si = OpSampledImage %sampledimage_t %src %sampler
+      %data0 = OpImageSampleExplicitLod %v4float %si %coord_0_0 Lod %float_0
+               OpImageWrite %dst %coord_0_0 %data0
+      %data1 = OpImageSampleExplicitLod %v4float %si %coord_0_0 Lod|Nontemporal %float_0
+               OpImageWrite %dst %coord_0_0 %data1 Nontemporal
+               OpReturn
+               OpFunctionEnd
+
+; CHECK-LLVM: define spir_kernel void @read_write_image_nontemporal
+; CHECK-LLVM: call spir_func <4 x float> [[READ_IMAGEF:@[a-zA-Z0-9_]+]](
+; CHECK-LLVM: call spir_func void [[WRITE_IMAGEF:@[a-zA-Z0-9_]+]](
+; CHECK-LLVM: call spir_func <4 x float> [[READ_IMAGEF]](
+; CHECK-LLVM: call spir_func void [[WRITE_IMAGEF]](