COMGR HotSwap must inspect a gfx1250 B0 legacy VOP3 instruction while using the gfx1250 A0 MC decoder. The A0 decoder advances one dword and reports the B0-only opcode as unknown, so COMGR currently has no installed MC API that can establish that the complete 64-bit pair is a vector ALU instruction which cannot affect scalar control flow or MODE.\n\nPlease expose an installed AMDGPU MC/TargetParser API that can classify legacy stepping encodings (including instruction length and conservative register/control-flow effects) without duplicating backend-private TableGen fields in COMGR. AMDGPUBaseInfo.h and named operand helpers are backend-private and unavailable to installed COMGR builds.\n\nUntil this exists, the HotSwap M32 Scale16 work will keep one exact, fail-closed classifier for the observed B0 pair, reject any known entry into its continuation dword, and cover positive and near-miss encodings with focused tests.
COMGR HotSwap must inspect a gfx1250 B0 legacy VOP3 instruction while using the gfx1250 A0 MC decoder. The A0 decoder advances one dword and reports the B0-only opcode as unknown, so COMGR currently has no installed MC API that can establish that the complete 64-bit pair is a vector ALU instruction which cannot affect scalar control flow or MODE.\n\nPlease expose an installed AMDGPU MC/TargetParser API that can classify legacy stepping encodings (including instruction length and conservative register/control-flow effects) without duplicating backend-private TableGen fields in COMGR.
AMDGPUBaseInfo.hand named operand helpers are backend-private and unavailable to installed COMGR builds.\n\nUntil this exists, the HotSwap M32 Scale16 work will keep one exact, fail-closed classifier for the observed B0 pair, reject any known entry into its continuation dword, and cover positive and near-miss encodings with focused tests.