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Commit 8f59834

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leowu2017leowu2017
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fix incorrect GRVWM in logic YAML
1 parent fe479d7 commit 8f59834

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Lines changed: 8 additions & 8 deletions

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‎projects/hipsparselt/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/GridBased/aquavanjaram_Cijk_Alik_Bljk_BBS_BH_Bias_FDMN_SPB_A_S_SAV.yaml‎

Lines changed: 4 additions & 4 deletions
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‎projects/hipsparselt/library/src/hcc_detail/rocsparselt/src/spmm/Tensile/Logic/asm_full/aquavanjaram/gfx942/GridBased/aquavanjaram_Cijk_Alik_Bljk_HHS_BH_Bias_FDMN_SPB_A_S_SAV.yaml‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change

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