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Merge pull request herd#1846 from murzinv/fix-x12
[gen][AArch64] Properly reserve X12 for SME
2 parents bd62991 + 56d536b commit 585e44d

2 files changed

Lines changed: 9 additions & 11 deletions

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gen/AArch64Compile_gen.ml

Lines changed: 1 addition & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -50,16 +50,7 @@ module Make(Cfg:Config) : XXXCompile_gen.S =
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(* Reserve SME's slice index register *)
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let x12 = Ireg R12
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53-
let next_reg x =
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if do_sme then
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begin
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let r,x = A64.alloc_reg x in
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match r with
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| Ireg R12 -> A64.alloc_reg x
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| _ -> r,x
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end
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else
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A64.alloc_reg x
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let next_reg x = A64.alloc_reg x
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let next_reg2 x =
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let r1,x = next_reg x in

gen/common/AArch64Arch_gen.ml

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1109,6 +1109,13 @@ let is_valid_rmw rmw_list =
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List.length atomic_st_list = List.length (Util.List.uniq ~eq:atomic_op_equal atomic_st_list)
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end
11111111

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let free_registers =
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if do_sme then
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(* Reserve SME's slice index register *)
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List.filter ( fun r -> r != Ireg R12) allowed_for_symb
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else
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allowed_for_symb
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include
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ArchExtra_gen.Make
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(struct
@@ -1119,7 +1126,7 @@ include
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| _ -> false
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let pp_reg = pp_reg
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let free_registers = allowed_for_symb
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let free_registers = free_registers
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type special = reg
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type special2 = reg

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