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1 | 1 | #![allow(non_camel_case_types)]
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2 | 2 | //! Analog-to-Digital Converter
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3 | 3 |
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4 |
| -use crate::port; |
| 4 | +use crate::{pac, port::*}; |
5 | 5 | pub use avr_hal_generic::adc::{AdcChannel, AdcOps, ClockDivider};
|
6 | 6 |
|
7 | 7 | /// Check the [`avr_hal_generic::adc::Adc`] documentation.
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@@ -32,109 +32,150 @@ pub mod channel {
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32 | 32 |
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33 | 33 | #[cfg(feature = "attiny85")]
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34 | 34 | avr_hal_generic::impl_adc! {
|
35 |
| - hal: crate::Attiny, |
36 |
| - peripheral: crate::pac::ADC, |
37 |
| - settings: AdcSettings, |
38 |
| - apply_settings: |peripheral, settings| { |
39 |
| - apply_clock(peripheral, settings); |
40 |
| - peripheral.admux.write(|w| match settings.ref_voltage { |
| 35 | + /// Select the voltage reference for the ADC peripheral |
| 36 | + /// |
| 37 | + /// The internal voltage reference options may not be used if an external reference voltage is |
| 38 | + /// being applied to the AREF pin. |
| 39 | + #[derive(Debug, Default, Clone, Copy, PartialEq, Eq)] |
| 40 | + #[repr(u8)] |
| 41 | + pub enum ReferenceVoltage { |
| 42 | + /// Voltage applied to AREF pin. |
| 43 | + Aref, |
| 44 | + /// System reference voltage, GND (default). |
| 45 | + #[default] |
| 46 | + AVcc, |
| 47 | + /// Internal 1.1V reference. |
| 48 | + Internal1_1, |
| 49 | + /// Internal 2.56V reference. |
| 50 | + Internal2_56, |
| 51 | + } |
| 52 | + |
| 53 | + pub fn set_reference(self, settings: Self::Settings) { |
| 54 | + self.admux.write(|w| match settings.ref_voltage { |
41 | 55 | ReferenceVoltage::Aref => w.refs().aref(),
|
42 | 56 | ReferenceVoltage::AVcc => w.refs().vcc(),
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43 | 57 | ReferenceVoltage::Internal1_1 => w.refs().internal().refs2().clear_bit(),
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44 | 58 | ReferenceVoltage::Internal2_56 => w.refs().internal().refs2().set_bit(),
|
45 | 59 | });
|
46 |
| - }, |
47 |
| - channel_id: crate::pac::adc::admux::MUX_A, |
48 |
| - set_channel: |peripheral, id| { |
49 |
| - peripheral.admux.modify(|_, w| w.mux().variant(id)); |
50 |
| - }, |
51 |
| - pins: { |
52 |
| - port::PB5: (crate::pac::adc::admux::MUX_A::ADC0, didr0::adc0d), |
53 |
| - port::PB2: (crate::pac::adc::admux::MUX_A::ADC1, didr0::adc1d), |
54 |
| - port::PB4: (crate::pac::adc::admux::MUX_A::ADC2, didr0::adc2d), |
55 |
| - port::PB3: (crate::pac::adc::admux::MUX_A::ADC3, didr0::adc3d), |
56 |
| - }, |
57 |
| - channels: { |
58 |
| - channel::Vbg: crate::pac::adc::admux::MUX_A::ADC_VBG, |
59 |
| - channel::Gnd: crate::pac::adc::admux::MUX_A::ADC_GND, |
60 |
| - channel::Temperature: crate::pac::adc::admux::MUX_A::TEMPSENS, |
61 |
| - }, |
62 |
| -} |
| 60 | + } |
| 61 | + pub fn set_channel(self, channel: Self::Channel) { |
| 62 | + self.admux.modify(|_, w| w.mux().variant(channel)); |
| 63 | + } |
63 | 64 |
|
| 65 | + impl AdcProvider for pac::ADC { |
| 66 | + type Hal = crate::Attiny; |
| 67 | + |
| 68 | + const PB5: DIDR0::ADC0D = pac::adc::admux::MUX_A::ADC0; |
| 69 | + const PB2: DIDR0::ADC1D = pac::adc::admux::MUX_A::ADC1; |
| 70 | + const PB4: DIDR0::ADC2D = pac::adc::admux::MUX_A::ADC2; |
| 71 | + const PB3: DIDR0::ADC3D = pac::adc::admux::MUX_A::ADC3; |
| 72 | + } |
| 73 | + |
| 74 | + type ChannelId = pac::adc::admux::MUX_A; |
| 75 | + pub enum Channels { |
| 76 | + channel::Vbg = pac::adc::admux::MUX_A::ADC_VBG, |
| 77 | + channel::Gnd = pac::adc::admux::MUX_A::ADC_GND, |
| 78 | + channel::Temperature = pac::adc::admux::MUX_A::TEMPSENS, |
| 79 | + } |
| 80 | +} |
64 | 81 |
|
65 | 82 | #[cfg(feature = "attiny88")]
|
66 | 83 | avr_hal_generic::impl_adc! {
|
67 |
| - hal: crate::Attiny, |
68 |
| - peripheral: crate::pac::ADC, |
69 |
| - settings: AdcSettings, |
70 |
| - apply_settings: |peripheral, settings| { |
71 |
| - apply_clock(peripheral, settings); |
72 |
| - peripheral.admux.write(|w| match settings.ref_voltage { |
| 84 | + /// Select the voltage reference for the ADC peripheral |
| 85 | + /// |
| 86 | + /// The internal voltage reference options may not be used if an external reference voltage is |
| 87 | + /// being applied to the AREF pin. |
| 88 | + #[derive(Debug, Default, Clone, Copy, PartialEq, Eq)] |
| 89 | + #[repr(u8)] |
| 90 | + pub enum ReferenceVoltage { |
| 91 | + /// System reference voltage, GND (default). |
| 92 | + #[default] |
| 93 | + AVcc, |
| 94 | + /// Internal 1.1V reference. |
| 95 | + Internal1_1, |
| 96 | + } |
| 97 | + |
| 98 | + pub fn set_reference(self, settings: Self::Settings) { |
| 99 | + self.admux.write(|w| match settings.ref_voltage { |
73 | 100 | ReferenceVoltage::AVcc => w.refs0().avcc(),
|
74 | 101 | ReferenceVoltage::Internal1_1 => w.refs0().internal(),
|
75 | 102 | });
|
76 |
| - }, |
77 |
| - channel_id: crate::pac::adc::admux::MUX_A, |
78 |
| - set_channel: |peripheral, id| { |
79 |
| - peripheral.admux.modify(|_, w| w.mux().variant(id)); |
80 |
| - }, |
81 |
| - pins: { |
82 |
| - port::PC0: (crate::pac::adc::admux::MUX_A::ADC0, didr0::adc0d), |
83 |
| - port::PC1: (crate::pac::adc::admux::MUX_A::ADC1, didr0::adc1d), |
84 |
| - port::PC2: (crate::pac::adc::admux::MUX_A::ADC2, didr0::adc2d), |
85 |
| - port::PC3: (crate::pac::adc::admux::MUX_A::ADC3, didr0::adc3d), |
86 |
| - port::PC4: (crate::pac::adc::admux::MUX_A::ADC4, didr0::adc4d), |
87 |
| - port::PC5: (crate::pac::adc::admux::MUX_A::ADC5, didr0::adc5d), |
88 |
| - port::PA0: (crate::pac::adc::admux::MUX_A::ADC6, didr0::adc6d), |
89 |
| - port::PA1: (crate::pac::adc::admux::MUX_A::ADC7, didr0::adc7d), |
90 |
| - }, |
91 |
| - channels: { |
92 |
| - channel::Vbg: crate::pac::adc::admux::MUX_A::ADC_VBG, |
93 |
| - channel::Gnd: crate::pac::adc::admux::MUX_A::ADC_GND, |
94 |
| - channel::Temperature: crate::pac::adc::admux::MUX_A::TEMPSENS, |
95 |
| - }, |
96 |
| -} |
| 103 | + } |
| 104 | + pub fn set_channel(self, channel: Self::Channel) { |
| 105 | + self.admux.modify(|_, w| w.mux().variant(channel)); |
| 106 | + } |
97 | 107 |
|
| 108 | + impl AdcProvider for pac::ADC { |
| 109 | + type Hal = crate::Attiny; |
| 110 | + |
| 111 | + const PC0: DIDR0::ADC0D = pac::adc::admux::MUX_A::ADC0; |
| 112 | + const PC1: DIDR0::ADC1D = pac::adc::admux::MUX_A::ADC1; |
| 113 | + const PC2: DIDR0::ADC2D = pac::adc::admux::MUX_A::ADC2; |
| 114 | + const PC3: DIDR0::ADC3D = pac::adc::admux::MUX_A::ADC3; |
| 115 | + const PC4: DIDR0::ADC4D = pac::adc::admux::MUX_A::ADC4; |
| 116 | + const PC5: DIDR0::ADC5D = pac::adc::admux::MUX_A::ADC5; |
| 117 | + const PA0: DIDR0::ADC6D = pac::adc::admux::MUX_A::ADC6; |
| 118 | + const PA1: DIDR0::ADC7D = pac::adc::admux::MUX_A::ADC7; |
| 119 | + } |
| 120 | + |
| 121 | + type ChannelId = pac::adc::admux::MUX_A; |
| 122 | + pub enum Channels { |
| 123 | + channel::Vbg = pac::adc::admux::MUX_A::ADC_VBG, |
| 124 | + channel::Gnd = pac::adc::admux::MUX_A::ADC_GND, |
| 125 | + channel::Temperature = pac::adc::admux::MUX_A::TEMPSENS, |
| 126 | + } |
| 127 | +} |
98 | 128 |
|
99 | 129 | #[cfg(feature = "attiny167")]
|
100 | 130 | avr_hal_generic::impl_adc! {
|
101 |
| - hal: crate::Attiny, |
102 |
| - peripheral: crate::pac::ADC, |
103 |
| - settings: AdcSettings, |
104 |
| - apply_settings: |peripheral, settings| { |
105 |
| - apply_clock(peripheral, settings); |
106 |
| - peripheral.amiscr.write(|w| match settings.ref_voltage { |
| 131 | + /// Select the voltage reference for the ADC peripheral |
| 132 | + /// |
| 133 | + /// The internal voltage reference options may not be used if an external reference voltage is |
| 134 | + /// being applied to the AREF pin. |
| 135 | + #[derive(Debug, Default, Clone, Copy, PartialEq, Eq)] |
| 136 | + #[repr(u8)] |
| 137 | + pub enum ReferenceVoltage { |
| 138 | + /// Voltage applied to AREF pin. |
| 139 | + Aref, |
| 140 | + /// System reference voltage, GND (default). |
| 141 | + #[default] |
| 142 | + AVcc, |
| 143 | + /// Internal 1.1V reference. |
| 144 | + Internal1_1, |
| 145 | + /// Internal 2.56V reference. |
| 146 | + Internal2_56, |
| 147 | + } |
| 148 | + |
| 149 | + pub fn set_reference(self, settings: Self::Settings) { |
| 150 | + self.amiscr.write(|w| match settings.ref_voltage { |
107 | 151 | ReferenceVoltage::Aref => w.arefen().set_bit(),
|
108 | 152 | _ => w.arefen().clear_bit(),
|
109 | 153 | });
|
110 |
| - peripheral.admux.write(|w| match settings.ref_voltage { |
| 154 | + self.admux.write(|w| match settings.ref_voltage { |
111 | 155 | ReferenceVoltage::Aref => w.refs().avcc(),
|
112 | 156 | ReferenceVoltage::AVcc => w.refs().avcc(),
|
113 | 157 | ReferenceVoltage::Internal1_1 => w.refs().internal_11(),
|
114 | 158 | ReferenceVoltage::Internal2_56 => w.refs().internal_256(),
|
115 | 159 | });
|
116 |
| - }, |
117 |
| - channel_id: crate::pac::adc::admux::MUX_A, |
118 |
| - set_channel: |peripheral, id| { |
119 |
| - peripheral.admux.modify(|_, w| w.mux().variant(id)); |
120 |
| - }, |
121 |
| - pins: { |
122 |
| - port::PA0: (crate::pac::adc::admux::MUX_A::ADC0, didr0::adc0d), |
123 |
| - port::PA1: (crate::pac::adc::admux::MUX_A::ADC1, didr0::adc1d), |
124 |
| - port::PA2: (crate::pac::adc::admux::MUX_A::ADC2, didr0::adc2d), |
125 |
| - port::PA3: (crate::pac::adc::admux::MUX_A::ADC3, didr0::adc3d), |
126 |
| - port::PA4: (crate::pac::adc::admux::MUX_A::ADC4, didr0::adc4d), |
127 |
| - port::PA5: (crate::pac::adc::admux::MUX_A::ADC5, didr0::adc5d), |
128 |
| - port::PA6: (crate::pac::adc::admux::MUX_A::ADC6, didr0::adc6d), |
129 |
| - port::PA7: (crate::pac::adc::admux::MUX_A::ADC7, didr0::adc7d), |
130 |
| - port::PB5: (crate::pac::adc::admux::MUX_A::ADC8, didr1::adc8d), |
131 |
| - port::PB6: (crate::pac::adc::admux::MUX_A::ADC9, didr1::adc9d), |
132 |
| - port::PB7: (crate::pac::adc::admux::MUX_A::ADC10, didr1::adc10d), |
133 |
| - }, |
134 |
| - channels: { |
135 |
| - channel::AVcc_4: crate::pac::adc::admux::MUX_A::ADC_AVCC_4, |
136 |
| - channel::Vbg: crate::pac::adc::admux::MUX_A::ADC_VBG, |
137 |
| - channel::Gnd: crate::pac::adc::admux::MUX_A::ADC_GND, |
138 |
| - channel::Temperature: crate::pac::adc::admux::MUX_A::TEMPSENS, |
139 |
| - }, |
| 160 | + } |
| 161 | + pub fn set_channel(self, channel: Self::Channel) { |
| 162 | + self.admux.modify(|_, w| w.mux().variant(channel)); |
| 163 | + } |
| 164 | + |
| 165 | + impl AdcProvider for pac::ADC { |
| 166 | + type Hal = crate::Attiny; |
| 167 | + |
| 168 | + const PB5: DIDR0::ADC0D = pac::adc::admux::MUX_A::ADC0; |
| 169 | + const PB2: DIDR0::ADC1D = pac::adc::admux::MUX_A::ADC1; |
| 170 | + const PB4: DIDR0::ADC2D = pac::adc::admux::MUX_A::ADC2; |
| 171 | + const PB3: DIDR0::ADC3D = pac::adc::admux::MUX_A::ADC3; |
| 172 | + } |
| 173 | + |
| 174 | + type ChannelId = pac::adc::admux::MUX_A; |
| 175 | + pub enum Channels { |
| 176 | + channel::AVcc_4 = pac::adc::admux::MUX_A::ADC_AVCC_4, |
| 177 | + channel::Vbg = pac::adc::admux::MUX_A::ADC_VBG, |
| 178 | + channel::Gnd = pac::adc::admux::MUX_A::ADC_GND, |
| 179 | + channel::Temperature = pac::adc::admux::MUX_A::TEMPSENS, |
| 180 | + } |
140 | 181 | }
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