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"In this mode (4 step sequence), the interrupt flag is set every 29830 CPU cycles, which is slightly (0.166%) slower than the 29780.5 CPU cycles per NTSC PPU frame" - shouldn't it be on the last 3rd of the 4th step? but it also says toi set only if interrupt inhibit is clear
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linear counter: "If control flag is clear, clear halt flag." - aren't they the same bit?