Updated params to yosys so we can see what module that fail during synth

Ronny Hansen · Ronny Hansen · commit 106d1e48d4ca · 2025-02-12T20:12:44.000+01:00
diff --git a/Verilog/ND-120-Yosys/synh.bat b/Verilog/ND-120-Yosys/synh.bat
@@ -1 +1,5 @@
-yosys -s nd-120.ys -v 3 --trace --debug
+call "C:\Utils\oss-cad-suite\environment.bat" 
+
+yosys -s nd-120.ys --trace -d
+
+REM  -v 3
