Update WRF descriptions to clarify "Working Register File" across multiple files

Ronny Hansen · Ronny Hansen · commit 8f1d9c3ba917 · 2025-07-11T19:02:24.000+02:00
diff --git a/Verilog/DELILAH-CPU/CGA_WRF/circuit/CGA_WRF.v b/Verilog/DELILAH-CPU/CGA_WRF/circuit/CGA_WRF.v
@@ -1,7 +1,7 @@
 /**************************************************************************
 ** ND120 CPU, MM&M                                                       **
 ** CGA/WRF                                                               **
-** WRF: Register File                                                    **
+** WRF: Working Register File                                            **
 ** (PDF page 59)                                                         **
 **                                                                       **
 ** Last reviewed: 9-FEB-2025                                             **
diff --git a/Verilog/DELILAH-CPU/CGA_WRF/circuit/CGA_WRF_RBLOCK.v b/Verilog/DELILAH-CPU/CGA_WRF/circuit/CGA_WRF_RBLOCK.v
@@ -1,7 +1,7 @@
 /**************************************************************************
 ** ND120 CPU, MM&M                                                       **
 ** CGA/WRF/RBLOCK                                                        **
-** WRF: Register File Block                                              **
+** WRF: Working Register File                                            **
 ** (PDF page 60)                                                         **
 **                                                                       **
 ** Last reviewed: 9-FEB-2025                                             **
diff --git a/Verilog/DELILAH-CPU/CGA_WRF/circuit/CGA_WRF_RBLOCK_DR16.v b/Verilog/DELILAH-CPU/CGA_WRF/circuit/CGA_WRF_RBLOCK_DR16.v
@@ -1,7 +1,7 @@
 /**************************************************************************
 ** ND120 CPU, MM&M                                                       **
 ** CGA/WRF/RBLOCK/DR16                                                   **
-** WRF: Register File                                                    **
+** WRF: Working Register File                                            **
 ** (PDF page 64)                                                         **
 **                                                                       **
 ** Last reviewed: 1-DEC-2024                                             **
diff --git a/Verilog/DELILAH-CPU/CGA_WRF/circuit/CGA_WRF_RBLOCK_LR16.v b/Verilog/DELILAH-CPU/CGA_WRF/circuit/CGA_WRF_RBLOCK_LR16.v
@@ -1,7 +1,7 @@
 /**************************************************************************
 ** ND120 CPU, MM&M                                                       **
 ** CGA/WRF/RBLOCK/LR16                                                   **
-** WRF: Register File                                                    **
+** WRF: Working Register File                                            **
 ** (PDF page 63)                                                         **
 **                                                                       **
 ** Last reviewed: 9-FEB-2025                                             **
diff --git a/Verilog/DELILAH-CPU/CGA_WRF/circuit/CGA_WRF_RBLOCK_PREG.v b/Verilog/DELILAH-CPU/CGA_WRF/circuit/CGA_WRF_RBLOCK_PREG.v
@@ -1,7 +1,7 @@
 /**************************************************************************
 ** ND120 CPU, MM&M                                                       **
 ** CGA/WRF/RBLOCK/PREG                                                   **
-** WRF: Register File                                                    **
+** WRF: Working Register File                                            **
 ** (PDF page 62)                                                         **
 **                                                                       **
 ** Last reviewed: 9-FEB-2025                                             **
diff --git a/Verilog/DELILAH-CPU/CGA_WRF/circuit/CGA_WRF_RBLOCK_SEL16.v b/Verilog/DELILAH-CPU/CGA_WRF/circuit/CGA_WRF_RBLOCK_SEL16.v
@@ -1,7 +1,7 @@
 /**************************************************************************
 ** ND120 CPU, MM&M                                                       **
 ** CGA/WRF/RBLOCK/SEL16                                                  **
-** WRF: Register File                                                    **
+** WRF: Working Register File                                            **
 ** (PDF page 61)                                                         **
 **                                                                       **
 ** Last reviewed: 09-NOV-2024                                            **
