fxps7400_reg.c

/**
  ******************************************************************************
  * @file    fxps7400_reg.c
  * @author  Sensors Software Solution Team
  * @brief   FXPS7400 driver file
  ******************************************************************************
  * @attention
  *
  * Copyright (c) 2026 STMicroelectronics.
  * All rights reserved.
  *
  * This software is licensed under terms that can be found in the LICENSE file
  * in the root directory of this software component.
  * If no LICENSE file comes with this software, it is provided AS-IS.
  *
  ******************************************************************************
  */

//-----------------------------------------------------------------------
// Includes
//-----------------------------------------------------------------------
#include "fxps7400_reg.h"


//-----------------------------------------------------------------------
// Global Variables
//-----------------------------------------------------------------------
//fxps7400 fixed self test register setting vs expected value table
const fxps7400_st_t fixed_st[] = {{FXPS7400_DSP_CFG_U5_STL_CTRL_INHIBIT_SNS_DATA_X_WRITE0, 0x0},
                                  {FXPS7400_DSP_CFG_U5_STL_CTRL_INHIBIT_SNS_DATA_X_WRITE1, 0xAAAA},
                                  {FXPS7400_DSP_CFG_U5_STL_CTRL_INHIBIT_SNS_DATA_X_WRITE2, 0x5555},
                                  {FXPS7400_DSP_CFG_U5_STL_CTRL_INHIBIT_SNS_DATA_X_WRITE3, 0xFFFF}};

//fxps7400 digital self test  register setting vs expected value table
const fxps7400_st_t digital_st[] = {{FXPS7400_DSP_CFG_U5_STL_CTRL_DIGITAL_SELF_TEST0, 0x8171},
                                    {FXPS7400_DSP_CFG_U5_STL_CTRL_DIGITAL_SELF_TEST1, 0x6C95},
                                    {FXPS7400_DSP_CFG_U5_STL_CTRL_DIGITAL_SELF_TEST2, 0x807A},
                                    {FXPS7400_DSP_CFG_U5_STL_CTRL_DIGITAL_SELF_TEST3, 0x78AC}};

// fxps7400 part information table
const fxps7400_part_table_t part_tbl = {0x40, 28990, 14};
fxps7400_driver_t fxpsdev;


int32_t fxps7400_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
                            uint8_t *data, uint16_t len)
{
  int32_t ret;

  if (ctx == NULL || ctx->read_reg == NULL)
  {
    return FXPS7400_INVALIDPARAM_ERR;
  }

  ret = ctx->read_reg(ctx->handle, reg, data, len);

  return ret;
}


int32_t fxps7400_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
                             const uint8_t *data, uint16_t len)
{
  int32_t ret;

  if (ctx == NULL || ctx->write_reg == NULL)
  {
    return FXPS7400_INVALIDPARAM_ERR;
  }

  ret = ctx->write_reg(ctx->handle, reg, data, len);

  return ret;
}


int32_t fxps7400_device_id_get(stmdev_ctx_t *ctx, uint8_t *id)
{
  if (id == NULL)
  {
    return FXPS7400_INVALIDPARAM_ERR;
  }
  
  return fxps7400_read_reg(ctx, FXPS7400_WHO_AM_I, id, 1);
}


int32_t fxps7400_read_region(stmdev_ctx_t *ctx, uint16_t address, uint8_t *pReadBuffer)
{
  int32_t ret = FXPS7400_SUCCESS;

  if((NULL == pReadBuffer))
  {
    return FXPS7400_INVALIDPARAM_ERR;
  }

  if(address >= 0xA0)
  {
    ret = fxps7400_load_region(ctx, (address & 0xF0));
    if(ret != FXPS7400_SUCCESS){
      return ret;
    }
  }
  ret += fxps7400_read_reg(ctx, address, pReadBuffer, 1);

  return ret;
}


int32_t fxps7400_write_region(stmdev_ctx_t *ctx, uint16_t address, uint8_t *pWriteBuffer)
{
  int32_t ret = FXPS7400_SUCCESS;

  if((NULL == pWriteBuffer))
  {
    return FXPS7400_INVALIDPARAM_ERR;
  }

  if(address >= 0xA0)
  {
    ret = fxps7400_load_region(ctx, (address & 0xF0));
    if(ret != FXPS7400_SUCCESS)
	{
      return ret;
    }
  }
  ret += fxps7400_write_reg(ctx, address, pWriteBuffer, 1);
  
  return ret;
}


int32_t fxps7400_get_pressure_raw(stmdev_ctx_t *ctx, uint16_t *pPressure)
{
  int32_t ret;
  int16_t raw_pressure = 0;
  uint8_t buff[2] = {0};  //FXPS7400_DATA_SIZE

  if (pPressure == NULL)
  {
    return FXPS7400_INVALIDPARAM_ERR;
  }
  
  ret = fxps7400_read_reg(ctx, FXPS7400_SNSDATA0_L, buff, 2);
  raw_pressure = ((int16_t)(buff[1]<< 8) | buff[0]);

  *pPressure = raw_pressure;

  return ret;
}


int32_t fxps7400_get_temperature_raw(stmdev_ctx_t *ctx, uint8_t *pTemp)
{
  int32_t ret;
  uint8_t raw_temp = 0;
  
  if (pTemp == NULL)
  {
    return FXPS7400_INVALIDPARAM_ERR;
  }
  
  ret = fxps7400_read_reg(ctx, FXPS7400_TEMPERATURE, &raw_temp, 1);

  *pTemp = raw_temp;

  return ret;
}


int32_t fxps7400_startup_self_test(stmdev_ctx_t *ctx, fxps7400_st_test_type_t type, fxps7400_st_test_t testNo, uint8_t delay)
{
  int32_t ret;
  uint8_t regSet = 0;
  uint16_t sens_16_data = 0, sens_16_expected = 0;
  uint8_t sens_data[2] = {0};

  fxps7400_dsp_stat_t dsp_status = {0};
  fxps7400_dsp_cfg_u5_t reg;

  uint8_t retry  = 10;
  if(FXPS7400_COMMON_MODE_ST == type)
  {
    reg.w = FXPS7400_DSP_CFG_U5_STL_CTRL_P_CELL_MODE_VERIFICATION;
    ret = fxps7400_write_reg(ctx, FXPS7400_DSP_CFG_U5, (uint8_t*)&reg, 1);
    ctx->mdelay(delay);

    reg.w = FXPS7400_DSP_CFG_U5_STL_CTRL_NORMAL_SIGNAL;
    ret += fxps7400_write_reg(ctx, FXPS7400_DSP_CFG_U5, (uint8_t*)&reg, 1);
    ctx->mdelay(delay);

    ret += fxps7400_read_reg(ctx, FXPS7400_DSP_STAT, (uint8_t*)&dsp_status, 1);
    while(dsp_status.b.st_active && retry--)
    {
      ctx->mdelay(delay);
      ret += fxps7400_read_reg(ctx, FXPS7400_DSP_STAT, (uint8_t*)&dsp_status, 1);
    }

    if (ret != 0)
    {
      return ret;
    }

    if(dsp_status.b.st_active || dsp_status.b.st_error)
    {
      ret = FXPS7400_ST_FAILED;
    }

  }
  else
  {
    if(FXPS7400_FIXED_ST == type)
    {
      regSet = fixed_st[testNo].regVal;
      sens_16_expected = fixed_st[testNo].expected;
    }
    else
    {
      regSet = digital_st[testNo].regVal;
      sens_16_expected = digital_st[testNo].expected;
    }

    // Enable the self test
    ret = fxps7400_write_reg(ctx, FXPS7400_DSP_CFG_U5, (uint8_t*)&regSet, 1);
    ctx->mdelay(delay);

    ret += fxps7400_read_reg(ctx, FXPS7400_SNSDATA0_L, sens_data, 2);
    sens_16_data = ((int16_t)(sens_data[1]<< 8) | sens_data[0]);

    if (ret != 0)
    {
      return ret;
    }

    if(sens_16_data != sens_16_expected)
    {
      ret = FXPS7400_ST_FAILED;
    }

    //disable the self test
    reg.w = 0;
    ret += fxps7400_write_reg(ctx, FXPS7400_DSP_CFG_U5, (uint8_t*)&reg, 1);
  }

  return ret;
}


uint8_t fxps7400_calculate_crc(fxps7400_crc_param_t *pCrcSettings, uint32_t value)
{
  uint16_t i;
  uint64_t xor;
  uint64_t mask;
  uint64_t remainder;

  if (pCrcSettings == NULL)
  {
    return FXPS7400_INVALIDPARAM_ERR;
  }
  
  mask = ((~(uint64_t)0) >> (32 - pCrcSettings->dataLength)) - ((uint64_t)(((uint64_t)1) << pCrcSettings->crcLength) - 1);
  value = (value >> pCrcSettings->dataBitStart) & ((uint32_t)(((uint64_t)1) << pCrcSettings->dataLength) - 1);

  remainder = (uint64_t)(((((uint64_t)value)) | (((uint64_t)pCrcSettings->initialValue) << (pCrcSettings->dataLength))) & mask);
  xor = ((uint64_t)pCrcSettings->polynomial) << (pCrcSettings->dataLength - 1) ;

  for (i = (uint16_t) (((uint16_t)pCrcSettings->dataLength) + ((uint16_t)pCrcSettings->crcLength)); i > 0; i--)
  {
    if (((remainder >> (i - 1)) & 0x01) != 0)
    {
      remainder ^= xor;
    }
    xor >>= 1;
  
    if ((remainder & mask) == 0)
    {
      break;
    }
  }
  
  return (uint8_t)(remainder & (uint8_t)((uint64_t)(((uint64_t)1) << pCrcSettings->crcLength) - 1));
}


bool fxps7400_crc_check(uint8_t crc, fxps7400_crc_param_t *pCrcSettings,uint32_t value)
{
  if (pCrcSettings == NULL)
  {
    return FXPS7400_INVALIDPARAM_ERR;
  }
  
  crc &= (1<< pCrcSettings->crcLength) - 1;
  return crc == fxps7400_calculate_crc(pCrcSettings,value);
}


int32_t fxps7400_load_region(stmdev_ctx_t *ctx, uint8_t region)
{
  int32_t ret;
  uint8_t retry = CONFIG_RETRY;
  fxps7400_uf_region_w_t w_reg;
  fxps7400_uf_region_r_t r_reg;

  w_reg.w = region;

  // Read the part number information
  ret = fxps7400_write_reg(ctx, FXPS7400_UF_REGION_W, (uint8_t*)&w_reg, 1);

  while(retry--)
  {
    ret += fxps7400_read_reg(ctx, FXPS7400_UF_REGION_R, (uint8_t*)&r_reg, 1);
    // validated
    if(region == (uint8_t)r_reg.w){
      break;
    }
    else if (retry == 0 ){
      return FXPS7400_REGION_ERROR;
    }
  }

  return ret;
}


int32_t fxps7400_devstat_get(stmdev_ctx_t *ctx, fxps7400_devstat_t *status)
{
  int32_t ret;
  fxps7400_devstat_t reg;

  if (status == NULL)
  {
    return FXPS7400_INVALIDPARAM_ERR;
  }
  
  ret = fxps7400_read_reg(ctx, FXPS7400_DEVSTAT, (uint8_t*)&reg, 1);

  *status = reg;

  return ret;
}


int32_t fxps7400_devstat1_get(stmdev_ctx_t *ctx, fxps7400_devstat1_t *status)
{
  int32_t ret;
  fxps7400_devstat1_t reg;

  if (status == NULL)
  {
    return FXPS7400_INVALIDPARAM_ERR;
  }

  ret = fxps7400_read_reg(ctx, FXPS7400_DEVSTAT1, (uint8_t*)&reg, 1);

  *status = reg;

  return ret;
}


int32_t fxps7400_devstat2_get(stmdev_ctx_t *ctx, fxps7400_devstat2_t *status)
{
  int32_t ret;
  fxps7400_devstat2_t reg;

  if (status == NULL)
  {
    return FXPS7400_INVALIDPARAM_ERR;
  }
  
  ret = fxps7400_read_reg(ctx, FXPS7400_DEVSTAT2, (uint8_t*)&reg, 1);

  *status = reg;

  return ret;
}


int32_t fxps7400_devstat3_get(stmdev_ctx_t *ctx, fxps7400_devstat3_t *status)
{
  int32_t ret;
  fxps7400_devstat3_t reg;

  if (status == NULL)
  {
    return FXPS7400_INVALIDPARAM_ERR;
  }
  
  ret = fxps7400_read_reg(ctx, FXPS7400_DEVSTAT3, (uint8_t*)&reg, 1);

  *status = reg;

  return ret;
}


int32_t fxps7400_dsp_stat_get(stmdev_ctx_t *ctx, fxps7400_dsp_stat_t *status)
{
  int32_t ret;
  fxps7400_dsp_stat_t reg;

  if (status == NULL)
  {
    return FXPS7400_INVALIDPARAM_ERR;
  }
  
  ret = fxps7400_read_reg(ctx, FXPS7400_DSP_STAT, (uint8_t*)&reg, 1);

  *status = reg;

  return ret;
}


int32_t fxps7400_dev_lock_set(stmdev_ctx_t *ctx)
{
  int32_t ret;
  fxps7400_devlock_wr_t reg;

  ret = fxps7400_read_reg(ctx, FXPS7400_DEVLOCK_WR, (uint8_t*)&reg, 1);
  reg.b.endinit = FXPS7400_SETB;

  ret += fxps7400_write_reg(ctx, FXPS7400_DEVLOCK_WR, (uint8_t*)&reg, 1);

  return ret;
}


int32_t fxps7400_reset(stmdev_ctx_t *ctx)
{
  int32_t ret = 0;
  fxps7400_devstat_t reg;

  /* Ignore the first 4 Reads of device status (dummy). */
  for (uint8_t i=0; i<4; i++)
  {
    ret += fxps7400_read_reg(ctx, FXPS7400_DEVSTAT, (uint8_t*)&reg, 1);
  }

  ret += fxps7400_write_reg(ctx, FXPS7400_DEVLOCK_WR,
    (uint8_t[]){ FXPS7400_DEVLOCK_WR_RESET00 }, 1); /* First element in the reset sequence. */
  ret += fxps7400_write_reg(ctx, FXPS7400_DEVLOCK_WR,
    (uint8_t[]){ FXPS7400_DEVLOCK_WR_RESET11 }, 1); /* Second element in the reset sequence. */
  ret += fxps7400_write_reg(ctx, FXPS7400_DEVLOCK_WR,
    (uint8_t[]){ FXPS7400_DEVLOCK_WR_RESET01 }, 1); /* Final element in the reset sequence. */

  ret += fxps7400_read_reg(ctx, FXPS7400_DEVSTAT, (uint8_t*)&reg, 1);

  if (ret != 0)
  {
    return ret;
  }

  if (!reg.b.devres)
  {
    ret = FXPS7400_NOT_RESET;
  }

  return ret;
}


int32_t fxps7400_supply_error_mode(stmdev_ctx_t *ctx, bool val)
{
  int32_t ret;
  fxps7400_devlock_wr_t reg;

  ret = fxps7400_read_reg(ctx, FXPS7400_DEVLOCK_WR, (uint8_t*)&reg, 1);

  reg.b.sup_err_dis = val; /* SET or RESET */
  ret += fxps7400_write_reg(ctx, FXPS7400_DEVLOCK_WR, (uint8_t*)&reg, 1);

  return ret;
}


int32_t fxps7400_user_i2c_address_set(stmdev_ctx_t *ctx, fxps7400_i2c_address_t addr)
{
  int32_t ret;

  if (addr > 0 && addr <=127)
    ret = fxps7400_write_reg(ctx, FXPS7400_I2C_ADDRESS, (uint8_t*)&addr, 1);
  else
    ret = FXPS7400_INVALID_I2C_ADDR;

  return ret;
}


int32_t fxps7400_user_i2c_address_get(stmdev_ctx_t *ctx, fxps7400_i2c_address_t *addr)
{
  int32_t ret;
  fxps7400_i2c_address_t val;

  if (addr == NULL)
  {
    return FXPS7400_INVALIDPARAM_ERR;
  }
  
  ret = fxps7400_read_reg(ctx, FXPS7400_I2C_ADDRESS, (uint8_t*)&val, 1);

  /* Current I2C Address */
  if (val == 0)
    *addr = 0x60; //default I2C address
  else
    *addr = val; //actual I2C Address.

  return ret;
}


int32_t fxps7400_lpf_set(stmdev_ctx_t *ctx, lpf_type_t lpf)
{
  int32_t ret;
  fxps7400_dsp_cfg_u1_t reg;

  ret = fxps7400_read_reg(ctx, FXPS7400_DSP_CFG_U1, (uint8_t *)&reg, 1);
  if (ret != 0)
  {
    return ret;
  }
  reg.b.lpf = (uint8_t)lpf;
  ret = fxps7400_write_reg(ctx, FXPS7400_DSP_CFG_U1, (uint8_t *)&reg, 1);

  return ret;
}


int32_t fxps7400_lpf_get(stmdev_ctx_t *ctx, lpf_type_t *lpf)
{
  int32_t ret;
  fxps7400_dsp_cfg_u1_t reg;

  if (lpf == NULL)
  {
    return FXPS7400_INVALIDPARAM_ERR;
  }
  
  ret = fxps7400_read_reg(ctx, FXPS7400_DSP_CFG_U1, (uint8_t *)&reg, 1);
  if (ret != 0)
  {
    return ret;
  }

  switch (reg.b.lpf)
  {
  case LPFTYPE_800HZ_4POLE:
    *lpf = LPFTYPE_800HZ_4POLE;
    break;
  case LPFTYPE_1000HZ_4POLE:
    *lpf = LPFTYPE_1000HZ_4POLE;
    break;
  default:
    ret = FXPS7400_WRONG_FILTER;
    break;
  }

  return ret;
}


int32_t fxps7400_datatype0_set(stmdev_ctx_t *ctx, datatype_type_t data0)
{
  int32_t ret;
  fxps7400_dsp_cfg_u3_t reg;

  ret = fxps7400_read_reg(ctx, FXPS7400_DSP_CFG_U3, (uint8_t *)&reg, 1);
  if (ret != 0)
  {
    return ret;
  }

  reg.b.datatype0 = (uint8_t)data0;

  return fxps7400_write_reg(ctx, FXPS7400_DSP_CFG_U3, (uint8_t *)&reg, 1);
}


int32_t fxps7400_datatype0_get(stmdev_ctx_t *ctx, datatype_type_t *data0)
{
  int32_t ret;
  fxps7400_dsp_cfg_u3_t reg;

  if (data0 == NULL)
  {
    return FXPS7400_INVALIDPARAM_ERR;
  }
  
  ret = fxps7400_read_reg(ctx, FXPS7400_DSP_CFG_U3, (uint8_t *)&reg, 1);
  if (ret != 0)
  {
    return ret;
  }

  switch (reg.b.datatype0)
  {
  case DATATYPE_default:
    *data0 = DATATYPE_default; //datatype0 not set yet
    break;
  case DATATYPE_PRESSURE_ABS:
    *data0 = DATATYPE_PRESSURE_ABS;
    break;
  case DATATYPE_TEMPERATURE:
    *data0 = DATATYPE_TEMPERATURE;
    break;
  default:
    ret = FXPS7400_WRONG_DATATYPE;
    break;
  }

  return ret;
}


int32_t fxps7400_datatype1_set(stmdev_ctx_t *ctx, datatype_type_t data1)
{
  int32_t ret;
  fxps7400_dsp_cfg_u3_t reg;

  ret = fxps7400_read_reg(ctx, FXPS7400_DSP_CFG_U3, (uint8_t *)&reg, 1);
  if (ret != 0)
  {
    return ret;
  }

  reg.b.datatype1 = (uint8_t)data1;

  return fxps7400_write_reg(ctx, FXPS7400_DSP_CFG_U3, (uint8_t *)&reg, 1);
}


int32_t fxps7400_datatype1_get(stmdev_ctx_t *ctx, datatype_type_t *data1)
{
  int32_t ret;
  fxps7400_dsp_cfg_u3_t reg;

  if (data1 == NULL)
  {
    return FXPS7400_INVALIDPARAM_ERR;
  }
  
  ret = fxps7400_read_reg(ctx, FXPS7400_DSP_CFG_U3, (uint8_t *)&reg, 1);
  if (ret != 0)
  {
    return ret;
  }

  switch (reg.b.datatype1)
  {
  case DATATYPE_default:
    *data1 = DATATYPE_default;
    break;
  case DATATYPE_PRESSURE_ABS:
    *data1 = DATATYPE_PRESSURE_ABS;
    break;
  case DATATYPE_TEMPERATURE:
    *data1 = DATATYPE_TEMPERATURE;
    break;
  default:
    ret = FXPS7400_WRONG_DATATYPE;
    break;
  }

  return ret;
}


int32_t fxps7400_threshold_high_set(stmdev_ctx_t *ctx, float high)
{
  int32_t ret;
  uint16_t raw;
  uint8_t lval, hval;

  raw = fxps7400_pressure_kpa_to_raw(high);
  hval = (uint8_t)((raw >> 8) & 0xFF);
  lval = (uint8_t)(raw & 0xFF);

  ret = fxps7400_write_reg(ctx, FXPS7400_P_INT_HI_L, (uint8_t *)&lval, 1);
  ret += fxps7400_write_reg(ctx, FXPS7400_P_INT_HI_H, (uint8_t *)&hval, 1);

  return ret;
}


int32_t fxps7400_threshold_low_set(stmdev_ctx_t *ctx, float low)
{
  int32_t ret;
  uint16_t raw;
  uint8_t lval, hval;

  raw = fxps7400_pressure_kpa_to_raw(low);
  hval = (uint8_t)((raw >> 8) & 0xFF);
  lval = (uint8_t)(raw & 0xFF);

  ret = fxps7400_write_reg(ctx, FXPS7400_P_INT_LO_L, (uint8_t *)&lval, 1);
  ret += fxps7400_write_reg(ctx, FXPS7400_P_INT_LO_H, (uint8_t *)&hval, 1);

  return ret;
}


int32_t fxps7400_int_out_mode(stmdev_ctx_t *ctx, int_out_type_t mode)
{
  fxps7400_dsp_cfg_u4_t reg;
  reg.b.int_out = (uint8_t)mode;

  return fxps7400_write_reg(ctx, FXPS7400_DSP_CFG_U4, (uint8_t *)&reg, 1);
}


int32_t fxps7400_int_pulse_stretch_set(stmdev_ctx_t *ctx, int_ps_type_t ps)
{
  fxps7400_int_cfg_t reg;
  reg.b.int_ps = (uint8_t)ps;

  return fxps7400_write_reg(ctx, FXPS7400_INT_CFG, (uint8_t *)&reg, 1);
}


int32_t fxps7400_int_polarity_mode(stmdev_ctx_t *ctx, int_polarity_type_t mode)
{
  fxps7400_int_cfg_t reg;
  reg.b.int_polarity = (uint8_t)mode;

  return fxps7400_write_reg(ctx, FXPS7400_INT_CFG, (uint8_t *)&reg, 1);
}


int32_t fxps7400_sensor_timestamp_get(stmdev_ctx_t *ctx, uint8_t *ts)
{
  if (ts == NULL)
  {
    return FXPS7400_INVALIDPARAM_ERR;
  }

  return fxps7400_read_reg(ctx, FXPS7400_SNSDATA0_TIME0, ts, FXPS7400_TIMESTAMP_SIZE);
}


int32_t fxps7400_region_c_get(stmdev_ctx_t *ctx, fxps7400_regionc_t *val)
{
  int32_t ret;
  fxps7400_regionc_t regc;

  if (val == NULL)
  {
    return FXPS7400_INVALIDPARAM_ERR;
  }
  
  /* Load Region C allows user to read trace-ability registers located
   * in the address range: 0xC0 to 0xCF */
  ret = fxps7400_load_region(ctx, CONFIG_C_REGISTERS);
  if(ret != FXPS7400_SUCCESS){
    return ret;
  }

  ret += fxps7400_read_reg(ctx, FXPS7400_ICTYPEID, (uint8_t *)&regc.ic_type_id, 1);
  ret += fxps7400_read_reg(ctx, FXPS7400_ICREVID, (uint8_t *)&regc.ic_rev_id, 1);
  ret += fxps7400_read_reg(ctx, FXPS7400_ICMFGID, (uint8_t *)&regc.ic_mfg_id, 1);
  ret += fxps7400_read_reg(ctx, FXPS7400_PN0, (uint8_t *)&regc.PN0, 1);
  ret += fxps7400_read_reg(ctx, FXPS7400_PN1, (uint8_t *)&regc.PN1, 1);
  ret += fxps7400_read_reg(ctx, FXPS7400_SN0, regc.dev_sn, 5);
  ret += fxps7400_read_reg(ctx, FXPS7400_ASICWFR, (uint8_t *)&regc.asic_wfr, 1);
  ret += fxps7400_read_reg(ctx, FXPS7400_ASICWFR_X, (uint8_t *)&regc.asic_wfr_x, 1);
  ret += fxps7400_read_reg(ctx, FXPS7400_ASICWFR_Y, (uint8_t *)&regc.asic_wfr_y, 1);

  *val = regc;

  return ret;
}


int32_t fxps7400_region_d_get(stmdev_ctx_t *ctx, fxps7400_regiond_t *val)
{
  int32_t ret;
  fxps7400_regiond_t regd;

  if (val == NULL)
  {
    return FXPS7400_INVALIDPARAM_ERR;
  }

  /* Load Region D allows user to read trace-ability registers located
  * in the address range: 0xD0 to 0xDF */
  ret = fxps7400_load_region(ctx, CONFIG_D_REGISTERS);
  if(ret != FXPS7400_SUCCESS){
    return ret;
  }

  ret += fxps7400_read_reg(ctx, FXPS7400_ASICWLOT_L, regd.wlot, 2);
  regd.asic_wlot = (regd.wlot[1]<<8) | regd.wlot[0];
  *val = regd;

  return ret;
}


float fxps7400_pressure_raw_to_kpa(uint16_t pressure_raw)
{
  return (float )((pressure_raw - fxpsdev.pressureOffset) / fxpsdev.pressureSens);
}


uint16_t fxps7400_pressure_kpa_to_raw(float pressure_kpa)
{
  return (uint16_t)((pressure_kpa * fxpsdev.pressureSens) + fxpsdev.pressureOffset);
}


int8_t fxps7400_temp_raw_to_degc(int8_t temperature)
{
  return (int8_t )((temperature - FXPS7400_TEMP_OFFSET) / FXPS7400_TEMP_SEN);
}