GPDMA DMA state not reset when using negative block repeat address increments

[samuelpowell]

stm32u5xx-hal-driver/Src/stm32u5xx_hal_dma.c

Line 1073 in 38f1a11

if (hdma->Instance->CBR1 == 0U)

At the end of a DMA transfer the source and destination block repeat sign is unchanged, hence bits 30 and 31 of the GPDMA BR1 register may be set at the end of the transfer. In this case, the test will fail and the HAL DMA state will not return to ready, despite completion.

[MKISTM]

Hello @samuelpowell,

Thank you for your report, could you please share your use case, specify which example from the repository you used, configuration or scenario where you encountered this issue?

This will help us to reproduce this issue, understand and address it better.

BR,
Mohamed Chaker.

[MKISTM]

Hello @samuelpowell,

I hope you are doing well. Do you have any updates, please? We need to clarify this issue.

BR,
Mohamed Chaker.

[samuelpowell]

Hello @MKISTM

I understand if you are unable to examine this without an MWE, but I am not in a position to provide that at present. I can give a little more detail though.

Consider the case that a 2D DMA transfer has been configured (perhaps via CubeMX) and set up using the HAL library, e.g.,

    /* SPI2 DMA Init */
    /* GPDMA1_REQUEST_SPI2_RX Init */
    handle_GPDMA1_Channel12.Instance = GPDMA1_Channel12;
    handle_GPDMA1_Channel12.Init.Request = GPDMA1_REQUEST_SPI2_RX;
    handle_GPDMA1_Channel12.Init.BlkHWRequest = DMA_BREQ_SINGLE_BURST;
    handle_GPDMA1_Channel12.Init.Direction = DMA_PERIPH_TO_MEMORY;
    handle_GPDMA1_Channel12.Init.SrcInc = DMA_SINC_FIXED;
    handle_GPDMA1_Channel12.Init.DestInc = DMA_DINC_INCREMENTED;
    handle_GPDMA1_Channel12.Init.SrcDataWidth = DMA_SRC_DATAWIDTH_WORD;
    handle_GPDMA1_Channel12.Init.DestDataWidth = DMA_DEST_DATAWIDTH_WORD;
    handle_GPDMA1_Channel12.Init.Priority = DMA_LOW_PRIORITY_MID_WEIGHT;
    handle_GPDMA1_Channel12.Init.SrcBurstLength = 1;
    handle_GPDMA1_Channel12.Init.DestBurstLength = 1;
    handle_GPDMA1_Channel12.Init.TransferAllocatedPort = DMA_SRC_ALLOCATED_PORT0|DMA_DEST_ALLOCATED_PORT1;
    handle_GPDMA1_Channel12.Init.TransferEventMode = DMA_TCEM_BLOCK_TRANSFER;
    handle_GPDMA1_Channel12.Init.Mode = DMA_NORMAL;
    if (HAL_DMA_Init(&handle_GPDMA1_Channel12) != HAL_OK)
    {
      Error_Handler();
    }

    RepeatBlockConfig.RepeatCount = 16;
    RepeatBlockConfig.SrcAddrOffset = 0;
    RepeatBlockConfig.DestAddrOffset = 16;
    RepeatBlockConfig.BlkSrcAddrOffset = 0;
    RepeatBlockConfig.BlkDestAddrOffset = -255;
    if (HAL_DMAEx_ConfigRepeatBlock(&handle_GPDMA1_Channel12, &RepeatBlockConfig) != HAL_OK)
    {
      Error_Handler();
    }

The exact offsets are unimportant, but if either the block source or destination offsets are negative, register BR1 will have bits 31 or 32 set (to signify the negative offset). This value is not cleared by hardware at the end of transfer, but the logic quoted in my original post checks that the entire register is zero to confirm the completion of a normal transfer.

I note that there are other areas of the HAL that do not work with 2D DMA (many functions overwrite the DMA data block length register will the full transfer size, rather than the block transfer size), so it may be that the HAL is not intended to be compatible with the 2D addressing modes. I did not see this documented however.

[MKISTM]

Hello @samuelpowell,

Thank you for your clarification, this point will be tracked internally.

BR,
Mohamed Chaker.

[MKISTM]

ST Internal Reference: 225445