What is the maximum configurable SD card clock frequency for the Jetson Nano?

[ZXD990129]

Hello,

I am working with an NVIDIA Jetson Nano and need to optimize the SD card read/write performance. My carrier board's documentation states:

"We provide SD card function on carrier board, which supports CLK Frequency 48MHz. Increasing CLK by yourself might cause certificates (such as CE/FCC) failure!"

While I understand the certification warning, I would like to know the technical limit for my development purposes.

Could you please clarify what the highest stable SD card clock frequency is that can be configured in the device tree or kernel parameters for the Jetson Nano? Is 48 MHz the absolute maximum supported by the hardware, or can it be driven higher, such as 50 MHz or 200 MHz (High-Speed mode), under specific conditions?

Any insights into the relevant device tree (sdc1) node or kernel driver that controls this would be greatly appreciated.

Thank you.

[baorepo]

@ZXD990129
https://github.com/OE4T/linux-tegra-4.9/tree/oe4t-patches-l4t-r32.7.4/nvidia/platform/t210/porg/kernel-dts , Based on the kernel source path, here are the specific steps and key information to find the maximum SD card clock frequency for Jetson Nano:

1. Locate Key Device Tree Files

In the arch/arm64/boot/dts/nvidia/ directory, focus on the following files:

• tegra210-p3448-0000-p3449-0000-a00.dts (Jetson Nano A02 version)
• tegra210-p3448-0002-p3449-0002-a00.dts (Jetson Nano 2GB version)
• tegra210.dtsi (base SoC definition file)

2. Find the SD card controller node

Search for the following key nodes in the files mentioned above:

sdhci@700b0000 {  // SD card controller main node
    compatible = "nvidia,tegra210-sdhci";
    ...
max-frequency = <48000000>;  // Default 48MHz configuration
...
};

3. Key Configuration Analysis

The basic definition is found in tegra210.dtsi:

sdhci@700b0000 {
compatible = "nvidia,tegra210-sdhci";
reg = <0x0 0x700b0000 0x0 0x200>;
interrupts = <0 14 0x04>;
clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;
resets = <&tegra_car 14>;
reset-names = "sdhci";
pinctrl-names = "default", "sdmmc-3v3", "sdmmc-1v8";
pinctrl-0 = <&sdmmc1_default>;
pinctrl-1 = <&sdmmc1_3v3>;
pinctrl-2 = <&sdmmc1_1v8>;
nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
max-frequency = <208000000>;  // The theoretical maximum supported by hardware is 208MHz
...
};

4. Important Findings

1. Hardware Theoretical Limit: The Tegra210 SDHCI controller hardware supports a maximum clock frequency of 208MHz
2. Default Configuration Limitation: In the Jetson Nano board-level device tree, it is typically set to 48MHz:

   &sdhci@700b0000 {
       status = "okay";
max-frequency = <48000000>;  // Carrier board default limitation
...
};

5.High-Speed Mode Support: The controller supports UHS-I SDR104 mode (up to 208MHz), but requires:

• SD card support for UHS-I