Layout versus schematic (LVS)

[joamatab]

As circuits become more complex is important to check that your design intent matches the produced layout

What are your plans for LVS?

We just added schematic driven layout in gdsfactory and netlist extraction and we were wondering the best way to compare both. See issue

i was wondering if this is something that you also plan on implementing in SiEPIC tools

[lukasc-ubc]

Hi @joamatab ,

Without a schematic tool in KLayout, the only thing we can do is extract the netlist and run simulations.

That said, from a netlist you can create a schematic in Lumerical INTERCONNECT.

In principle, one could create a schematic in INTERCONNECT first, then compare it to the netlist extracted from the layout.

We had some efforts on creating a schematic driven layout from INTERCONNECT, but it is not complete.

[joamatab]

SDL from interconnect sounds good

We also have a pure python SDL flow

https://gdsfactory.github.io/gdsfactory/sdl.html