info.yaml

# Tiny Tapeout project information
project:
  title:        "8-Bit CPU"                                                   # Project title
  author:       "Siddharth Nema"                                              # Your name
  discord:      ""                                                            # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
  description:  "A basic 8-bit CPU design building off the SAP-1"             # One line description of what your project does
  language:     "Verilog"                                                     # other examples include SystemVerilog, Amaranth, VHDL, etc
  clock_hz:     50000000                                                      # Clock frequency in Hz (or 0 if not applicable)

  # How many tiles your design occupies? A single tile is about 167x108 uM.
  tiles: "1x1"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2

  # Your top module name must start with "tt_um_". Make it unique by including your github username:
  top_module:  "tt_um_control_block"

  # List your project's source files here.
  # Source files must be in ./src and you must list each source file separately, one per line.
  # Don't forget to also update `PROJECT_SOURCES` in test/Makefile.
  source_files:
    - "control_block.v"

# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
pinout:
  # Inputs
  ui[0]: "opcode_0"
  ui[1]: "opcode_1"
  ui[2]: "opcode_2"
  ui[3]: "opcode_3"
  ui[4]: ""
  ui[5]: ""
  ui[6]: ""
  ui[7]: ""

  # Outputs
  uo[0]: "controlsig_8"
  uo[1]: "controlsig_9"
  uo[2]: "controlsig_10"
  uo[3]: "controlsig_11"
  uo[4]: "controlsig_12"
  uo[5]: "controlsig_13"
  uo[6]: "controlsig_14"
  uo[7]: ""
   
   # Bidirectional pins
  uio[0]: "controlsig_0"
  uio[1]: "controlsig_1"
  uio[2]: "controlsig_2"
  uio[3]: "controlsig_3"
  uio[4]: "controlsig_4"
  uio[5]: "controlsig_5"
  uio[6]: "controlsig_6"
  uio[7]: "controlsig_7"

# Do not change!
yaml_version: 6