diff --git a/projects/bluetooth/sl_si91x_icm40627_3/.cproject b/projects/bluetooth/sl_si91x_icm40627_3/.cproject
new file mode 100644
index 0000000..3add1bb
--- /dev/null
+++ b/projects/bluetooth/sl_si91x_icm40627_3/.cproject
@@ -0,0 +1,291 @@
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\ No newline at end of file
diff --git a/projects/bluetooth/sl_si91x_icm40627_3/.pdm/uc.module.setup.CommonProjectPostBuild.com.silabs.ss.framework.project.toolchain.core.default#com.silabs.ss.tool.ide.arm.toolchain.gnu.cdt.12.2.1.20221205.gcc.slsproj b/projects/bluetooth/sl_si91x_icm40627_3/.pdm/uc.module.setup.CommonProjectPostBuild.com.silabs.ss.framework.project.toolchain.core.default#com.silabs.ss.tool.ide.arm.toolchain.gnu.cdt.12.2.1.20221205.gcc.slsproj
new file mode 100644
index 0000000..0d5e14f
--- /dev/null
+++ b/projects/bluetooth/sl_si91x_icm40627_3/.pdm/uc.module.setup.CommonProjectPostBuild.com.silabs.ss.framework.project.toolchain.core.default#com.silabs.ss.tool.ide.arm.toolchain.gnu.cdt.12.2.1.20221205.gcc.slsproj
@@ -0,0 +1,5 @@
+
+
+
+ $(commander) postbuild "$(project)/$(projectName).slpb" --parameter build_dir:"$(builddir)"
+
diff --git a/projects/bluetooth/sl_si91x_icm40627_3/.pdm/uc.module.setup.ProjectPostBuild.com.silabs.ss.framework.project.toolchain.core.default#com.silabs.ss.tool.ide.arm.toolchain.gnu.cdt.12.2.1.20221205.gcc.slsproj b/projects/bluetooth/sl_si91x_icm40627_3/.pdm/uc.module.setup.ProjectPostBuild.com.silabs.ss.framework.project.toolchain.core.default#com.silabs.ss.tool.ide.arm.toolchain.gnu.cdt.12.2.1.20221205.gcc.slsproj
new file mode 100644
index 0000000..f30d1cf
--- /dev/null
+++ b/projects/bluetooth/sl_si91x_icm40627_3/.pdm/uc.module.setup.ProjectPostBuild.com.silabs.ss.framework.project.toolchain.core.default#com.silabs.ss.tool.ide.arm.toolchain.gnu.cdt.12.2.1.20221205.gcc.slsproj
@@ -0,0 +1,2 @@
+
+
diff --git a/projects/bluetooth/sl_si91x_icm40627_3/.pdm/uc.module.setup.componentSetup.com.silabs.ss.framework.project.toolchain.core.default#com.silabs.ss.tool.ide.arm.toolchain.gnu.cdt.12.2.1.20221205.gcc.slsproj b/projects/bluetooth/sl_si91x_icm40627_3/.pdm/uc.module.setup.componentSetup.com.silabs.ss.framework.project.toolchain.core.default#com.silabs.ss.tool.ide.arm.toolchain.gnu.cdt.12.2.1.20221205.gcc.slsproj
new file mode 100644
index 0000000..d873faf
--- /dev/null
+++ b/projects/bluetooth/sl_si91x_icm40627_3/.pdm/uc.module.setup.componentSetup.com.silabs.ss.framework.project.toolchain.core.default#com.silabs.ss.tool.ide.arm.toolchain.gnu.cdt.12.2.1.20221205.gcc.slsproj
@@ -0,0 +1,504 @@
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+ resources/readme/setupdiagram.png
+ resources/readme/output1.png
+
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diff --git a/projects/bluetooth/sl_si91x_icm40627_3/.pdm/uc.module.setup.defaultSettings.com.silabs.ss.framework.project.toolchain.core.default#com.silabs.ss.tool.ide.arm.toolchain.gnu.cdt.12.2.1.20221205.gcc.slsproj b/projects/bluetooth/sl_si91x_icm40627_3/.pdm/uc.module.setup.defaultSettings.com.silabs.ss.framework.project.toolchain.core.default#com.silabs.ss.tool.ide.arm.toolchain.gnu.cdt.12.2.1.20221205.gcc.slsproj
new file mode 100644
index 0000000..e315d8d
--- /dev/null
+++ b/projects/bluetooth/sl_si91x_icm40627_3/.pdm/uc.module.setup.defaultSettings.com.silabs.ss.framework.project.toolchain.core.default#com.silabs.ss.tool.ide.arm.toolchain.gnu.cdt.12.2.1.20221205.gcc.slsproj
@@ -0,0 +1,2 @@
+
+
diff --git a/projects/bluetooth/sl_si91x_icm40627_3/.pdm/uc.module.setup.projectMetadata.com.silabs.ss.framework.project.toolchain.core.default#com.silabs.ss.tool.ide.arm.toolchain.gnu.cdt.12.2.1.20221205.gcc.slsproj b/projects/bluetooth/sl_si91x_icm40627_3/.pdm/uc.module.setup.projectMetadata.com.silabs.ss.framework.project.toolchain.core.default#com.silabs.ss.tool.ide.arm.toolchain.gnu.cdt.12.2.1.20221205.gcc.slsproj
new file mode 100644
index 0000000..801dd4e
--- /dev/null
+++ b/projects/bluetooth/sl_si91x_icm40627_3/.pdm/uc.module.setup.projectMetadata.com.silabs.ss.framework.project.toolchain.core.default#com.silabs.ss.tool.ide.arm.toolchain.gnu.cdt.12.2.1.20221205.gcc.slsproj
@@ -0,0 +1,7 @@
+
+
+
+
+
+
+
diff --git a/projects/bluetooth/sl_si91x_icm40627_3/.pdm/uc.module.setup.ucConfig.com.silabs.ss.framework.project.toolchain.core.default#com.silabs.ss.tool.ide.arm.toolchain.gnu.cdt.12.2.1.20221205.gcc.slsproj b/projects/bluetooth/sl_si91x_icm40627_3/.pdm/uc.module.setup.ucConfig.com.silabs.ss.framework.project.toolchain.core.default#com.silabs.ss.tool.ide.arm.toolchain.gnu.cdt.12.2.1.20221205.gcc.slsproj
new file mode 100644
index 0000000..93625f6
--- /dev/null
+++ b/projects/bluetooth/sl_si91x_icm40627_3/.pdm/uc.module.setup.ucConfig.com.silabs.ss.framework.project.toolchain.core.default#com.silabs.ss.tool.ide.arm.toolchain.gnu.cdt.12.2.1.20221205.gcc.slsproj
@@ -0,0 +1,19 @@
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/projects/bluetooth/sl_si91x_icm40627_3/.pdm/uc.module.setup.ucProject.com.silabs.ss.framework.project.toolchain.core.default#com.silabs.ss.tool.ide.arm.toolchain.gnu.cdt.12.2.1.20221205.gcc.slsproj b/projects/bluetooth/sl_si91x_icm40627_3/.pdm/uc.module.setup.ucProject.com.silabs.ss.framework.project.toolchain.core.default#com.silabs.ss.tool.ide.arm.toolchain.gnu.cdt.12.2.1.20221205.gcc.slsproj
new file mode 100644
index 0000000..298e135
--- /dev/null
+++ b/projects/bluetooth/sl_si91x_icm40627_3/.pdm/uc.module.setup.ucProject.com.silabs.ss.framework.project.toolchain.core.default#com.silabs.ss.tool.ide.arm.toolchain.gnu.cdt.12.2.1.20221205.gcc.slsproj
@@ -0,0 +1,8 @@
+
+
+
+
+
+
+
+
diff --git a/projects/bluetooth/sl_si91x_icm40627_3/.pdm/uc.module.setup.ucTemplate.com.silabs.ss.framework.project.toolchain.core.default#com.silabs.ss.tool.ide.arm.toolchain.gnu.cdt.12.2.1.20221205.gcc.slsproj b/projects/bluetooth/sl_si91x_icm40627_3/.pdm/uc.module.setup.ucTemplate.com.silabs.ss.framework.project.toolchain.core.default#com.silabs.ss.tool.ide.arm.toolchain.gnu.cdt.12.2.1.20221205.gcc.slsproj
new file mode 100644
index 0000000..d16e1de
--- /dev/null
+++ b/projects/bluetooth/sl_si91x_icm40627_3/.pdm/uc.module.setup.ucTemplate.com.silabs.ss.framework.project.toolchain.core.default#com.silabs.ss.tool.ide.arm.toolchain.gnu.cdt.12.2.1.20221205.gcc.slsproj
@@ -0,0 +1,13 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/projects/bluetooth/sl_si91x_icm40627_3/.project b/projects/bluetooth/sl_si91x_icm40627_3/.project
new file mode 100644
index 0000000..00f449d
--- /dev/null
+++ b/projects/bluetooth/sl_si91x_icm40627_3/.project
@@ -0,0 +1,909 @@
+
+
+ sl_si91x_icm40627_3
+
+
+
+
+
+ com.silabs.ss.framework.ide.project.sls.core.slsResourceBuilder
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.genmakebuilder
+ clean,full,incremental,
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+ full,incremental,
+
+
+
+
+
+ org.eclipse.cdt.core.cnature
+ com.silabs.ss.framework.ide.project.sls.core.SLSProjectNature
+ org.eclipse.cdt.managedbuilder.core.managedBuildNature
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+
+
+
+ simplicity_sdk_2025.6.2/platform/common/inc/sl_assert.h
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+
+
+ simplicity_sdk_2025.6.2/platform/common/inc/sl_atomic.h
+ 1
+ STUDIO_SDK_LOC/platform/common/inc/sl_atomic.h
+
+
+ simplicity_sdk_2025.6.2/platform/common/inc/sl_code_classification.h
+ 1
+ STUDIO_SDK_LOC/platform/common/inc/sl_code_classification.h
+
+
+ simplicity_sdk_2025.6.2/platform/common/inc/sl_common.h
+ 1
+ STUDIO_SDK_LOC/platform/common/inc/sl_common.h
+
+
+ simplicity_sdk_2025.6.2/platform/common/inc/sl_compiler.h
+ 1
+ STUDIO_SDK_LOC/platform/common/inc/sl_compiler.h
+
+
+ simplicity_sdk_2025.6.2/platform/common/inc/sl_core.h
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+ STUDIO_SDK_LOC/platform/common/inc/sl_core.h
+
+
+ simplicity_sdk_2025.6.2/platform/common/inc/sl_status.h
+ 1
+ STUDIO_SDK_LOC/platform/common/inc/sl_status.h
+
+
+ simplicity_sdk_2025.6.2/platform/common/inc/sli_code_classification.h
+ 1
+ STUDIO_SDK_LOC/platform/common/inc/sli_code_classification.h
+
+
+ simplicity_sdk_2025.6.2/platform/common/src/sl_assert.c
+ 1
+ STUDIO_SDK_LOC/platform/common/src/sl_assert.c
+
+
+ simplicity_sdk_2025.6.2/platform/common/src/sl_core_cortexm.c
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+ simplicity_sdk_2025.6.2/platform/common/src/sl_syscalls.c
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+
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+ STUDIO_SDK_LOC/platform/CMSIS/Core/Include/cmsis_compiler.h
+
+
+ simplicity_sdk_2025.6.2/platform/CMSIS/Core/Include/cmsis_gcc.h
+ 1
+ STUDIO_SDK_LOC/platform/CMSIS/Core/Include/cmsis_gcc.h
+
+
+ simplicity_sdk_2025.6.2/platform/CMSIS/Core/Include/cmsis_version.h
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+
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+
+ simplicity_sdk_2025.6.2/platform/service/sl_main/inc/sl_main_init_memory.h
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+
+ simplicity_sdk_2025.6.2/platform/service/sl_main/inc/sl_main_process_action.h
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+ STUDIO_SDK_LOC/platform/service/sl_main/inc/sl_main_process_action.h
+
+
+ simplicity_sdk_2025.6.2/platform/service/sl_main/src/sl_main_init.c
+ 1
+ STUDIO_SDK_LOC/platform/service/sl_main/src/sl_main_init.c
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+
+ simplicity_sdk_2025.6.2/platform/service/sl_main/src/sl_main_init_memory.c
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+
+ simplicity_sdk_2025.6.2/platform/service/sl_main/src/sl_main_process_action.c
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+
+ simplicity_sdk_2025.6.2/platform/service/sl_main/src/sli_main_init_memory.h
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+ simplicity_sdk_2025.6.2/platform/service/sleeptimer/inc/sli_sleeptimer.h
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+
+ simplicity_sdk_2025.6.2/platform/service/sleeptimer/src/sl_sleeptimer.c
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+
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+
+
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+
+ wiseconnect3_sdk_3.5.2/components/board/silabs/inc/rsi_board_configuration.h
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+ STUDIO_SDK_LOC/extension/wiseconnect/components/board/silabs/inc/rsi_board_configuration.h
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+
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+
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+
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+
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+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_udma_wrapper.h
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_ulpss_clk.h
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_ulpss_clk.h
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_bod.h
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_bod.h
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_ds_timer.h
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_ds_timer.h
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_ipmu.h
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_ipmu.h
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_pll.h
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_pll.h
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_pmu.h
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_pmu.h
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_power_save.h
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_power_save.h
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_processor_sensor.h
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_processor_sensor.h
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_reg_spi.h
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_reg_spi.h
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_retention.h
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_retention.h
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_rtc.h
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_rtc.h
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_temp_sensor.h
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_temp_sensor.h
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_time_period.h
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_time_period.h
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_ulpss_clk.h
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_ulpss_clk.h
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_wwdt.h
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_wwdt.h
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_bod.c
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_bod.c
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_ipmu.c
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_ipmu.c
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_pll.c
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_pll.c
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_rtc.c
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_rtc.c
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_temp_sensor.c
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_temp_sensor.c
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_time_period.c
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_time_period.c
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_ulpss_clk.c
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_ulpss_clk.c
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_driver_gpio.h
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_driver_gpio.h
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_adc.h
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_adc.h
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_bjt_temperature_sensor.h
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_bjt_temperature_sensor.h
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_dma.h
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_dma.h
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_driver_gpio.h
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_driver_gpio.h
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_ssi.h
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_ssi.h
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_adc.c
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_adc.c
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_bjt_temperature_sensor.c
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_bjt_temperature_sensor.c
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_dma.c
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_dma.c
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_driver_gpio.c
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_driver_gpio.c
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_ssi.c
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_ssi.c
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/inc/sl_si91x_gpio.h
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/inc/sl_si91x_gpio.h
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/inc/sl_si91x_gpio_common.h
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/inc/sl_si91x_gpio_common.h
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/inc/sl_si91x_peripheral_gpio.h
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/inc/sl_si91x_peripheral_gpio.h
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/src/sl_si91x_peripheral_gpio.c
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/src/sl_si91x_peripheral_gpio.c
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/hardware_drivers/icm40627/inc/sl_si91x_icm40627.h
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/hardware_drivers/icm40627/inc/sl_si91x_icm40627.h
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/hardware_drivers/icm40627/src/sl_si91x_icm40627.c
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/hardware_drivers/icm40627/src/sl_si91x_icm40627.c
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/service/clock_manager/inc/sl_si91x_clock_manager.h
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/service/clock_manager/inc/sl_si91x_clock_manager.h
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/service/clock_manager/src/sl_si91x_clock_manager.c
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/service/clock_manager/src/sl_si91x_clock_manager.c
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/service/sleeptimer/inc/sli_sleeptimer_hal.h
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/service/sleeptimer/inc/sli_sleeptimer_hal.h
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/service/sleeptimer/src/sl_sleeptimer_hal_si91x_sysrtc.c
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/service/sleeptimer/src/sl_sleeptimer_hal_si91x_sysrtc.c
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/core/chip/src/iPMU_prog/iPMU_dotc/ipmu_apis.c
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/core/chip/src/iPMU_prog/iPMU_dotc/ipmu_apis.c
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/core/chip/src/iPMU_prog/iPMU_dotc/rsi_system_config_917.c
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/core/chip/src/iPMU_prog/iPMU_dotc/rsi_system_config_917.c
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_Common.h
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_Common.h
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_Flash.h
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_Flash.h
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_I2C.h
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_I2C.h
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_SAI.h
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_SAI.h
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_SPI.h
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_SPI.h
+
+
+ wiseconnect3_sdk_3.5.2/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_USART.h
+ 1
+ STUDIO_SDK_LOC/extension/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_USART.h
+
+
+
diff --git a/projects/bluetooth/sl_si91x_icm40627_3/app.c b/projects/bluetooth/sl_si91x_icm40627_3/app.c
new file mode 100644
index 0000000..da9f947
--- /dev/null
+++ b/projects/bluetooth/sl_si91x_icm40627_3/app.c
@@ -0,0 +1,60 @@
+#include "app.h"
+#include "icm40627_example.h"
+#include "sl_si91x_icm40627.h"
+#include "sl_status.h"
+#include
+#include
+#include
+#include "sl_sleeptimer.h"
+#define TEMP_THRESHOLD 75.0f // °C
+#define VIB_THRESHOLD 2.0f // g RMS
+float latest_temperature = 0.0f;
+float latest_accel[3] = {0};
+float latest_gyro[3] = {0};
+static float get_vibration_level(void)
+{
+ return sqrtf(latest_accel[0]*latest_accel[0] +
+ latest_accel[1]*latest_accel[1] +
+ latest_accel[2]*latest_accel[2]);
+}
+void app_init(void)
+{
+ icm40627_example_init();
+ printf("Engine Health Monitoring Started...\n");
+}
+
+void app_process_action(void)
+{
+ sl_status_t status;
+ char status_str[16] = "NORMAL";
+ float vibration = 0.0f;
+
+ icm40627_example_process_action();
+
+ status = sl_si91x_icm40627_get_temperature_data(ssi_driver_handle, &latest_temperature);
+ if (status != SL_STATUS_OK) {
+ printf("Temperature read failed\n");
+ }
+
+ status = sl_si91x_icm40627_get_accel_data(ssi_driver_handle, latest_accel);
+ if (status != SL_STATUS_OK) {
+ printf("Accel read failed\n");
+ }
+
+ status = sl_si91x_icm40627_get_gyro_data(ssi_driver_handle, latest_gyro);
+ if (status != SL_STATUS_OK) {
+ printf("Gyro read failed\n");
+ }
+
+ vibration = get_vibration_level();
+
+ if (latest_temperature > TEMP_THRESHOLD || vibration > VIB_THRESHOLD) {
+ strcpy(status_str, "UNHEALTHY");
+ } else if (latest_temperature > (TEMP_THRESHOLD - 5) || vibration > (VIB_THRESHOLD - 0.5)) {
+ strcpy(status_str, "WARNING");
+ }
+
+ printf("Temp: %.2f °C | Vib: %.2f g | Status: %s\n",
+ latest_temperature, vibration, status_str);
+ sl_sleeptimer_delay_millisecond(3000);
+}
diff --git a/projects/bluetooth/sl_si91x_icm40627_3/app.h b/projects/bluetooth/sl_si91x_icm40627_3/app.h
new file mode 100644
index 0000000..2b13c35
--- /dev/null
+++ b/projects/bluetooth/sl_si91x_icm40627_3/app.h
@@ -0,0 +1,7 @@
+#ifndef APP_H
+#define APP_H
+
+void app_init(void);
+void app_process_action(void);
+
+#endif // APP_H
diff --git a/projects/bluetooth/sl_si91x_icm40627_3/autogen/.slc_state/.crc_config.crc b/projects/bluetooth/sl_si91x_icm40627_3/autogen/.slc_state/.crc_config.crc
new file mode 100644
index 0000000..4f0d372
--- /dev/null
+++ b/projects/bluetooth/sl_si91x_icm40627_3/autogen/.slc_state/.crc_config.crc
@@ -0,0 +1 @@
+#CRC Codes for initially generated config files -- do not modify!
\ No newline at end of file
diff --git a/projects/bluetooth/sl_si91x_icm40627_3/autogen/RTE_Components.h b/projects/bluetooth/sl_si91x_icm40627_3/autogen/RTE_Components.h
new file mode 100644
index 0000000..aa62dc4
--- /dev/null
+++ b/projects/bluetooth/sl_si91x_icm40627_3/autogen/RTE_Components.h
@@ -0,0 +1,22 @@
+// This file is autogenerated by Simplicity Configuration Tools.
+// The contents of this file will be replaced in their entirety upon regeneration.
+//
+// Source template file: RTE_Components.h.jinja
+
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+/* standard device header from emlib */
+#define CMSIS_device_header "em_device.h"
+
+/* components are auto-generated here */
+
+
+#endif /* RTE_COMPONENTS_H */
+
+/* This file is autogenerated by Simplicity Configuration Tools. */
+/* The contents of this file will be replaced in their entirety upon regeneration. */
+/* */
+/* Source template file: RTE_Components.h.jinja */
+
diff --git a/projects/bluetooth/sl_si91x_icm40627_3/autogen/gen.properties b/projects/bluetooth/sl_si91x_icm40627_3/autogen/gen.properties
new file mode 100644
index 0000000..2804010
--- /dev/null
+++ b/projects/bluetooth/sl_si91x_icm40627_3/autogen/gen.properties
@@ -0,0 +1,2 @@
+sdk=simplicity_sdk:2025.6.2
+extensions=wiseconnect3_sdk:3.5.2
\ No newline at end of file
diff --git a/projects/bluetooth/sl_si91x_icm40627_3/autogen/linkerfile_SoC.ld b/projects/bluetooth/sl_si91x_icm40627_3/autogen/linkerfile_SoC.ld
new file mode 100644
index 0000000..5f111af
--- /dev/null
+++ b/projects/bluetooth/sl_si91x_icm40627_3/autogen/linkerfile_SoC.ld
@@ -0,0 +1,187 @@
+/***************************************************************************//**
+ * GCC Linker script for Silicon Labs devices
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+
+ MEMORY
+ {
+ rom (rx) : ORIGIN = 0x8202000, LENGTH = 0x1fe000
+
+ ram (rwx) : ORIGIN = 0xc, LENGTH = 0x2fbf4
+ }
+ MEMORY
+ {
+ udma0 (rwx) : ORIGIN = 0x2fc00, LENGTH = 0x400
+ udma1 (rwx) : ORIGIN = 0x24061c00, LENGTH = 0x400
+ }
+
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ . = ALIGN(32);
+ *(EXCLUDE_FILE(*UDMA.o).text*)
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+
+
+
+
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+ *(.rodata*)
+
+ KEEP(*(.eh_fram e*))
+ } > rom
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > rom
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > rom
+ __exidx_end = .;
+ __etext = .;
+
+ __rom_start = ORIGIN(rom);
+ __rom_length = LENGTH(rom);
+
+ /* _sidata is used in code startup code */
+ _sidata = __etext;
+
+
+
+
+
+ .data :
+
+ {
+ __data_start__ = .;
+
+ /* _sdata is used in startup code */
+ _sdata = __data_start__;
+ *(.data*)
+ *UDMA.o(.text*)
+
+
+
+ /* ipmu calibration data */
+ *(.common_ipmu_ram*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ /* _edata is used in startup code */
+ _edata = __data_end__;
+ } > ram AT> rom
+
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > ram
+
+
+ .stack (NOLOAD):
+ {
+ __StackLimit = .;
+ KEEP(*(.stack*))
+ . = ALIGN(4);
+ __StackTop = .;
+ PROVIDE(__stack = __StackTop);
+ } > ram
+ .heap (COPY):
+ {
+ __HeapBase = .;
+ __end__ = .;
+ end = __end__;
+ _end = __end__;
+ KEEP(*(.heap*))
+ . = ORIGIN(ram) + LENGTH(ram);
+ __HeapLimit = .;
+ } > ram
+
+ __heap_size = __HeapLimit - __HeapBase;
+ .udma_addr0 :
+ {
+ *(.udma_addr0*)
+ } > udma0 AT> rom
+
+ .udma_addr1 :
+ {
+ *(.udma_addr1*)
+ } > udma1 AT> rom
+ /* nvm3 enable*/ /* Flash Present*/ /* littlefs_enable */ /* Flash Present */
+}
\ No newline at end of file
diff --git a/projects/bluetooth/sl_si91x_icm40627_3/autogen/sbom/cyclonedx_bom.json b/projects/bluetooth/sl_si91x_icm40627_3/autogen/sbom/cyclonedx_bom.json
new file mode 100644
index 0000000..f9d94f1
--- /dev/null
+++ b/projects/bluetooth/sl_si91x_icm40627_3/autogen/sbom/cyclonedx_bom.json
@@ -0,0 +1,872 @@
+{
+ "bomFormat" : "CycloneDX",
+ "specVersion" : "1.6",
+ "version" : 1,
+ "metadata" : {
+ "timestamp" : "2025-10-26T17:54:28Z",
+ "authors" : [ {
+ "name" : "Silicon Laboratories, Inc."
+ } ],
+ "properties" : [ {
+ "name" : "Silicon Labs Disclaimer",
+ "value" : "TERMS OF USE - SILICON LABORATORIES INC.\n(With respect to Silicon Labs software components, this Software Bill of Materials (SBOM) is based upon Silicon Labs'\nreview and analysis of the code version when released. It is provided \"AS IS\" and does not modify, change or alter\nthe terms or conditions of your use of Silicon Labs' software and/or SDKs based upon license terms and/or agreements\nassociated with this software or SDKs when distributed to you, received by you, or installed by you. Further, no\nwarranties or obligations are created by this SBOM. It is your obligation to comply with the terms of licenses\nreferenced in this SBOM.)"
+ } ]
+ },
+ "components" : [ {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2",
+ "name" : "WiSeConnect 3 SDK",
+ "version" : "3.5.2",
+ "components" : [ {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:SIWG917M111MGTBA",
+ "name" : "SIWG917M111MGTBA",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "MSLA"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:brd2605a",
+ "name" : "BRD2605A",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:si91x_memory_default_config",
+ "name" : "Default RAM Memory Configuration",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:sl_icm40627",
+ "name" : "ICM40627 6-axis Inertial Sensor (IMU)",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:sl_ssi",
+ "name" : "SSI",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:sl_ssi_instance",
+ "name" : "SSI",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:ssi_ulp_component",
+ "name" : "PM ULP SSI",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:syscalls",
+ "name" : "System Calls",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "MSLA"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:rsilib_opamp",
+ "name" : "OPAMP",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:wiseconnect_toolchain_gcc_standard",
+ "name" : "GCC Toolchain Standard Linker",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:rsilib_egpio",
+ "name" : "EGPIO",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:cmsis_usart",
+ "name" : "CMSIS USART",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Apache-2.0 AND Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:systemlevel_headers",
+ "name" : "System-Level API Headers",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:rsilib_spi",
+ "name" : "SPI",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:cmsis_driver_headers",
+ "name" : "CMSIS Driver Header Files",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Apache-2.0"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:wiseconnect_toolchain_plugin",
+ "name" : "GCC Toolchain Support",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:rsilib_aux_reference_volt_config",
+ "name" : "AUX REFERENCE VOLT",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:sl_si91x_mcu",
+ "name" : "Si91x MCU Subsystem",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "MSLA"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:systemlevel_time_period",
+ "name" : "TIME PERIOD",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:external_psram_8mb",
+ "name" : "8MB PSRAM (External)",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:sl_clock_manager",
+ "name" : "Clock Manager",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:rsilib_usart",
+ "name" : "USART",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:romdriver_udma_wrapper",
+ "name" : "ROM DRIVER UDMA WRAPPER",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:freertos_config",
+ "name" : "SL SI91X FreeRTOS Configuration",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "MIT"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:romdriver_packing",
+ "name" : "ROM DRIVER PACKING",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:romdriver_clks",
+ "name" : "ROM DRIVER CLOCK",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:systemlevel_bod",
+ "name" : "BOD",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:cmsis_udma",
+ "name" : "CMSIS UDMA",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "MSLA AND Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:cmsis_common_driver",
+ "name" : "CMSIS COMMON DRIVER",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:rsilib_udma",
+ "name" : "UDMA",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:sl_gpio_peripheral",
+ "name" : "SL GPIO Peripheral",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:romdriver_udma",
+ "name" : "ROM DRIVER UDMA",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:rsilib_dac",
+ "name" : "DAC",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:opn_config",
+ "name" : "opn config",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:systemlevel_ulpss_clk",
+ "name" : "ULPSS CLOCK",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:rsilib_adc",
+ "name" : "ADC",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:romdriver_romtable",
+ "name" : "ROM TABLE",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:systemlevel_reg_spi",
+ "name" : "REG SPI",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:romdriver_romtable_headers",
+ "name" : "ROM Table Header",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:romdriver_crc",
+ "name" : "ROM DRIVER CRC",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:rsilib_headers",
+ "name" : "RSI Peripheral Headers",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:external_flash_none",
+ "name" : "No External Flash",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:sl_dma",
+ "name" : "DMA",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:si91x_mem_config_1",
+ "name" : "MEMORY_MCU_BASIC_WIRELESS_ADVANCED",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:rsilib_userconfig",
+ "name" : "RSI User Configuration",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "MSLA"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:cmsis_spi",
+ "name" : "CMSIS SPI",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Apache-2.0"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:sl_bjt_temperature_sensor",
+ "name" : "BJT Temperature Sensor",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:cmsis_peripheral_headers",
+ "name" : "CMSIS Peripheral Header Files",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "MSLA AND Apache-2.0"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:sl_gpio",
+ "name" : "GPIO",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:systemlevel_rtc",
+ "name" : "RTC",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:systemlevel_ipmu",
+ "name" : "IPMU",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:udma_linker_config",
+ "name" : "UDMA Linker Configuration",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:board_configuration_headers",
+ "name" : "Board Configuration Header Files",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:sl_adc",
+ "name" : "ADC",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:romdriver_egpio",
+ "name" : "ROM DRIVER EGPIO",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:systemlevel_temp_sensor",
+ "name" : "TEMPERATURE SENSOR",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:si91x_device_init_nvic",
+ "name" : "NVIC Interrupt Priorities Configuration for FreeRTOS",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "MSLA"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:systemlevel_pll",
+ "name" : "PLL",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:rsilib_board",
+ "name" : "Si91x SoC Board Configurations",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "MSLA AND Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:brd2605a_config",
+ "name" : "brd2605a config",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:rsilib_clock_update",
+ "name" : "CLOCK UPDATE",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:si91x_debug",
+ "name" : "Debug Unit",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:si91x_common_flash",
+ "name" : "Common Flash Component",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:rsilib_chip",
+ "name" : "Core",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:rsilib_sysrtc",
+ "name" : "SYSRTC",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:rsilib_udma_wrapper",
+ "name" : "UDMA WRAPPER",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:si91x_stack_size_configuration",
+ "name" : "SiW91x Stack Size Configuration",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:cmsis_usart_driver",
+ "name" : "CMSIS USART DRIVER",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:sleeptimer_si91x",
+ "name" : "Sleep Timer for Si91x",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:romdriver_ulpss",
+ "name" : "ROM DRIVER ULPSS",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "wiseconnect3_sdk:3.5.2:rsilib_crc",
+ "name" : "CRC",
+ "version" : "3.5.2",
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "simplicity_sdk:2025.6.2",
+ "name" : "Simplicity SDK Suite",
+ "version" : "2025.6.2",
+ "supplier" : {
+ "name" : "Silicon Laboratories, Inc."
+ },
+ "components" : [ {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "simplicity_sdk:2025.6.2:sl_main",
+ "name" : "System Setup (sl_main)",
+ "version" : "2025.6.2",
+ "supplier" : {
+ "name" : "Silicon Laboratories, Inc."
+ },
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "simplicity_sdk:2025.6.2:sleeptimer",
+ "name" : "Sleep Timer",
+ "version" : "2025.6.2",
+ "supplier" : {
+ "name" : "Silicon Laboratories, Inc."
+ },
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "simplicity_sdk:2025.6.2:event_handler",
+ "name" : "Event Handler",
+ "version" : "2025.6.2",
+ "supplier" : {
+ "name" : "Silicon Laboratories, Inc."
+ },
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "simplicity_sdk:2025.6.2:sl_main_memory_init",
+ "name" : "sl_main Setup",
+ "version" : "2025.6.2",
+ "supplier" : {
+ "name" : "Silicon Laboratories, Inc."
+ },
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "simplicity_sdk:2025.6.2:atomic",
+ "name" : "Atomic Operations Library",
+ "version" : "2025.6.2",
+ "supplier" : {
+ "name" : "Silicon Laboratories, Inc."
+ },
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "simplicity_sdk:2025.6.2:code_classification",
+ "name" : "Code Classification",
+ "version" : "2025.6.2",
+ "supplier" : {
+ "name" : "Silicon Laboratories, Inc."
+ },
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "simplicity_sdk:2025.6.2:status",
+ "name" : "Status Codes Definitions",
+ "version" : "2025.6.2",
+ "supplier" : {
+ "name" : "Silicon Laboratories, Inc."
+ },
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "simplicity_sdk:2025.6.2:toolchain_variant_arm",
+ "name" : "Toolchain for ARM",
+ "version" : "2025.6.2",
+ "supplier" : {
+ "name" : "Silicon Laboratories, Inc."
+ },
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "simplicity_sdk:2025.6.2:sl_assert",
+ "name" : "Assert Functions",
+ "version" : "2025.6.2",
+ "supplier" : {
+ "name" : "Silicon Laboratories, Inc."
+ },
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "simplicity_sdk:2025.6.2:component_catalog",
+ "name" : "Component Catalog",
+ "version" : "2025.6.2",
+ "supplier" : {
+ "name" : "Silicon Laboratories, Inc."
+ },
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "simplicity_sdk:2025.6.2:sl_core",
+ "name" : "core",
+ "version" : "2025.6.2",
+ "supplier" : {
+ "name" : "Silicon Laboratories, Inc."
+ },
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "simplicity_sdk:2025.6.2:cmsis_core",
+ "name" : "CMSIS-Core",
+ "version" : "2025.6.2",
+ "supplier" : {
+ "name" : "Silicon Laboratories, Inc."
+ },
+ "licenses" : [ {
+ "expression" : "Apache 2.0"
+ } ],
+ "pedigree" : {
+ "ancestors" : [ {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "cmsis_core:5.8.0",
+ "name" : "CMSIS_5",
+ "version" : "5.8.0",
+ "supplier" : {
+ "name" : "ARM-software"
+ },
+ "externalReferences" : [ {
+ "type" : "website",
+ "url" : "https://github.com/ARM-software/CMSIS_5"
+ } ],
+ "purl" : "pkg:github/ARM-software/CMSIS_5@5.8.0",
+ "pedigree" : {
+ "notes" : "The CMSIS is a set of tools, APIs, frameworks, and work flows"
+ }
+ } ]
+ }
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "simplicity_sdk:2025.6.2:sl_common",
+ "name" : "Common Functions",
+ "version" : "2025.6.2",
+ "supplier" : {
+ "name" : "Silicon Laboratories, Inc."
+ },
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "simplicity_sdk:2025.6.2:sl_main_init",
+ "name" : "sl main Init",
+ "version" : "2025.6.2",
+ "supplier" : {
+ "name" : "Silicon Laboratories, Inc."
+ },
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ }, {
+ "scope" : "required",
+ "type" : "library",
+ "bom-ref" : "simplicity_sdk:2025.6.2:sl_main_process_action",
+ "name" : "sl_main Process Action",
+ "version" : "2025.6.2",
+ "supplier" : {
+ "name" : "Silicon Laboratories, Inc."
+ },
+ "licenses" : [ {
+ "expression" : "Zlib"
+ } ]
+ } ]
+ } ]
+}
\ No newline at end of file
diff --git a/projects/bluetooth/sl_si91x_icm40627_3/autogen/sbom/cyclonedx_bom.xml b/projects/bluetooth/sl_si91x_icm40627_3/autogen/sbom/cyclonedx_bom.xml
new file mode 100644
index 0000000..633b1a7
--- /dev/null
+++ b/projects/bluetooth/sl_si91x_icm40627_3/autogen/sbom/cyclonedx_bom.xml
@@ -0,0 +1,704 @@
+
+
+
+
+ 2025-10-26T17:54:28Z
+
+
+ Silicon Laboratories, Inc.
+
+
+
+
+
+ WiSeConnect 3 SDK
+ 3.5.2
+
+
+ SIWG917M111MGTBA
+ 3.5.2
+
+ MSLA
+
+
+
+ BRD2605A
+ 3.5.2
+
+ Zlib
+
+
+
+ Default RAM Memory Configuration
+ 3.5.2
+
+ Zlib
+
+
+
+ ICM40627 6-axis Inertial Sensor (IMU)
+ 3.5.2
+
+ Zlib
+
+
+
+ SSI
+ 3.5.2
+
+ Zlib
+
+
+
+ SSI
+ 3.5.2
+
+ Zlib
+
+
+
+ PM ULP SSI
+ 3.5.2
+
+ Zlib
+
+
+
+ System Calls
+ 3.5.2
+
+ MSLA
+
+
+
+ OPAMP
+ 3.5.2
+
+ Zlib
+
+
+
+ GCC Toolchain Standard Linker
+ 3.5.2
+
+ Zlib
+
+
+
+ EGPIO
+ 3.5.2
+
+ Zlib
+
+
+
+ CMSIS USART
+ 3.5.2
+
+ Apache-2.0 AND Zlib
+
+
+
+ System-Level API Headers
+ 3.5.2
+
+ Zlib
+
+
+
+ SPI
+ 3.5.2
+
+ Zlib
+
+
+
+ CMSIS Driver Header Files
+ 3.5.2
+
+ Apache-2.0
+
+
+
+ GCC Toolchain Support
+ 3.5.2
+
+ Zlib
+
+
+
+ AUX REFERENCE VOLT
+ 3.5.2
+
+ Zlib
+
+
+
+ Si91x MCU Subsystem
+ 3.5.2
+
+ MSLA
+
+
+
+ TIME PERIOD
+ 3.5.2
+
+ Zlib
+
+
+
+ 8MB PSRAM (External)
+ 3.5.2
+
+ Zlib
+
+
+
+ Clock Manager
+ 3.5.2
+
+ Zlib
+
+
+
+ USART
+ 3.5.2
+
+ Zlib
+
+
+
+ ROM DRIVER UDMA WRAPPER
+ 3.5.2
+
+ Zlib
+
+
+
+ SL SI91X FreeRTOS Configuration
+ 3.5.2
+
+ MIT
+
+
+
+ ROM DRIVER PACKING
+ 3.5.2
+
+ Zlib
+
+
+
+ ROM DRIVER CLOCK
+ 3.5.2
+
+ Zlib
+
+
+
+ BOD
+ 3.5.2
+
+ Zlib
+
+
+
+ CMSIS UDMA
+ 3.5.2
+
+ MSLA AND Zlib
+
+
+
+ CMSIS COMMON DRIVER
+ 3.5.2
+
+ Zlib
+
+
+
+ UDMA
+ 3.5.2
+
+ Zlib
+
+
+
+ SL GPIO Peripheral
+ 3.5.2
+
+ Zlib
+
+
+
+ ROM DRIVER UDMA
+ 3.5.2
+
+ Zlib
+
+
+
+ DAC
+ 3.5.2
+
+ Zlib
+
+
+
+ opn config
+ 3.5.2
+
+ Zlib
+
+
+
+ ULPSS CLOCK
+ 3.5.2
+
+ Zlib
+
+
+
+ ADC
+ 3.5.2
+
+ Zlib
+
+
+
+ ROM TABLE
+ 3.5.2
+
+ Zlib
+
+
+
+ REG SPI
+ 3.5.2
+
+ Zlib
+
+
+
+ ROM Table Header
+ 3.5.2
+
+ Zlib
+
+
+
+ ROM DRIVER CRC
+ 3.5.2
+
+ Zlib
+
+
+
+ RSI Peripheral Headers
+ 3.5.2
+
+ Zlib
+
+
+
+ No External Flash
+ 3.5.2
+
+ Zlib
+
+
+
+ DMA
+ 3.5.2
+
+ Zlib
+
+
+
+ MEMORY_MCU_BASIC_WIRELESS_ADVANCED
+ 3.5.2
+
+ Zlib
+
+
+
+ RSI User Configuration
+ 3.5.2
+
+ MSLA
+
+
+
+ CMSIS SPI
+ 3.5.2
+
+ Apache-2.0
+
+
+
+ BJT Temperature Sensor
+ 3.5.2
+
+ Zlib
+
+
+
+ CMSIS Peripheral Header Files
+ 3.5.2
+
+ MSLA AND Apache-2.0
+
+
+
+ GPIO
+ 3.5.2
+
+ Zlib
+
+
+
+ RTC
+ 3.5.2
+
+ Zlib
+
+
+
+ IPMU
+ 3.5.2
+
+ Zlib
+
+
+
+ UDMA Linker Configuration
+ 3.5.2
+
+ Zlib
+
+
+
+ Board Configuration Header Files
+ 3.5.2
+
+ Zlib
+
+
+
+ ADC
+ 3.5.2
+
+ Zlib
+
+
+
+ ROM DRIVER EGPIO
+ 3.5.2
+
+ Zlib
+
+
+
+ TEMPERATURE SENSOR
+ 3.5.2
+
+ Zlib
+
+
+
+ NVIC Interrupt Priorities Configuration for FreeRTOS
+ 3.5.2
+
+ MSLA
+
+
+
+ PLL
+ 3.5.2
+
+ Zlib
+
+
+
+ Si91x SoC Board Configurations
+ 3.5.2
+
+ MSLA AND Zlib
+
+
+
+ brd2605a config
+ 3.5.2
+
+ Zlib
+
+
+
+ CLOCK UPDATE
+ 3.5.2
+
+ Zlib
+
+
+
+ Debug Unit
+ 3.5.2
+
+ Zlib
+
+
+
+ Common Flash Component
+ 3.5.2
+
+ Zlib
+
+
+
+ Core
+ 3.5.2
+
+ Zlib
+
+
+
+ SYSRTC
+ 3.5.2
+
+ Zlib
+
+
+
+ UDMA WRAPPER
+ 3.5.2
+
+ Zlib
+
+
+
+ SiW91x Stack Size Configuration
+ 3.5.2
+
+ Zlib
+
+
+
+ CMSIS USART DRIVER
+ 3.5.2
+
+ Zlib
+
+
+
+ Sleep Timer for Si91x
+ 3.5.2
+
+ Zlib
+
+
+
+ ROM DRIVER ULPSS
+ 3.5.2
+
+ Zlib
+
+
+
+ CRC
+ 3.5.2
+
+ Zlib
+
+
+
+
+
+
+ Silicon Laboratories, Inc.
+
+ Simplicity SDK Suite
+ 2025.6.2
+
+
+ System Setup (sl_main)
+ 2025.6.2
+
+ Silicon Laboratories, Inc.
+
+
+ Zlib
+
+
+
+ Sleep Timer
+ 2025.6.2
+
+ Silicon Laboratories, Inc.
+
+
+ Zlib
+
+
+
+ Event Handler
+ 2025.6.2
+
+ Silicon Laboratories, Inc.
+
+
+ Zlib
+
+
+
+ sl_main Setup
+ 2025.6.2
+
+ Silicon Laboratories, Inc.
+
+
+ Zlib
+
+
+
+ Atomic Operations Library
+ 2025.6.2
+
+ Silicon Laboratories, Inc.
+
+
+ Zlib
+
+
+
+ Code Classification
+ 2025.6.2
+
+ Silicon Laboratories, Inc.
+
+
+ Zlib
+
+
+
+ Status Codes Definitions
+ 2025.6.2
+
+ Silicon Laboratories, Inc.
+
+
+ Zlib
+
+
+
+ Toolchain for ARM
+ 2025.6.2
+
+ Silicon Laboratories, Inc.
+
+
+ Zlib
+
+
+
+ Assert Functions
+ 2025.6.2
+
+ Silicon Laboratories, Inc.
+
+
+ Zlib
+
+
+
+ Component Catalog
+ 2025.6.2
+
+ Silicon Laboratories, Inc.
+
+
+ Zlib
+
+
+
+ core
+ 2025.6.2
+
+ Silicon Laboratories, Inc.
+
+
+ Zlib
+
+
+
+ CMSIS-Core
+ 2025.6.2
+
+ Silicon Laboratories, Inc.
+
+
+ Apache 2.0
+
+
+
+
+
+ ARM-software
+
+ CMSIS_5
+ 5.8.0
+ pkg:github/ARM-software/CMSIS_5@5.8.0
+
+ The CMSIS is a set of tools, APIs, frameworks, and work flows
+
+
+
+ https://github.com/ARM-software/CMSIS_5
+
+
+
+
+
+
+
+ Common Functions
+ 2025.6.2
+
+ Silicon Laboratories, Inc.
+
+
+ Zlib
+
+
+
+ sl main Init
+ 2025.6.2
+
+ Silicon Laboratories, Inc.
+
+
+ Zlib
+
+
+
+ sl_main Process Action
+ 2025.6.2
+
+ Silicon Laboratories, Inc.
+
+
+ Zlib
+
+
+
+
+
+
\ No newline at end of file
diff --git a/projects/bluetooth/sl_si91x_icm40627_3/autogen/sbom/spdx_bom.spdx b/projects/bluetooth/sl_si91x_icm40627_3/autogen/sbom/spdx_bom.spdx
new file mode 100644
index 0000000..169e9ea
--- /dev/null
+++ b/projects/bluetooth/sl_si91x_icm40627_3/autogen/sbom/spdx_bom.spdx
@@ -0,0 +1,1084 @@
+# TERMS OF USE - SILICON LABORATORIES INC.
+# (With respect to Silicon Labs software components, this Software Bill of Materials (SBOM) is based upon Silicon Labs'
+# review and analysis of the code version when released. It is provided "AS IS" and does not modify, change or alter
+# the terms or conditions of your use of Silicon Labs' software and/or SDKs based upon license terms and/or agreements
+# associated with this software or SDKs when distributed to you, received by you, or installed by you. Further, no
+# warranties or obligations are created by this SBOM. It is your obligation to comply with the terms of licenses
+# referenced in this SBOM.)
+SPDXVersion: SPDX-2.3
+DataLicense: CC0-1.0
+SPDXID: SPDXRef-DOCUMENT
+DocumentName: Silicon-Laboratories
+DocumentNamespace: https://silabs.com
+
+## Creation Information
+Creator: Organization: Silicon Laboratories, Inc.
+Created: 2025-10-26T17:54:28Z
+## Relationships
+Relationship: SPDXRef-DOCUMENT DESCRIBES SPDXRef-wiseconnect3_sdk-3.5.2
+Relationship: SPDXRef-DOCUMENT DESCRIBES SPDXRef-simplicity_sdk-2025.6.2
+
+## Package Information
+PackageName: WiSeConnect 3 SDK
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-SIWG917M111MGTBA
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-brd2605a
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-si91x_memory_default_config
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-sl_icm40627
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-sl_ssi
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-sl_ssi_instance
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-ssi_ulp_component
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-syscalls
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_opamp
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-wiseconnect_toolchain_gcc_standard
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_egpio
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-cmsis_usart
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-systemlevel_headers
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_spi
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-cmsis_driver_headers
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-wiseconnect_toolchain_plugin
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_aux_reference_volt_config
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-sl_si91x_mcu
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-systemlevel_time_period
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-external_psram_8mb
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-sl_clock_manager
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_usart
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-romdriver_udma_wrapper
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-freertos_config
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-romdriver_packing
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-romdriver_clks
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-systemlevel_bod
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-cmsis_udma
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-cmsis_common_driver
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_udma
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-sl_gpio_peripheral
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-romdriver_udma
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_dac
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-opn_config
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-systemlevel_ulpss_clk
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_adc
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-romdriver_romtable
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-systemlevel_reg_spi
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-romdriver_romtable_headers
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-romdriver_crc
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_headers
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-external_flash_none
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-sl_dma
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-si91x_mem_config_1
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_userconfig
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-cmsis_spi
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-sl_bjt_temperature_sensor
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-cmsis_peripheral_headers
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-sl_gpio
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-systemlevel_rtc
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-systemlevel_ipmu
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-udma_linker_config
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-board_configuration_headers
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-sl_adc
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-romdriver_egpio
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-systemlevel_temp_sensor
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-si91x_device_init_nvic
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-systemlevel_pll
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_board
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-brd2605a_config
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_clock_update
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-si91x_debug
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-si91x_common_flash
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_chip
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_sysrtc
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_udma_wrapper
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-si91x_stack_size_configuration
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-cmsis_usart_driver
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-sleeptimer_si91x
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-romdriver_ulpss
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2 CONTAINS SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_crc
+
+## Package Information
+PackageName: SIWG917M111MGTBA
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-SIWG917M111MGTBA
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: MSLA
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-SIWG917M111MGTBA CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: BRD2605A
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-brd2605a
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-brd2605a CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: Default RAM Memory Configuration
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-si91x_memory_default_config
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-si91x_memory_default_config CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: ICM40627 6-axis Inertial Sensor (IMU)
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-sl_icm40627
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-sl_icm40627 CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: SSI
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-sl_ssi
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-sl_ssi CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: SSI
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-sl_ssi_instance
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-sl_ssi_instance CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: PM ULP SSI
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-ssi_ulp_component
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-ssi_ulp_component CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: System Calls
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-syscalls
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: MSLA
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-syscalls CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: OPAMP
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_opamp
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_opamp CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: GCC Toolchain Standard Linker
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-wiseconnect_toolchain_gcc_standard
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-wiseconnect_toolchain_gcc_standard CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: EGPIO
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_egpio
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_egpio CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: CMSIS USART
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-cmsis_usart
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Apache-2.0 AND Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-cmsis_usart CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: System-Level API Headers
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-systemlevel_headers
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-systemlevel_headers CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: SPI
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_spi
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_spi CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: CMSIS Driver Header Files
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-cmsis_driver_headers
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Apache-2.0
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-cmsis_driver_headers CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: GCC Toolchain Support
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-wiseconnect_toolchain_plugin
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-wiseconnect_toolchain_plugin CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: AUX REFERENCE VOLT
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_aux_reference_volt_config
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_aux_reference_volt_config CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: Si91x MCU Subsystem
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-sl_si91x_mcu
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: MSLA
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-sl_si91x_mcu CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: TIME PERIOD
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-systemlevel_time_period
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-systemlevel_time_period CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: 8MB PSRAM (External)
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-external_psram_8mb
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-external_psram_8mb CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: Clock Manager
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-sl_clock_manager
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-sl_clock_manager CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: USART
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_usart
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_usart CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: ROM DRIVER UDMA WRAPPER
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-romdriver_udma_wrapper
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-romdriver_udma_wrapper CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: SL SI91X FreeRTOS Configuration
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-freertos_config
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: MIT
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-freertos_config CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: ROM DRIVER PACKING
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-romdriver_packing
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-romdriver_packing CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: ROM DRIVER CLOCK
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-romdriver_clks
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-romdriver_clks CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: BOD
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-systemlevel_bod
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-systemlevel_bod CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: CMSIS UDMA
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-cmsis_udma
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: MSLA AND Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-cmsis_udma CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: CMSIS COMMON DRIVER
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-cmsis_common_driver
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-cmsis_common_driver CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: UDMA
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_udma
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_udma CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: SL GPIO Peripheral
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-sl_gpio_peripheral
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-sl_gpio_peripheral CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: ROM DRIVER UDMA
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-romdriver_udma
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-romdriver_udma CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: DAC
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_dac
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_dac CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: opn config
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-opn_config
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-opn_config CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: ULPSS CLOCK
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-systemlevel_ulpss_clk
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-systemlevel_ulpss_clk CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: ADC
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_adc
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_adc CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: ROM TABLE
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-romdriver_romtable
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-romdriver_romtable CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: REG SPI
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-systemlevel_reg_spi
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-systemlevel_reg_spi CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: ROM Table Header
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-romdriver_romtable_headers
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-romdriver_romtable_headers CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: ROM DRIVER CRC
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-romdriver_crc
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-romdriver_crc CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: RSI Peripheral Headers
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_headers
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_headers CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: No External Flash
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-external_flash_none
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-external_flash_none CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: DMA
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-sl_dma
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-sl_dma CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: MEMORY_MCU_BASIC_WIRELESS_ADVANCED
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-si91x_mem_config_1
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-si91x_mem_config_1 CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: RSI User Configuration
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_userconfig
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: MSLA
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_userconfig CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: CMSIS SPI
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-cmsis_spi
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Apache-2.0
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-cmsis_spi CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: BJT Temperature Sensor
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-sl_bjt_temperature_sensor
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-sl_bjt_temperature_sensor CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: CMSIS Peripheral Header Files
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-cmsis_peripheral_headers
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: MSLA AND Apache-2.0
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-cmsis_peripheral_headers CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: GPIO
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-sl_gpio
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-sl_gpio CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: RTC
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-systemlevel_rtc
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-systemlevel_rtc CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: IPMU
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-systemlevel_ipmu
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-systemlevel_ipmu CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: UDMA Linker Configuration
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-udma_linker_config
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-udma_linker_config CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: Board Configuration Header Files
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-board_configuration_headers
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-board_configuration_headers CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: ADC
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-sl_adc
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-sl_adc CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: ROM DRIVER EGPIO
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-romdriver_egpio
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-romdriver_egpio CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: TEMPERATURE SENSOR
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-systemlevel_temp_sensor
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-systemlevel_temp_sensor CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: NVIC Interrupt Priorities Configuration for FreeRTOS
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-si91x_device_init_nvic
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: MSLA
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-si91x_device_init_nvic CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: PLL
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-systemlevel_pll
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-systemlevel_pll CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: Si91x SoC Board Configurations
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_board
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: MSLA AND Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_board CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: brd2605a config
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-brd2605a_config
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-brd2605a_config CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: CLOCK UPDATE
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_clock_update
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_clock_update CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: Debug Unit
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-si91x_debug
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-si91x_debug CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: Common Flash Component
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-si91x_common_flash
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-si91x_common_flash CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: Core
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_chip
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_chip CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: SYSRTC
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_sysrtc
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_sysrtc CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: UDMA WRAPPER
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_udma_wrapper
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_udma_wrapper CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: SiW91x Stack Size Configuration
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-si91x_stack_size_configuration
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-si91x_stack_size_configuration CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: CMSIS USART DRIVER
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-cmsis_usart_driver
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-cmsis_usart_driver CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: Sleep Timer for Si91x
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-sleeptimer_si91x
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-sleeptimer_si91x CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: ROM DRIVER ULPSS
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-romdriver_ulpss
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-romdriver_ulpss CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: CRC
+SPDXID: SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_crc
+PackageVersion: 3.5.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: NOASSERTION
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_crc CONTAINED_BY SPDXRef-wiseconnect3_sdk-3.5.2
+
+## Package Information
+PackageName: Simplicity SDK Suite
+SPDXID: SPDXRef-simplicity_sdk-2025.6.2
+PackageVersion: 2025.6.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: Silicon Laboratories, Inc.
+## Relationships
+Relationship: SPDXRef-simplicity_sdk-2025.6.2 CONTAINS SPDXRef-simplicity_sdk-2025.6.2-sl_main
+Relationship: SPDXRef-simplicity_sdk-2025.6.2 CONTAINS SPDXRef-simplicity_sdk-2025.6.2-sleeptimer
+Relationship: SPDXRef-simplicity_sdk-2025.6.2 CONTAINS SPDXRef-simplicity_sdk-2025.6.2-event_handler
+Relationship: SPDXRef-simplicity_sdk-2025.6.2 CONTAINS SPDXRef-simplicity_sdk-2025.6.2-sl_main_memory_init
+Relationship: SPDXRef-simplicity_sdk-2025.6.2 CONTAINS SPDXRef-simplicity_sdk-2025.6.2-atomic
+Relationship: SPDXRef-simplicity_sdk-2025.6.2 CONTAINS SPDXRef-simplicity_sdk-2025.6.2-code_classification
+Relationship: SPDXRef-simplicity_sdk-2025.6.2 CONTAINS SPDXRef-simplicity_sdk-2025.6.2-status
+Relationship: SPDXRef-simplicity_sdk-2025.6.2 CONTAINS SPDXRef-simplicity_sdk-2025.6.2-toolchain_variant_arm
+Relationship: SPDXRef-simplicity_sdk-2025.6.2 CONTAINS SPDXRef-simplicity_sdk-2025.6.2-sl_assert
+Relationship: SPDXRef-simplicity_sdk-2025.6.2 CONTAINS SPDXRef-simplicity_sdk-2025.6.2-component_catalog
+Relationship: SPDXRef-simplicity_sdk-2025.6.2 CONTAINS SPDXRef-simplicity_sdk-2025.6.2-sl_core
+Relationship: SPDXRef-simplicity_sdk-2025.6.2 CONTAINS SPDXRef-simplicity_sdk-2025.6.2-cmsis_core
+Relationship: SPDXRef-simplicity_sdk-2025.6.2 CONTAINS SPDXRef-simplicity_sdk-2025.6.2-sl_common
+Relationship: SPDXRef-simplicity_sdk-2025.6.2 CONTAINS SPDXRef-simplicity_sdk-2025.6.2-sl_main_init
+Relationship: SPDXRef-simplicity_sdk-2025.6.2 CONTAINS SPDXRef-simplicity_sdk-2025.6.2-sl_main_process_action
+
+## Package Information
+PackageName: System Setup (sl_main)
+SPDXID: SPDXRef-simplicity_sdk-2025.6.2-sl_main
+PackageVersion: 2025.6.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: Silicon Laboratories, Inc.
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-simplicity_sdk-2025.6.2-sl_main CONTAINED_BY SPDXRef-simplicity_sdk-2025.6.2
+
+## Package Information
+PackageName: Sleep Timer
+SPDXID: SPDXRef-simplicity_sdk-2025.6.2-sleeptimer
+PackageVersion: 2025.6.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: Silicon Laboratories, Inc.
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-simplicity_sdk-2025.6.2-sleeptimer CONTAINED_BY SPDXRef-simplicity_sdk-2025.6.2
+
+## Package Information
+PackageName: Event Handler
+SPDXID: SPDXRef-simplicity_sdk-2025.6.2-event_handler
+PackageVersion: 2025.6.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: Silicon Laboratories, Inc.
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-simplicity_sdk-2025.6.2-event_handler CONTAINED_BY SPDXRef-simplicity_sdk-2025.6.2
+
+## Package Information
+PackageName: sl_main Setup
+SPDXID: SPDXRef-simplicity_sdk-2025.6.2-sl_main_memory_init
+PackageVersion: 2025.6.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: Silicon Laboratories, Inc.
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-simplicity_sdk-2025.6.2-sl_main_memory_init CONTAINED_BY SPDXRef-simplicity_sdk-2025.6.2
+
+## Package Information
+PackageName: Atomic Operations Library
+SPDXID: SPDXRef-simplicity_sdk-2025.6.2-atomic
+PackageVersion: 2025.6.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: Silicon Laboratories, Inc.
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-simplicity_sdk-2025.6.2-atomic CONTAINED_BY SPDXRef-simplicity_sdk-2025.6.2
+
+## Package Information
+PackageName: Code Classification
+SPDXID: SPDXRef-simplicity_sdk-2025.6.2-code_classification
+PackageVersion: 2025.6.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: Silicon Laboratories, Inc.
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-simplicity_sdk-2025.6.2-code_classification CONTAINED_BY SPDXRef-simplicity_sdk-2025.6.2
+
+## Package Information
+PackageName: Status Codes Definitions
+SPDXID: SPDXRef-simplicity_sdk-2025.6.2-status
+PackageVersion: 2025.6.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: Silicon Laboratories, Inc.
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-simplicity_sdk-2025.6.2-status CONTAINED_BY SPDXRef-simplicity_sdk-2025.6.2
+
+## Package Information
+PackageName: Toolchain for ARM
+SPDXID: SPDXRef-simplicity_sdk-2025.6.2-toolchain_variant_arm
+PackageVersion: 2025.6.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: Silicon Laboratories, Inc.
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-simplicity_sdk-2025.6.2-toolchain_variant_arm CONTAINED_BY SPDXRef-simplicity_sdk-2025.6.2
+
+## Package Information
+PackageName: Assert Functions
+SPDXID: SPDXRef-simplicity_sdk-2025.6.2-sl_assert
+PackageVersion: 2025.6.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: Silicon Laboratories, Inc.
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-simplicity_sdk-2025.6.2-sl_assert CONTAINED_BY SPDXRef-simplicity_sdk-2025.6.2
+
+## Package Information
+PackageName: Component Catalog
+SPDXID: SPDXRef-simplicity_sdk-2025.6.2-component_catalog
+PackageVersion: 2025.6.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: Silicon Laboratories, Inc.
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-simplicity_sdk-2025.6.2-component_catalog CONTAINED_BY SPDXRef-simplicity_sdk-2025.6.2
+
+## Package Information
+PackageName: core
+SPDXID: SPDXRef-simplicity_sdk-2025.6.2-sl_core
+PackageVersion: 2025.6.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: Silicon Laboratories, Inc.
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-simplicity_sdk-2025.6.2-sl_core CONTAINED_BY SPDXRef-simplicity_sdk-2025.6.2
+
+## Package Information
+PackageName: CMSIS-Core
+SPDXID: SPDXRef-simplicity_sdk-2025.6.2-cmsis_core
+PackageVersion: 2025.6.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: Silicon Laboratories, Inc.
+PackageLicenseConcluded: Apache 2.0
+## Relationships
+Relationship: SPDXRef-simplicity_sdk-2025.6.2-cmsis_core CONTAINED_BY SPDXRef-simplicity_sdk-2025.6.2
+Relationship: SPDXRef-simplicity_sdk-2025.6.2-cmsis_core ANCESTOR_OF SPDXRef-cmsis_core-5.8.0
+
+## Package Information
+PackageName: CMSIS_5
+SPDXID: SPDXRef-cmsis_core-5.8.0
+PackageVersion: 5.8.0
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: ARM-software
+PackageOriginator: Organization: NOASSERTION
+PackageHomePage: https://github.com/ARM-software/CMSIS_5
+ExternalRef: PACKAGE-MANAGER purl pkg:github/ARM-software/CMSIS_5@5.8.0
+PackageComment: The CMSIS is a set of tools, APIs, frameworks, and work flows
+## Relationships
+Relationship: SPDXRef-cmsis_core-5.8.0 DESCENDANT_OF SPDXRef-simplicity_sdk-2025.6.2-cmsis_core
+
+## Package Information
+PackageName: Common Functions
+SPDXID: SPDXRef-simplicity_sdk-2025.6.2-sl_common
+PackageVersion: 2025.6.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: Silicon Laboratories, Inc.
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-simplicity_sdk-2025.6.2-sl_common CONTAINED_BY SPDXRef-simplicity_sdk-2025.6.2
+
+## Package Information
+PackageName: sl main Init
+SPDXID: SPDXRef-simplicity_sdk-2025.6.2-sl_main_init
+PackageVersion: 2025.6.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: Silicon Laboratories, Inc.
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-simplicity_sdk-2025.6.2-sl_main_init CONTAINED_BY SPDXRef-simplicity_sdk-2025.6.2
+
+## Package Information
+PackageName: sl_main Process Action
+SPDXID: SPDXRef-simplicity_sdk-2025.6.2-sl_main_process_action
+PackageVersion: 2025.6.2
+PrimaryPackagePurpose: LIBRARY
+PackageDownloadLocation: NOASSERTION
+PackageSupplier: Organization: Silicon Laboratories, Inc.
+PackageLicenseConcluded: Zlib
+## Relationships
+Relationship: SPDXRef-simplicity_sdk-2025.6.2-sl_main_process_action CONTAINED_BY SPDXRef-simplicity_sdk-2025.6.2
diff --git a/projects/bluetooth/sl_si91x_icm40627_3/autogen/sbom/spdx_bom.spdx.json b/projects/bluetooth/sl_si91x_icm40627_3/autogen/sbom/spdx_bom.spdx.json
new file mode 100644
index 0000000..53f36ed
--- /dev/null
+++ b/projects/bluetooth/sl_si91x_icm40627_3/autogen/sbom/spdx_bom.spdx.json
@@ -0,0 +1,1088 @@
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+ "documentNamespace" : "https://silabs.com",
+ "creationInfo" : {
+ "created" : "2025-10-26T17:54:28Z",
+ "creators" : [ "Tool: Silicon Labs Configuration Tooling" ]
+ },
+ "comment" : "TERMS OF USE - SILICON LABORATORIES INC.\n(With respect to Silicon Labs software components, this Software Bill of Materials (SBOM) is based upon Silicon Labs'\nreview and analysis of the code version when released. It is provided \"AS IS\" and does not modify, change or alter\nthe terms or conditions of your use of Silicon Labs' software and/or SDKs based upon license terms and/or agreements\nassociated with this software or SDKs when distributed to you, received by you, or installed by you. Further, no\nwarranties or obligations are created by this SBOM. It is your obligation to comply with the terms of licenses\nreferenced in this SBOM.)",
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+ "name" : "WiSeConnect 3 SDK",
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+ "supplier" : "Organization: NOASSERTION"
+ }, {
+ "SPDXID" : "SPDXRef-wiseconnect3_sdk-3.5.2-SIWG917M111MGTBA",
+ "name" : "SIWG917M111MGTBA",
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+ "name" : "BRD2605A",
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+ "name" : "Default RAM Memory Configuration",
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+ "relationshipType" : "CONTAINS"
+ }, {
+ "spdxElementId" : "SPDXRef-wiseconnect3_sdk-3.5.2",
+ "relatedSpdxElement" : "SPDXRef-wiseconnect3_sdk-3.5.2-systemlevel_ipmu",
+ "relationshipType" : "CONTAINS"
+ }, {
+ "spdxElementId" : "SPDXRef-wiseconnect3_sdk-3.5.2",
+ "relatedSpdxElement" : "SPDXRef-wiseconnect3_sdk-3.5.2-udma_linker_config",
+ "relationshipType" : "CONTAINS"
+ }, {
+ "spdxElementId" : "SPDXRef-wiseconnect3_sdk-3.5.2",
+ "relatedSpdxElement" : "SPDXRef-wiseconnect3_sdk-3.5.2-board_configuration_headers",
+ "relationshipType" : "CONTAINS"
+ }, {
+ "spdxElementId" : "SPDXRef-wiseconnect3_sdk-3.5.2",
+ "relatedSpdxElement" : "SPDXRef-wiseconnect3_sdk-3.5.2-sl_adc",
+ "relationshipType" : "CONTAINS"
+ }, {
+ "spdxElementId" : "SPDXRef-wiseconnect3_sdk-3.5.2",
+ "relatedSpdxElement" : "SPDXRef-wiseconnect3_sdk-3.5.2-romdriver_egpio",
+ "relationshipType" : "CONTAINS"
+ }, {
+ "spdxElementId" : "SPDXRef-wiseconnect3_sdk-3.5.2",
+ "relatedSpdxElement" : "SPDXRef-wiseconnect3_sdk-3.5.2-systemlevel_temp_sensor",
+ "relationshipType" : "CONTAINS"
+ }, {
+ "spdxElementId" : "SPDXRef-wiseconnect3_sdk-3.5.2",
+ "relatedSpdxElement" : "SPDXRef-wiseconnect3_sdk-3.5.2-si91x_device_init_nvic",
+ "relationshipType" : "CONTAINS"
+ }, {
+ "spdxElementId" : "SPDXRef-wiseconnect3_sdk-3.5.2",
+ "relatedSpdxElement" : "SPDXRef-wiseconnect3_sdk-3.5.2-systemlevel_pll",
+ "relationshipType" : "CONTAINS"
+ }, {
+ "spdxElementId" : "SPDXRef-wiseconnect3_sdk-3.5.2",
+ "relatedSpdxElement" : "SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_board",
+ "relationshipType" : "CONTAINS"
+ }, {
+ "spdxElementId" : "SPDXRef-wiseconnect3_sdk-3.5.2",
+ "relatedSpdxElement" : "SPDXRef-wiseconnect3_sdk-3.5.2-brd2605a_config",
+ "relationshipType" : "CONTAINS"
+ }, {
+ "spdxElementId" : "SPDXRef-wiseconnect3_sdk-3.5.2",
+ "relatedSpdxElement" : "SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_clock_update",
+ "relationshipType" : "CONTAINS"
+ }, {
+ "spdxElementId" : "SPDXRef-wiseconnect3_sdk-3.5.2",
+ "relatedSpdxElement" : "SPDXRef-wiseconnect3_sdk-3.5.2-si91x_debug",
+ "relationshipType" : "CONTAINS"
+ }, {
+ "spdxElementId" : "SPDXRef-wiseconnect3_sdk-3.5.2",
+ "relatedSpdxElement" : "SPDXRef-wiseconnect3_sdk-3.5.2-si91x_common_flash",
+ "relationshipType" : "CONTAINS"
+ }, {
+ "spdxElementId" : "SPDXRef-wiseconnect3_sdk-3.5.2",
+ "relatedSpdxElement" : "SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_chip",
+ "relationshipType" : "CONTAINS"
+ }, {
+ "spdxElementId" : "SPDXRef-wiseconnect3_sdk-3.5.2",
+ "relatedSpdxElement" : "SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_sysrtc",
+ "relationshipType" : "CONTAINS"
+ }, {
+ "spdxElementId" : "SPDXRef-wiseconnect3_sdk-3.5.2",
+ "relatedSpdxElement" : "SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_udma_wrapper",
+ "relationshipType" : "CONTAINS"
+ }, {
+ "spdxElementId" : "SPDXRef-wiseconnect3_sdk-3.5.2",
+ "relatedSpdxElement" : "SPDXRef-wiseconnect3_sdk-3.5.2-si91x_stack_size_configuration",
+ "relationshipType" : "CONTAINS"
+ }, {
+ "spdxElementId" : "SPDXRef-wiseconnect3_sdk-3.5.2",
+ "relatedSpdxElement" : "SPDXRef-wiseconnect3_sdk-3.5.2-cmsis_usart_driver",
+ "relationshipType" : "CONTAINS"
+ }, {
+ "spdxElementId" : "SPDXRef-wiseconnect3_sdk-3.5.2",
+ "relatedSpdxElement" : "SPDXRef-wiseconnect3_sdk-3.5.2-sleeptimer_si91x",
+ "relationshipType" : "CONTAINS"
+ }, {
+ "spdxElementId" : "SPDXRef-wiseconnect3_sdk-3.5.2",
+ "relatedSpdxElement" : "SPDXRef-wiseconnect3_sdk-3.5.2-romdriver_ulpss",
+ "relationshipType" : "CONTAINS"
+ }, {
+ "spdxElementId" : "SPDXRef-wiseconnect3_sdk-3.5.2",
+ "relatedSpdxElement" : "SPDXRef-wiseconnect3_sdk-3.5.2-rsilib_crc",
+ "relationshipType" : "CONTAINS"
+ }, {
+ "spdxElementId" : "SPDXRef-simplicity_sdk-2025.6.2",
+ "relatedSpdxElement" : "SPDXRef-simplicity_sdk-2025.6.2-sl_main",
+ "relationshipType" : "CONTAINS"
+ }, {
+ "spdxElementId" : "SPDXRef-simplicity_sdk-2025.6.2",
+ "relatedSpdxElement" : "SPDXRef-simplicity_sdk-2025.6.2-sleeptimer",
+ "relationshipType" : "CONTAINS"
+ }, {
+ "spdxElementId" : "SPDXRef-simplicity_sdk-2025.6.2",
+ "relatedSpdxElement" : "SPDXRef-simplicity_sdk-2025.6.2-event_handler",
+ "relationshipType" : "CONTAINS"
+ }, {
+ "spdxElementId" : "SPDXRef-simplicity_sdk-2025.6.2",
+ "relatedSpdxElement" : "SPDXRef-simplicity_sdk-2025.6.2-sl_main_memory_init",
+ "relationshipType" : "CONTAINS"
+ }, {
+ "spdxElementId" : "SPDXRef-simplicity_sdk-2025.6.2",
+ "relatedSpdxElement" : "SPDXRef-simplicity_sdk-2025.6.2-atomic",
+ "relationshipType" : "CONTAINS"
+ }, {
+ "spdxElementId" : "SPDXRef-simplicity_sdk-2025.6.2",
+ "relatedSpdxElement" : "SPDXRef-simplicity_sdk-2025.6.2-code_classification",
+ "relationshipType" : "CONTAINS"
+ }, {
+ "spdxElementId" : "SPDXRef-simplicity_sdk-2025.6.2",
+ "relatedSpdxElement" : "SPDXRef-simplicity_sdk-2025.6.2-status",
+ "relationshipType" : "CONTAINS"
+ }, {
+ "spdxElementId" : "SPDXRef-simplicity_sdk-2025.6.2",
+ "relatedSpdxElement" : "SPDXRef-simplicity_sdk-2025.6.2-toolchain_variant_arm",
+ "relationshipType" : "CONTAINS"
+ }, {
+ "spdxElementId" : "SPDXRef-simplicity_sdk-2025.6.2",
+ "relatedSpdxElement" : "SPDXRef-simplicity_sdk-2025.6.2-sl_assert",
+ "relationshipType" : "CONTAINS"
+ }, {
+ "spdxElementId" : "SPDXRef-simplicity_sdk-2025.6.2",
+ "relatedSpdxElement" : "SPDXRef-simplicity_sdk-2025.6.2-component_catalog",
+ "relationshipType" : "CONTAINS"
+ }, {
+ "spdxElementId" : "SPDXRef-simplicity_sdk-2025.6.2",
+ "relatedSpdxElement" : "SPDXRef-simplicity_sdk-2025.6.2-sl_core",
+ "relationshipType" : "CONTAINS"
+ }, {
+ "spdxElementId" : "SPDXRef-simplicity_sdk-2025.6.2",
+ "relatedSpdxElement" : "SPDXRef-simplicity_sdk-2025.6.2-cmsis_core",
+ "relationshipType" : "CONTAINS"
+ }, {
+ "spdxElementId" : "SPDXRef-simplicity_sdk-2025.6.2-cmsis_core",
+ "relatedSpdxElement" : "SPDXRef-cmsis_core-5.8.0",
+ "relationshipType" : "ANCESTOR_OF"
+ }, {
+ "spdxElementId" : "SPDXRef-simplicity_sdk-2025.6.2",
+ "relatedSpdxElement" : "SPDXRef-simplicity_sdk-2025.6.2-sl_common",
+ "relationshipType" : "CONTAINS"
+ }, {
+ "spdxElementId" : "SPDXRef-simplicity_sdk-2025.6.2",
+ "relatedSpdxElement" : "SPDXRef-simplicity_sdk-2025.6.2-sl_main_init",
+ "relationshipType" : "CONTAINS"
+ }, {
+ "spdxElementId" : "SPDXRef-simplicity_sdk-2025.6.2",
+ "relatedSpdxElement" : "SPDXRef-simplicity_sdk-2025.6.2-sl_main_process_action",
+ "relationshipType" : "CONTAINS"
+ } ]
+}
\ No newline at end of file
diff --git a/projects/bluetooth/sl_si91x_icm40627_3/autogen/sl_component_catalog.h b/projects/bluetooth/sl_si91x_icm40627_3/autogen/sl_component_catalog.h
new file mode 100644
index 0000000..7b3e47c
--- /dev/null
+++ b/projects/bluetooth/sl_si91x_icm40627_3/autogen/sl_component_catalog.h
@@ -0,0 +1,10 @@
+#ifndef SL_COMPONENT_CATALOG_H
+#define SL_COMPONENT_CATALOG_H
+
+// APIs present in project
+#define SL_CATALOG_SSI_ULP_PRIMARY_PRESENT
+#define SL_CATALOG_SL_CORE_PRESENT
+#define SL_CATALOG_SL_MAIN_PRESENT
+#define SL_CATALOG_SLEEPTIMER_PRESENT
+
+#endif // SL_COMPONENT_CATALOG_H
diff --git a/projects/bluetooth/sl_si91x_icm40627_3/autogen/sl_event_handler.c b/projects/bluetooth/sl_si91x_icm40627_3/autogen/sl_event_handler.c
new file mode 100644
index 0000000..b5a332e
--- /dev/null
+++ b/projects/bluetooth/sl_si91x_icm40627_3/autogen/sl_event_handler.c
@@ -0,0 +1,65 @@
+#include "sl_event_handler.h"
+
+#include "sl_si91x_clock_manager.h"
+#include "rsi_board.h"
+#include "rsi_debug.h"
+
+void sli_driver_permanent_allocation(void)
+{
+}
+
+void sli_service_permanent_allocation(void)
+{
+}
+
+void sli_stack_permanent_allocation(void)
+{
+}
+
+void sli_internal_permanent_allocation(void)
+{
+}
+
+void sl_platform_init(void)
+{
+ sl_si91x_clock_manager_init();
+ RSI_Board_Init();
+ DEBUGINIT();
+}
+
+void sli_internal_init_early(void)
+{
+}
+
+void sl_driver_init(void)
+{
+}
+
+void sl_service_init(void)
+{
+}
+
+void sl_stack_init(void)
+{
+}
+
+void sl_internal_app_init(void)
+{
+}
+
+void sli_platform_process_action(void)
+{
+}
+
+void sli_service_process_action(void)
+{
+}
+
+void sli_stack_process_action(void)
+{
+}
+
+void sli_internal_app_process_action(void)
+{
+}
+
diff --git a/projects/bluetooth/sl_si91x_icm40627_3/autogen/sl_event_handler.h b/projects/bluetooth/sl_si91x_icm40627_3/autogen/sl_event_handler.h
new file mode 100644
index 0000000..5d22097
--- /dev/null
+++ b/projects/bluetooth/sl_si91x_icm40627_3/autogen/sl_event_handler.h
@@ -0,0 +1,19 @@
+#ifndef SL_EVENT_HANDLER_H
+#define SL_EVENT_HANDLER_H
+
+void sli_driver_permanent_allocation(void);
+void sli_service_permanent_allocation(void);
+void sli_stack_permanent_allocation(void);
+void sli_internal_permanent_allocation(void);
+void sl_platform_init(void);
+void sli_internal_init_early(void);
+void sl_driver_init(void);
+void sl_service_init(void);
+void sl_stack_init(void);
+void sl_internal_app_init(void);
+void sli_platform_process_action(void);
+void sli_service_process_action(void);
+void sli_stack_process_action(void);
+void sli_internal_app_process_action(void);
+
+#endif // SL_EVENT_HANDLER_H
diff --git a/projects/bluetooth/sl_si91x_icm40627_3/autogen/sl_ssi_common_config.h b/projects/bluetooth/sl_si91x_icm40627_3/autogen/sl_ssi_common_config.h
new file mode 100644
index 0000000..f1b39f9
--- /dev/null
+++ b/projects/bluetooth/sl_si91x_icm40627_3/autogen/sl_ssi_common_config.h
@@ -0,0 +1,47 @@
+/***************************************************************************//**
+ * @file sl_ssi_common_config.h.jinja
+ * @brief SSI Common configuration
+ *******************************************************************************
+ * # License
+ * Copyright 2024 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef SL_SSI_COMMON_CONFIG_H
+#define SL_SSI_COMMON_CONFIG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#include "sl_si91x_ssi_ulp_primary_common_config.h"
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // SL_SSI_COMMON_CONFIG_H
diff --git a/projects/bluetooth/sl_si91x_icm40627_3/autogen/sl_ssi_instances.h b/projects/bluetooth/sl_si91x_icm40627_3/autogen/sl_ssi_instances.h
new file mode 100644
index 0000000..b246486
--- /dev/null
+++ b/projects/bluetooth/sl_si91x_icm40627_3/autogen/sl_ssi_instances.h
@@ -0,0 +1,58 @@
+/***************************************************************************//**
+ * @file sl_ssi_instances.h.jinja
+ * @brief SSI Driver Instance
+ *******************************************************************************
+ * # License
+ * Copyright 2024 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef SL_SSI_INSTANCES_H
+#define SL_SSI_INSTANCES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+
+#include "sl_si91x_ssi_ulp_primary_config.h"
+
+
+
+sl_ssi_control_config_t ssi_ulp_primary_configuration = {
+ .bit_width = SL_SSI_ULP_PRIMARY_BIT_WIDTH,
+ .device_mode = SL_SSI_ULP_PRIMARY_DEVICE_MODE,
+ .clock_mode = SL_SSI_ULP_PRIMARY_CLOCK_MODE,
+ .receive_sample_delay = SL_SSI_ULP_PRIMARY_RECEIVE_SAMPLE_DELAY,
+ .baud_rate = SL_SSI_ULP_PRIMARY_BAUD,
+ .transfer_mode = SL_SSI_ULP_PRIMARY_TRANSFER_MODE,
+};
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // SL_SSI_INSTANCES_H
diff --git a/projects/bluetooth/sl_si91x_icm40627_3/config/FreeRTOSConfig.h b/projects/bluetooth/sl_si91x_icm40627_3/config/FreeRTOSConfig.h
new file mode 100644
index 0000000..4176156
--- /dev/null
+++ b/projects/bluetooth/sl_si91x_icm40627_3/config/FreeRTOSConfig.h
@@ -0,0 +1,351 @@
+/*
+FreeRTOS Kernel V10.2.0
+Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy of
+this software and associated documentation files (the "Software"), to deal in
+the Software without restriction, including without limitation the rights to
+use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+the Software, and to permit persons to whom the Software is furnished to do so,
+subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+ http://aws.amazon.com/freertos
+ http://www.FreeRTOS.org
+*/
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+*
+* These definitions should be adjusted for your particular hardware and
+* application requirements.
+*
+* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+* http://www.freertos.org/a00110.html
+*
+* The bottom of this file contains some constants specific to running the UDP
+* stack in this demo. Constants specific to FreeRTOS+TCP itself (rather than
+* the demo) are contained in FreeRTOSIPConfig.h.
+*----------------------------------------------------------*/
+
+#include
+#include "si91x_device.h"
+#if (SL_SI91X_TICKLESS_MODE == 1)
+#include "sl_si91x_m4_ps.h"
+#endif
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+// Minimal stack size [words] <0-65535>
+// Stack for idle task and default task stack in words.
+// Default: 256
+#define configMINIMAL_STACK_SIZE 256
+
+// Total heap size [bytes] <0-0xFFFFFFFF>
+// Heap memory size in bytes.
+// Default: 51200
+#define configTOTAL_HEAP_SIZE 51200
+
+// Kernel tick frequency [Hz] <0-0xFFFFFFFF>
+// Kernel tick rate in Hz.
+// Default: 1000
+#define configTICK_RATE_HZ 1000
+
+// Timer task stack depth [words] <0-65535>
+// Stack for timer task in words.
+// Default: 512
+#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2)
+
+// Timer task priority <0-56>
+// Timer task priority.
+// Default: 55 (High)
+#define configTIMER_TASK_PRIORITY 55
+
+// Timer queue length <0-1024>
+// Timer command queue length.
+// Default: 5
+#define configTIMER_QUEUE_LENGTH 5
+
+// Use time slicing
+// Enable setting to use timeslicing.
+// Default: 1
+#define configUSE_TIME_SLICING 1
+
+#if (SL_SI91X_TICKLESS_MODE == 1)
+// Use TICKLESS IDLE for Energy Management
+// Enable setting to use Tickless Idle.
+// Default: 0
+#define configUSE_TICKLESS_IDLE 1
+#else
+// Use TICKLESS IDLE for Energy Management
+// Enable setting to use Tickless Idle.
+// Default: 0
+#define configUSE_TICKLESS_IDLE 0
+#endif
+
+#if (configUSE_TICKLESS_IDLE == 1)
+
+// At least "n" further complete tick periods will pass before the kernel is
+// due to transition an application task out of the Blocked state,
+// where "n" is set by the configEXPECTED_IDLE_TIME_BEFORE_SLEEP
+#define configEXPECTED_IDLE_TIME_BEFORE_SLEEP 100
+
+// Define the following macro to set xExpectedIdleTime to 0
+// if the application prevents the device Sleep
+#define configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING(x)
+
+// Activate SiWx917 MCU specific low power functionality
+#define configPRE_SLEEP_PROCESSING(x)
+
+// It can be used to reverse the actions of configPRE_SLEEP_PROCESSING(),
+// and in so doing, return the Micro-controller back to its fully operational
+// state.
+#define configPOST_SLEEP_PROCESSING(x)
+
+#endif
+
+// Idle should yield
+// Control Yield behaviour of the idle task.
+// Default: 1
+#define configIDLE_SHOULD_YIELD 1
+
+// Check for stack overflow
+// <0=>Disable <1=>Method one <2=>Method two
+// Enable or disable stack overflow checking.
+// Callback function vApplicationStackOverflowHook implementation is required when stack checking is enabled.
+// Not applicable to the Win32 port.
+// Default: 0
+#define configCHECK_FOR_STACK_OVERFLOW 0
+
+#if (configUSE_TICKLESS_IDLE == 1)
+
+// Use idle hook
+// Enable callback function call on each idle task iteration.
+// Callback function vApplicationIdleHook implementation is required when
+// idle hook is enabled. Default: 0
+#define configUSE_IDLE_HOOK 1
+#endif
+
+#if (configUSE_TICKLESS_IDLE == 0)
+
+// Use idle hook
+// Enable callback function call on each idle task iteration.
+// Callback function vApplicationIdleHook implementation is required when
+// idle hook is enabled. Default: 0
+#define configUSE_IDLE_HOOK 0
+#endif
+
+// Use tick hook
+// Enable callback function call during each tick interrupt.
+// Callback function vApplicationTickHook implementation is required when tick hook is enabled.
+// Default: 0
+#define configUSE_TICK_HOOK 0
+
+// Use deamon task startup hook
+// Enable callback function call when timer service starts.
+// Callback function vApplicationDaemonTaskStartupHook implementation is required when deamon task startup hook is enabled.
+// Default: 0
+#define configUSE_DAEMON_TASK_STARTUP_HOOK 0
+
+// Use malloc failed hook
+// Enable callback function call when out of dynamic memory.
+// Callback function vApplicationMallocFailedHook implementation is required when malloc failed hook is enabled.
+// Default: 0
+#define configUSE_MALLOC_FAILED_HOOK 0
+
+// Queue registry size
+// Define maximum number of queue objects registered for debug purposes.
+// The queue registry is used by kernel aware debuggers to locate queue and semaphore structures and display associated text names.
+// Default: 8
+#define configQUEUE_REGISTRY_SIZE 8
+
+// Port Specific Features
+// Enable and configure port specific features.
+// Check FreeRTOS documentation for definitions that apply for the used port.
+
+// Use Floating Point Unit
+// Using Floating Point Unit (FPU) affects context handling.
+// Enable FPU when application uses floating point operations.
+// Default: 1
+#define configENABLE_FPU 1
+
+// Use Memory Protection Unit
+// Using Memory Protection Unit (MPU) requires detailed memory map definition.
+// This setting is only releavant for MPU enabled ports.
+// Default: 0
+#define configENABLE_MPU 0
+
+//
+
+// Thread Local Storage Settings
+// Thread local storage pointers
+// Thread local storage (or TLS) allows the application writer to store
+// values inside a task's control block, making the value specific to
+// (local to) the task itself.
+// Default: 0
+#define configNUM_USER_THREAD_LOCAL_STORAGE_POINTERS 0
+//
+
+// Use Threadsafe Errno
+// Enable Threadsafe Errno support.
+// Default: 0
+#define configUSE_POSIX_ERRNO 1
+
+//------------- <<< end of configuration section >>> ---------------------------
+
+extern uint32_t SystemCoreClock;
+
+#define configCPU_CLOCK_HZ SystemCoreClock
+#define configENABLE_BACKWARD_COMPATIBILITY 1
+#define configUSE_PREEMPTION 1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configMAX_PRIORITIES (56)
+#define configMAX_TASK_NAME_LEN (15)
+#define configUSE_TRACE_FACILITY 1
+#define configUSE_16_BIT_TICKS 0
+#define configUSE_CO_ROUTINES 0
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_APPLICATION_TASK_TAG 0
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configUSE_ALTERNATIVE_API 0
+#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5 /* FreeRTOS+FAT requires 2 pointers if a CWD is supported. */
+#define configRECORD_STACK_HIGH_ADDRESS 1
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+
+/* Event group related definitions. */
+#define configUSE_EVENT_GROUPS 1
+
+/* Run time stats gathering definitions. */
+
+unsigned long ulGetRunTimeCounterValue(void);
+void vConfigureTimerForRunTimeStats(void);
+#define configGENERATE_RUN_TIME_STATS 0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES (2)
+
+/* Currently the TCP/IP stack is using dynamic allocation, and the MQTT task is
+ * using static allocation. */
+#define configSUPPORT_DYNAMIC_ALLOCATION 1
+#define configSUPPORT_STATIC_ALLOCATION 1
+
+/* Set the following definitions to 1 to include the API function, or zero
+ * to exclude the API function. */
+#define INCLUDE_vTaskPrioritySet 1
+#define INCLUDE_uxTaskPriorityGet 1
+#define INCLUDE_vTaskDelete 1
+#define INCLUDE_vTaskCleanUpResources 1
+#define INCLUDE_vTaskSuspend 1
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 1
+#define INCLUDE_xTaskGetSchedulerState 1
+#define INCLUDE_xTimerGetTimerTaskHandle 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_xQueueGetMutexHolder 1
+#define INCLUDE_eTaskGetState 1
+#define INCLUDE_xEventGroupSetBitsFromISR 1
+#define INCLUDE_xTimerPendFunctionCall 1
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_xTaskAbortDelay 1
+
+/* Cortex-M specific definitions. */
+#ifdef __NVIC_PRIO_BITS
+#undef __NVIC_PRIO_BITS
+#endif
+#define configPRIO_BITS 6 /* 6 priority levels. */
+
+/* This demo makes use of one or more example stats formatting functions. These
+ * format the raw data provided by the uxTaskGetSystemState() function in to human
+ * readable ASCII form. See the notes in the implementation of vTaskList() within
+ * FreeRTOS/Source/tasks.c for limitations. configUSE_STATS_FORMATTING_FUNCTIONS
+ * is set to 2 so the formatting functions are included without the stdio.h being
+ * included in tasks.c. That is because this project defines its own sprintf()
+ * functions. */
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
+standard names. */
+#define vPortSVCHandler SVC_Handler
+#define xPortPendSVHandler PendSV_Handler
+#define vHardFault_Handler HardFault_Handler
+
+#if (configUSE_TICKLESS_IDLE == 0)
+/* Ensure Cortex-M port compatibility. */
+#define SysTick_Handler xPortSysTickHandler
+#endif
+/* Assert call defined for debug builds. */
+void vAssertCalled(const char *pcFile, uint32_t ulLine);
+
+#define configASSERT(x) \
+ if ((x) == 0) { \
+ taskDISABLE_INTERRUPTS(); \
+ for (;;) \
+ ; \
+ }
+
+#define configASSERTNULL(x) \
+ if ((x) == NULL) { \
+ taskDISABLE_INTERRUPTS(); \
+ for (;;) \
+ ; \
+ }
+
+/* The function that implements FreeRTOS printf style output, and the macro
+ * that maps the configPRINTF() macros to that function. */
+extern void vLoggingPrintf(const char *pcFormat, ...);
+#define configPRINTF(X) vLoggingPrintf X
+
+/* Non-format version thread-safe print */
+extern void vLoggingPrint(const char *pcMessage);
+#define configPRINT(X) vLoggingPrint(X)
+
+/* Map the logging task's printf to the board specific output function. */
+#define configPRINT_STRING(X) printf(X); /* : Change to your devices console print acceptance function. */
+/* Sets the length of the buffers into which logging messages are written - so
+ * also defines the maximum length of each log message. */
+#define configLOGGING_MAX_MESSAGE_LENGTH 100
+
+/* Set to 1 to prepend each log message with a message number, the task name,
+ * and a time stamp. */
+#define configLOGGING_INCLUDE_TIME_AND_TASK_NAME 1
+
+/* The priority at which the tick interrupt runs. This should probably be kept at 1. */
+//#define configKERNEL_INTERRUPT_PRIORITY 1
+
+/* The lowest interrupt priority that can be used in a call to a "set priority"
+function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x3f
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
+
+/* Interrupt priorities used by the kernel port layer itself. These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
+
+/* The platform FreeRTOS is running on. */
+#define configPLATFORM_NAME "Si917_SoC"
+
+#endif /* FREERTOS_CONFIG_H */
\ No newline at end of file
diff --git a/projects/bluetooth/sl_si91x_icm40627_3/config/RTE_Device_917.h b/projects/bluetooth/sl_si91x_icm40627_3/config/RTE_Device_917.h
new file mode 100644
index 0000000..8d3b25d
--- /dev/null
+++ b/projects/bluetooth/sl_si91x_icm40627_3/config/RTE_Device_917.h
@@ -0,0 +1,5845 @@
+/* -----------------------------------------------------------------------------
+ * Copyright (c) 2013-2016 ARM Ltd.
+ *
+ * This software is provided 'as-is', without any express or implied warranty.
+ * In no event will the authors be held liable for any damages arising from
+ * the use of this software. Permission is granted to anyone to use this
+ * software for any purpose, including commercial applications, and to alter
+ * it and redistribute it freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software in
+ * a product, an acknowledgement in the product documentation would be
+ * appreciated but is not required.
+ *
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ *
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * $Date: 1. June 2024
+ * $Revision: V2.4.4
+ *
+ * Project: RTE Device Configuration for Si91x 2.0 B0 BRD2605A
+ * -------------------------------------------------------------------------- */
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+#ifndef __RTE_DEVICE_H
+#define __RTE_DEVICE_H
+#include "rsi_ccp_user_config.h"
+#include "pin_config.h"
+
+// These macros define GPIO ports generated by PinTool
+// to ensure proper mapping and compatibility with the driver.
+#define HP 0
+#define ULP 4
+#define UULP_VBAT 5
+
+#define GPIO_PORT_0 0 // GPIO PORT HP
+#define ULP_GPIO_MODE_6 6 // ULP GPIO mode 6
+#define HOST_PAD_GPIO_MIN 25 // GPIO host pad minimum pin number
+#define HOST_PAD_GPIO_MAX 30 // GPIO host pad maximum pin number
+#define GPIO_MAX_PIN 64 // GPIO maximum pin number
+
+#define RTE_ULP_PORT 0
+
+#define BUTTON_0_GPIO_PIN 2
+
+#define RTE_BUTTON0_PORT UULP_VBAT
+#define RTE_BUTTON0_NUMBER 0
+#define RTE_BUTTON0_PIN (2U)
+
+#define RTE_BUTTON1_PORT 3
+#define RTE_BUTTON1_NUMBER 1
+#define RTE_BUTTON1_PIN (1U)
+#define RTE_BUTTON1_PAD 13
+
+// RGB LED Instance 0
+#define RTE_LED0_NUMBER 0
+
+// Red LED
+#define RTE_LED0_LEDR_PORT 3
+#define RTE_LED0_LEDR_NUMBER RTE_LED0_NUMBER
+#define RTE_LED0_LEDR_PIN 2
+#define RTE_LED0_LEDR_PAD 14
+
+// Green LED
+#define RTE_LED0_LEDG_PORT 3
+#define RTE_LED0_LEDG_NUMBER RTE_LED0_NUMBER
+#define RTE_LED0_LEDG_PIN 3
+#define RTE_LED0_LEDG_PAD 15
+
+// Blue LED
+#define RTE_LED0_LEDB_PORT HP
+#define RTE_LED0_LEDB_NUMBER RTE_LED0_NUMBER
+#define RTE_LED0_LEDB_PIN 15
+#define RTE_LED0_LEDB_PAD 8
+
+// USART0 [Driver_USART0]
+// Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART
+#define RTE_ENABLE_FIFO 1
+
+#define RTE_USART0 1
+
+#define RTE_USART0_CLK_SRC USART_ULPREFCLK
+#define RTE_USART0_CLK_DIV_FACT 1
+#define RTE_USART0_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER
+
+#define RTE_USART_MODE 0 //!Usart mode macros
+#define RTE_CONTINUOUS_CLOCK_MODE 0
+
+#define RTE_USART0_LOOPBACK 0
+#define RTE_USART0_DTR_EANBLE 0
+
+#define RTE_USART0_DMA_MODE1_EN 0 //!dma mode
+
+#define RTE_USART0_TX_FIFO_THRESHOLD USART_TRIGGER_TX_EMPTY
+#define RTE_USART0_RX_FIFO_THRESHOLD USART_TRIGGER_RX_AEMPTY
+
+#define RTE_USART0_DMA_TX_LEN_PER_DES 1024
+#define RTE_USART0_DMA_RX_LEN_PER_DES 1024
+
+#define RTE_USART0_CHNL_UDMA_TX_CH 25
+
+#define RTE_USART0_CHNL_UDMA_RX_CH 24
+
+// USART0_CLK <0=>P0_8 <1=>P0_25 <2=>P0_52 <3=>P0_64
+// CLK of USART0
+#ifndef USART0_CLK_LOC
+#define RTE_USART0_CLK_PORT_ID 0
+
+#if (RTE_USART0_CLK_PORT_ID == 0)
+#define RTE_USART0_CLK_PORT HP
+#define RTE_USART0_CLK_PIN 8
+#define RTE_USART0_CLK_MUX 2
+#define RTE_USART0_CLK_PAD 3
+#elif (RTE_USART0_CLK_PORT_ID == 1)
+#define RTE_USART0_CLK_PORT HP
+#define RTE_USART0_CLK_PIN 25
+#define RTE_USART0_CLK_MUX 2
+#define RTE_USART0_CLK_PAD 0 //NO PAD
+#elif (RTE_USART0_CLK_PORT_ID == 2)
+#define RTE_USART0_CLK_PORT HP
+#define RTE_USART0_CLK_PIN 52
+#define RTE_USART0_CLK_MUX 2
+#define RTE_USART0_CLK_PAD 16
+#else
+#error "Invalid USART0 RTE_USART0_CLK_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_USART0_CLK_PORT HP
+#if (USART0_CLK_LOC == 0)
+#define RTE_USART0_CLK_PIN USART0_CLK_PIN
+#define RTE_USART0_CLK_MUX 2
+#define RTE_USART0_CLK_PAD 3
+#endif
+#if (USART0_CLK_LOC == 1)
+#define RTE_USART0_CLK_PIN USART0_CLK_PIN
+#define RTE_USART0_CLK_MUX 2
+#define RTE_USART0_CLK_PAD 0 //NO PAD
+#endif
+#if (USART0_CLK_LOC == 2)
+#define RTE_USART0_CLK_PIN USART0_CLK_PIN
+#define RTE_USART0_CLK_MUX 2
+#define RTE_USART0_CLK_PAD 16
+#endif
+#if (USART0_CLK_LOC == 3)
+#define RTE_USART0_CLK_PIN (USART0_CLK_PIN + GPIO_MAX_PIN)
+#define RTE_USART0_CLK_MUX 2
+#define RTE_USART0_CLK_PAD 22
+#endif
+//Pintool data
+#endif
+
+// USART0_TX <0=>P0_15 <1=>P0_30 <2=>P0_54 <3=>P0_68 <4=>P0_71
+// TX for USART0
+#ifndef USART0_TX_LOC
+#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
+#define RTE_USART0_TX_PORT_ID 1
+#else
+#define RTE_USART0_TX_PORT_ID 0
+#endif
+
+#if (RTE_USART0_TX_PORT_ID == 0)
+#define RTE_USART0_TX_PORT HP
+#define RTE_USART0_TX_PIN 15
+#define RTE_USART0_TX_MUX 2
+#define RTE_USART0_TX_PAD 8
+#elif (RTE_USART0_TX_PORT_ID == 1)
+#define RTE_USART0_TX_PORT HP
+#define RTE_USART0_TX_PIN 30
+#define RTE_USART0_TX_MUX 2
+#define RTE_USART0_TX_PAD 0 //NO PAD
+#elif (RTE_USART0_TX_PORT_ID == 2)
+#define RTE_USART0_TX_PORT HP
+#define RTE_USART0_TX_PIN 54
+#define RTE_USART0_TX_MUX 2
+#define RTE_USART0_TX_PAD 18
+#elif (RTE_USART0_TX_PORT_ID == 3)
+#define RTE_USART0_TX_PORT HP
+#define RTE_USART0_TX_PIN 71
+#define RTE_USART0_TX_MUX 4
+#define RTE_USART0_TX_PAD 29
+#else
+#error "Invalid USART0 RTE_USART0_TX_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_USART0_TX_PORT HP
+#if (USART0_TX_LOC == 4)
+#define RTE_USART0_TX_PIN USART0_TX_PIN
+#define RTE_USART0_TX_MUX 2
+#define RTE_USART0_TX_PAD 8
+#endif
+#if (USART0_TX_LOC == 5)
+#define RTE_USART0_TX_PIN USART0_TX_PIN
+#define RTE_USART0_TX_MUX 2
+#define RTE_USART0_TX_PAD 0 //NO PAD
+#endif
+#if (USART0_TX_LOC == 6)
+#define RTE_USART0_TX_PIN USART0_TX_PIN
+#define RTE_USART0_TX_MUX 2
+#define RTE_USART0_TX_PAD 18
+#endif
+#if (USART0_TX_LOC == 7)
+#define RTE_USART0_TX_PIN (USART0_TX_PIN + GPIO_MAX_PIN)
+#define RTE_USART0_TX_MUX 2
+#define RTE_USART0_TX_PAD 26
+#endif
+#if (USART0_TX_LOC == 8)
+#define RTE_USART0_TX_PIN (USART0_TX_PIN + GPIO_MAX_PIN)
+#define RTE_USART0_TX_MUX 4
+#define RTE_USART0_TX_PAD 29
+#endif
+//Pintool data
+#endif
+
+// USART0_RX <0=>P0_10 <1=>P0_29 <2=>P0_55 <3=>P0_65 <4=>P0_70
+// RX for USART0
+#ifndef USART0_RX_LOC
+#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
+#define RTE_USART0_RX_PORT_ID 1
+#else
+#define RTE_USART0_RX_PORT_ID 0
+#endif
+
+#if (RTE_USART0_RX_PORT_ID == 0)
+#define RTE_USART0_RX_PORT HP
+#define RTE_USART0_RX_PIN 10
+#define RTE_USART0_RX_MUX 2
+#define RTE_USART0_RX_PAD 5
+#elif (RTE_USART0_RX_PORT_ID == 1)
+#define RTE_USART0_RX_PORT HP
+#define RTE_USART0_RX_PIN 29
+#define RTE_USART0_RX_MUX 2
+#define RTE_USART0_RX_PAD 0 //no pad
+#elif (RTE_USART0_RX_PORT_ID == 2)
+#define RTE_USART0_RX_PORT HP
+#define RTE_USART0_RX_PIN 55
+#define RTE_USART0_RX_MUX 2
+#define RTE_USART0_RX_PAD 19
+#elif (RTE_USART0_RX_PORT_ID == 3)
+#define RTE_USART0_RX_PORT HP
+#define RTE_USART0_RX_PIN 65
+#define RTE_USART0_RX_MUX 2
+#define RTE_USART0_RX_PAD 23
+#elif (RTE_USART0_RX_PORT_ID == 4)
+#define RTE_USART0_RX_PORT HP
+#define RTE_USART0_RX_PIN 70
+#define RTE_USART0_RX_MUX 4
+#define RTE_USART0_RX_PAD 28
+#else
+#error "Invalid USART0 RTE_USART0_RX_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_USART0_RX_PORT HP
+#if (USART0_RX_LOC == 9)
+#define RTE_USART0_RX_PIN USART0_RX_PIN
+#define RTE_USART0_RX_MUX 2
+#define RTE_USART0_RX_PAD 5
+#endif
+#if (USART0_RX_LOC == 10)
+#define RTE_USART0_RX_PIN USART0_RX_PIN
+#define RTE_USART0_RX_MUX 2
+#define RTE_USART0_RX_PAD 0 //no pad
+#endif
+#if (USART0_RX_LOC == 11)
+#define RTE_USART0_RX_PIN USART0_RX_PIN
+#define RTE_USART0_RX_MUX 2
+#define RTE_USART0_RX_PAD 19
+#endif
+#if (USART0_RX_LOC == 12)
+#define RTE_USART0_RX_PIN (USART0_RX_PIN + GPIO_MAX_PIN)
+#define RTE_USART0_RX_MUX 2
+#define RTE_USART0_RX_PAD 23
+#endif
+#if (USART0_RX_LOC == 13)
+#define RTE_USART0_RX_PIN (USART0_RX_PIN + GPIO_MAX_PIN)
+#define RTE_USART0_RX_MUX 4
+#define RTE_USART0_RX_PAD 28
+#endif
+//Pintool data
+#endif
+
+// USART0_CTS <0=>P0_6 <1=>P0_26 <2=>P0_56 <3=>P0_70
+// CTS for USART0
+#ifndef USART0_CTS_LOC
+#define RTE_USART0_CTS_PORT_ID 0
+
+#if (RTE_USART0_CTS_PORT_ID == 0)
+#define RTE_USART0_CTS_PORT HP
+#define RTE_USART0_CTS_PIN 6
+#define RTE_USART0_CTS_MUX 2
+#define RTE_USART0_CTS_PAD 1
+#elif (RTE_USART0_CTS_PORT_ID == 1)
+#define RTE_USART0_CTS_PORT HP
+#define RTE_USART0_CTS_PIN 26
+#define RTE_USART0_CTS_MUX 2
+#define RTE_USART0_CTS_PAD 0 //NO PAD
+#elif (RTE_USART0_CTS_PORT_ID == 2)
+#define RTE_USART0_CTS_PORT HP
+#define RTE_USART0_CTS_PIN 56
+#define RTE_USART0_CTS_MUX 2
+#define RTE_USART0_CTS_PAD 20
+#elif (RTE_USART0_CTS_PORT_ID == 3)
+#define RTE_USART0_CTS_PORT HP
+#define RTE_USART0_CTS_PIN 70
+#define RTE_USART0_CTS_MUX 2
+#define RTE_USART0_CTS_PAD 28
+#else
+#error "Invalid USART0 RTE_USART0_CTS_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_USART0_CTS_PORT HP
+#if (USART0_CTS_LOC == 14)
+#define RTE_USART0_CTS_PIN USART0_CTS_PIN
+#define RTE_USART0_CTS_MUX 2
+#define RTE_USART0_CTS_PAD 1
+#endif
+#if (USART0_CTS_LOC == 15)
+#define RTE_USART0_CTS_PIN USART0_CTS_PIN
+#define RTE_USART0_CTS_MUX 2
+#define RTE_USART0_CTS_PAD 0 //NO PAD
+#endif
+#if (USART0_CTS_LOC == 16)
+#define RTE_USART0_CTS_PIN USART0_CTS_PIN
+#define RTE_USART0_CTS_MUX 2
+#define RTE_USART0_CTS_PAD 20
+#endif
+#if (USART0_CTS_LOC == 17)
+#define RTE_USART0_CTS_PIN (USART0_CTS_PIN + GPIO_MAX_PIN)
+#define RTE_USART0_CTS_MUX 2
+#define RTE_USART0_CTS_PAD 28
+#endif
+//Pintool data
+#endif
+
+// USART0_RTS <0=>P0_9 <1=>P0_28 <2=>P0_53 <3=>P0_69
+// RTS for USART0
+#ifndef USART0_RTS_LOC
+#define RTE_USART0_RTS_PORT_ID 0
+
+#if (RTE_USART0_RTS_PORT_ID == 0)
+#define RTE_USART0_RTS_PORT HP
+#define RTE_USART0_RTS_PIN 9
+#define RTE_USART0_RTS_MUX 2
+#define RTE_USART0_RTS_PAD 4
+#elif (RTE_USART0_RTS_PORT_ID == 1)
+#define RTE_USART0_RTS_PORT HP
+#define RTE_USART0_RTS_PIN 28
+#define RTE_USART0_RTS_MUX 2
+#define RTE_USART0_RTS_PAD 0 //NO PAD
+#elif (RTE_USART0_RTS_PORT_ID == 2)
+#define RTE_USART0_RTS_PORT HP
+#define RTE_USART0_RTS_PIN 53
+#define RTE_USART0_RTS_MUX 2
+#define RTE_USART0_RTS_PAD 17
+#else
+#error "Invalid USART0 RTE_USART0_RTS_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_USART0_RTS_PORT HP
+#if (USART0_RTS_LOC == 18)
+#define RTE_USART0_RTS_PIN USART0_RTS_PIN
+#define RTE_USART0_RTS_MUX 2
+#define RTE_USART0_RTS_PAD 4
+#endif
+#if (USART0_RTS_LOC == 19)
+#define RTE_USART0_RTS_PIN USART0_RTS_PIN
+#define RTE_USART0_RTS_MUX 2
+#define RTE_USART0_RTS_PAD 0 //NO PAD
+#endif
+#if (USART0_RTS_LOC == 20)
+#define RTE_USART0_RTS_PIN USART0_RTS_PIN
+#define RTE_USART0_RTS_MUX 2
+#define RTE_USART0_RTS_PAD 17
+#endif
+#if (USART0_RTS_LOC == 21)
+#define RTE_USART0_RTS_PIN (USART0_RTS_PIN + GPIO_MAX_PIN)
+#define RTE_USART0_RTS_MUX 2
+#define RTE_USART0_RTS_PAD 27
+#endif
+//Pintool data
+#endif
+
+// USART0_IR_TX <0=>P0_48 <1=>P0_72
+// IR TX for USART0
+#ifndef USART0_IRTX_LOC
+#define RTE_IR_TX_PORT_ID 0
+#if ((RTE_IR_TX_PORT_ID == 2))
+#error "Invalid USART0 RTE_USART0_IR_TX_PIN Pin Configuration!"
+#endif
+
+#if (RTE_IR_TX_PORT_ID == 0)
+#define RTE_USART0_IR_TX_PORT HP
+#define RTE_USART0_IR_TX_PIN 48
+#define RTE_USART0_IR_TX_MUX 2
+#define RTE_USART0_IR_TX_PAD 12
+#elif (RTE_IR_TX_PORT_ID == 1)
+#define RTE_USART0_IR_TX_PORT HP
+#define RTE_USART0_IR_TX_PIN 72
+#define RTE_USART0_IR_TX_MUX 2
+#define RTE_USART0_IR_TX_PAD 30
+#elif (RTE_IR_TX_PORT_ID == 2)
+#define RTE_USART0_IR_TX_PORT HP
+#define RTE_USART0_IR_TX_PIN 26
+#define RTE_USART0_IR_TX_MUX 13
+#define RTE_USART0_IR_TX_PAD 0 //No pad
+#else
+#error "Invalid USART0 RTE_USART0_IR_TX_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_USART0_IR_TX_PORT HP
+#if (USART0_IRTX_LOC == 22)
+#define RTE_USART0_IR_TX_PIN USART0_IRTX_PIN
+#define RTE_USART0_IR_TX_MUX 13
+#define RTE_USART0_IR_TX_PAD 0 //No pad
+#endif
+#if (USART0_IRTX_LOC == 23)
+#define RTE_USART0_IR_TX_PIN USART0_IRTX_PIN
+#define RTE_USART0_IR_TX_MUX 2
+#define RTE_USART0_IR_TX_PAD 12
+#endif
+#if (USART0_IRTX_LOC == 24)
+#define RTE_USART0_IR_TX_PIN (USART0_IRTX_PIN + GPIO_MAX_PIN)
+#define RTE_USART0_IR_TX_MUX 11
+#define RTE_USART0_IR_TX_PAD 23
+#endif
+#if (USART0_IRTX_LOC == 25)
+#define RTE_USART0_IR_TX_PIN (USART0_IRTX_PIN + GPIO_MAX_PIN)
+#define RTE_USART0_IR_TX_MUX 2
+#define RTE_USART0_IR_TX_PAD 30
+#endif
+//Pintool data
+#endif
+
+// USART0_IR_RX <0=>P0_47 <1=>P0_71 <2=>P0_64 <3=>P0_25
+// IR RX for USART0
+#ifndef USART0_IRRX_LOC
+#define RTE_IR_RX_PORT_ID 0
+#if ((RTE_IR_RX_PORT_ID == 2))
+#error "Invalid USART0 RTE_USART0_IR_RX_PIN Pin Configuration!"
+#endif
+
+#if (RTE_IR_RX_PORT_ID == 0)
+#define RTE_USART0_IR_RX_PORT HP
+#define RTE_USART0_IR_RX_PIN 47
+#define RTE_USART0_IR_RX_MUX 2
+#define RTE_USART0_IR_RX_PAD 11
+#elif (RTE_IR_RX_PORT_ID == 1)
+#define RTE_USART0_IR_RX_PORT HP
+#define RTE_USART0_IR_RX_PIN 71
+#define RTE_USART0_IR_RX_MUX 2
+#define RTE_USART0_IR_RX_PAD 29
+#elif (RTE_IR_RX_PORT_ID == 2)
+#define RTE_USART0_IR_RX_PORT HP
+#define RTE_USART0_IR_RX_PIN 25
+#define RTE_USART0_IR_RX_MUX 13
+#define RTE_USART0_IR_RX_PAD 0 //no pad
+#else
+#error "Invalid USART0 RTE_USART0_IR_RX_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_USART0_IR_RX_PORT HP
+#if (USART0_IRRX_LOC == 26)
+#define RTE_USART0_IR_RX_PIN USART0_IRRX_PIN
+#define RTE_USART0_IR_RX_MUX 13
+#define RTE_USART0_IR_RX_PAD 0 //no pad
+#endif
+#if (USART0_IRRX_LOC == 27)
+#define RTE_USART0_IR_RX_PIN USART0_IRRX_PIN
+#define RTE_USART0_IR_RX_MUX 2
+#define RTE_USART0_IR_RX_PAD 11
+#endif
+#if (USART0_IRRX_LOC == 28)
+#define RTE_USART0_IR_RX_PIN (USART0_IRRX_PIN + GPIO_MAX_PIN)
+#define RTE_USART0_IR_RX_MUX 11
+#define RTE_USART0_IR_RX_PAD 22
+#endif
+#if (USART0_IRRX_LOC == 29)
+#define RTE_USART0_IR_RX_PIN (USART0_IRRX_PIN + GPIO_MAX_PIN)
+#define RTE_USART0_IR_RX_MUX 2
+#define RTE_USART0_IR_RX_PAD 29
+#endif
+//Pintool data
+#endif
+
+// USART0_RI <0=>P0_27 <1=>P0_46 <2=>P0_68
+// RI for USART0
+#ifndef USART0_RI_LOC
+#define RTE_RI_PORT_ID 0
+
+#if (RTE_RI_PORT_ID == 0)
+#define RTE_USART0_RI_PORT HP
+#define RTE_USART0_RI_PIN 27
+#define RTE_USART0_RI_MUX 2
+#define RTE_USART0_RI_PAD 0 //no pad
+#elif (RTE_RI_PORT_ID == 1)
+#define RTE_USART0_RI_PORT HP
+#define RTE_USART0_RI_PIN 46
+#define RTE_USART0_RI_MUX 2
+#define RTE_USART0_RI_PAD 10
+#else
+#error "Invalid USART0 RTE_USART0_RI_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_USART0_RI_PORT HP
+#if (USART0_RI_LOC == 30)
+#define RTE_USART0_RI_PIN USART0_RI_PIN
+#define RTE_USART0_RI_MUX 2
+#define RTE_USART0_RI_PAD 0 //no pad
+#endif
+#if (USART0_RI_LOC == 31)
+#define RTE_USART0_RI_PIN USART0_RI_PIN
+#define RTE_USART0_RI_MUX 2
+#define RTE_USART0_RI_PAD 10
+#endif
+#if (USART0_RI_LOC == 32)
+#define RTE_USART0_RI_PIN (USART0_RI_PIN + GPIO_MAX_PIN)
+#define RTE_USART0_RI_MUX 11
+#define RTE_USART0_RI_PAD 26
+#endif
+//Pintool data
+#endif
+
+// USART0_DSR <0=>P0_11 <1=>P0_57
+// DSR for USART0
+#ifndef USART0_DSR_LOC
+#define RTE_DSR_PORT_ID 0
+
+#if (RTE_DSR_PORT_ID == 0)
+#define RTE_USART0_DSR_PORT HP
+#define RTE_USART0_DSR_PIN 11
+#define RTE_USART0_DSR_MUX 2
+#define RTE_USART0_DSR_PAD 6
+#elif (RTE_DSR_PORT_ID == 1)
+#define RTE_USART0_DSR_PORT HP
+#define RTE_USART0_DSR_PIN 57
+#define RTE_USART0_DSR_MUX 2
+#define RTE_USART0_DSR_PAD 21
+#else
+#error "Invalid USART0 RTE_USART0_RI_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_USART0_DSR_PORT HP
+#define RTE_USART0_DSR_PIN USART0_DSR_PIN
+#if (USART0_DSR_LOC == 33)
+#define RTE_USART0_DSR_MUX 2
+#define RTE_USART0_DSR_PAD 6
+#endif
+#if (USART0_DSR_LOC == 34)
+#define RTE_USART0_DSR_MUX 2
+#define RTE_USART0_DSR_PAD 21
+#endif
+//Pintool data
+#endif
+
+// USART0_DCD <0=>P0_12 <1=>P0_29
+// DCD for USART0
+#ifndef USART0_DCD_LOC
+#define RTE_USART0_DCD_PORT HP
+#define RTE_USART0_DCD_PIN 12
+#else
+#define RTE_USART0_DCD_PORT HP
+#define RTE_USART0_DCD_PIN USART0_DCD_PIN
+#if (USART0_DCD_LOC == 35)
+#define RTE_USART0_DCD_MUX 2
+#define RTE_USART0_DCD_PAD 7
+#elif (USART0_DCD_LOC == 36)
+#define RTE_USART0_DCD_MUX 12
+#define RTE_USART0_DCD_PAD 0
+#endif
+#endif
+
+// USART0_DTR <0=>P0_7
+// DTR for USART0
+#ifndef USART0_DTR_LOC
+#define RTE_USART0_DTR_PORT HP
+#define RTE_USART0_DTR_PIN 7
+#else
+#define RTE_USART0_DTR_PORT HP
+#define RTE_USART0_DTR_PIN USART0_DTR_PIN
+#endif
+#define RTE_USART0_DTR_MUX 2
+#define RTE_USART0_DTR_PAD 2
+//
+
+// UART1 [Driver_UART1]
+// Configuration settings for Driver_UART1 in component ::CMSIS Driver:USART
+#define RTE_UART1 1
+
+#define RTE_UART1_CLK_SRC USART_ULPREFCLK
+#define RTE_UART1_CLK_DIV_FACT 1
+#define RTE_UART1_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER
+
+#define RTE_UART1_LOOPBACK 0
+#define RTE_UART1_DMA_MODE1_EN 0
+
+#define RTE_UART1_TX_FIFO_THRESHOLD USART_TRIGGER_TX_EMPTY
+#define RTE_UART1_RX_FIFO_THRESHOLD USART_TRIGGER_RX_AEMPTY
+
+#define RTE_UART1_DMA_TX_LEN_PER_DES 1024
+#define RTE_UART1_DMA_RX_LEN_PER_DES 1024
+
+#define RTE_UART1_CHNL_UDMA_TX_CH 27
+
+#define RTE_UART1_CHNL_UDMA_RX_CH 26
+
+/*UART1 PINS*/
+// UART1_TX <0=>P0_7 <1=>P0_30 <2=>P0_67 <3=>P0_69 <4=>P0_73 <5=>P0_75 <6=>P0_34
+// TX of UART1
+#ifndef UART1_TX_LOC
+#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
+#define RTE_UART1_TX_PORT_ID 0
+#else
+#define RTE_UART1_TX_PORT_ID 0
+
+#if ((RTE_UART1_TX_PORT_ID == 6))
+#error "Invalid UART1 RTE_UART1_TX_PIN Configuration!"
+#endif
+#endif
+
+#if (RTE_UART1_TX_PORT_ID == 0)
+#define RTE_UART1_TX_PORT HP
+#define RTE_UART1_TX_PIN 7
+#define RTE_UART1_TX_MUX 6
+#define RTE_UART1_TX_PAD 2
+#elif (RTE_UART1_TX_PORT_ID == 1)
+#define RTE_UART1_TX_PORT HP
+#define RTE_UART1_TX_PIN 30
+#define RTE_UART1_TX_MUX 6
+#define RTE_UART1_TX_PAD 0 //no pad
+#elif (RTE_UART1_TX_PORT_ID == 2)
+#define RTE_UART1_TX_PORT HP
+#define RTE_UART1_TX_PIN 67
+#define RTE_UART1_TX_MUX 9
+#define RTE_UART1_TX_PAD 25
+#elif (RTE_UART1_TX_PORT_ID == 3)
+#define RTE_UART1_TX_PORT HP
+#define RTE_UART1_TX_PIN 73
+#define RTE_UART1_TX_MUX 6
+#define RTE_UART1_TX_PAD 31
+#elif (RTE_UART1_TX_PORT_ID == 4)
+#define RTE_UART1_TX_PORT HP
+#define RTE_UART1_TX_PIN 75
+#define RTE_UART1_TX_MUX 9
+#define RTE_UART1_TX_PAD 33
+#else
+#error "Invalid UART1 RTE_UART1_TX_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_UART1_TX_PORT HP
+#if (UART1_TX_LOC == 0)
+#define RTE_UART1_TX_PIN UART1_TX_PIN
+#define RTE_UART1_TX_MUX 6
+#define RTE_UART1_TX_PAD 2
+#endif
+#if (UART1_TX_LOC == 1)
+#define RTE_UART1_TX_PIN UART1_TX_PIN
+#define RTE_UART1_TX_MUX 6
+#define RTE_UART1_TX_PAD 0 //no pad
+#endif
+#if (UART1_TX_LOC == 2)
+#define RTE_UART1_TX_PIN (UART1_TX_PIN + GPIO_MAX_PIN)
+#define RTE_UART1_TX_MUX 6
+#define RTE_UART1_TX_PAD 27
+#endif
+#if (UART1_TX_LOC == 3)
+#define RTE_UART1_TX_PIN (UART1_TX_PIN + GPIO_MAX_PIN)
+#define RTE_UART1_TX_MUX 6
+#define RTE_UART1_TX_PAD 31
+#endif
+#if (UART1_TX_LOC == 4)
+#define RTE_UART1_TX_PIN (UART1_TX_PIN + GPIO_MAX_PIN)
+#define RTE_UART1_TX_MUX 9
+#define RTE_UART1_TX_PAD 33
+#endif
+//Pintool data
+#endif
+
+// UART1_RX <0=>P0_6 <1=>P0_29 <2=>P0_66 <3=>P0_68 <4=>P0_72 <5=>P0_74 <6=>P0_33
+// RX of UART1
+#ifndef UART1_RX_LOC
+#define RTE_UART1_RX_PORT_ID 0
+
+#if (RTE_UART1_RX_PORT_ID == 0)
+#define RTE_UART1_RX_PORT HP
+#define RTE_UART1_RX_PIN 6
+#define RTE_UART1_RX_MUX 6
+#define RTE_UART1_RX_PAD 1
+#elif (RTE_UART1_RX_PORT_ID == 1)
+#define RTE_UART1_RX_PORT HP
+#define RTE_UART1_RX_PIN 29
+#define RTE_UART1_RX_MUX 6
+#define RTE_UART1_RX_PAD 0 //no pad
+#elif (RTE_UART1_RX_PORT_ID == 2)
+#define RTE_UART1_RX_PORT HP
+#define RTE_UART1_RX_PIN 66
+#define RTE_UART1_RX_MUX 9
+#define RTE_UART1_RX_PAD 24
+#elif (RTE_UART1_RX_PORT_ID == 3)
+#define RTE_UART1_RX_PORT HP
+#define RTE_UART1_RX_PIN 72
+#define RTE_UART1_RX_MUX 6
+#define RTE_UART1_RX_PAD 30
+#elif (RTE_UART1_RX_PORT_ID == 4)
+#define RTE_UART1_RX_PORT HP
+#define RTE_UART1_RX_PIN 74
+#define RTE_UART1_RX_MUX 9
+#define RTE_UART1_RX_PAD 32
+#else
+#error "Invalid UART1 RTE_UART1_RX_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_UART1_RX_PORT HP
+#if (UART1_RX_LOC == 5)
+#define RTE_UART1_RX_PIN UART1_RX_PIN
+#define RTE_UART1_RX_MUX 6
+#define RTE_UART1_RX_PAD 1
+#endif
+#if (UART1_RX_LOC == 6)
+#define RTE_UART1_RX_PIN UART1_RX_PIN
+#define RTE_UART1_RX_MUX 6
+#define RTE_UART1_RX_PAD 0 //no pad
+#endif
+#if (UART1_RX_LOC == 7)
+#define RTE_UART1_RX_PIN (UART1_RX_PIN + GPIO_MAX_PIN)
+#define RTE_UART1_RX_MUX 6
+#define RTE_UART1_RX_PAD 26
+#endif
+#if (UART1_RX_LOC == 8)
+#define RTE_UART1_RX_PIN (UART1_RX_PIN + GPIO_MAX_PIN)
+#define RTE_UART1_RX_MUX 6
+#define RTE_UART1_RX_PAD 30
+#endif
+#if (UART1_RX_LOC == 9)
+#define RTE_UART1_RX_PIN (UART1_RX_PIN + GPIO_MAX_PIN)
+#define RTE_UART1_RX_MUX 9
+#define RTE_UART1_RX_PAD 32
+#endif
+//Pintool data
+#endif
+
+// UART1_CTS <0=>P0_11 <1=>P0_28 <2=>P0_51 <3=>P0_65 <4=>P0_71 <5=>P0_73 <6=>P0_32
+// CTS of UART1
+#ifndef UART1_CTS_LOC
+#define RTE_UART1_CTS_PORT_ID 0
+
+#if (RTE_UART1_CTS_PORT_ID == 0)
+#define RTE_UART1_CTS_PORT HP
+#define RTE_UART1_CTS_PIN 11
+#define RTE_UART1_CTS_MUX 6
+#define RTE_UART1_CTS_PAD 6
+#elif (RTE_UART1_CTS_PORT_ID == 1)
+#define RTE_UART1_CTS_PORT HP
+#define RTE_UART1_CTS_PIN 28
+#define RTE_UART1_CTS_MUX 6
+#define RTE_UART1_CTS_PAD 0 //no pad
+#elif (RTE_UART1_CTS_PORT_ID == 2)
+#define RTE_UART1_CTS_PORT HP
+#define RTE_UART1_CTS_PIN 51
+#define RTE_UART1_CTS_MUX 9
+#define RTE_UART1_CTS_PAD 15
+#elif (RTE_UART1_CTS_PORT_ID == 3)
+#define RTE_UART1_CTS_PORT HP
+#define RTE_UART1_CTS_PIN 65
+#define RTE_UART1_CTS_MUX 9
+#define RTE_UART1_CTS_PAD 23
+#elif (RTE_UART1_CTS_PORT_ID == 4)
+#define RTE_UART1_CTS_PORT HP
+#define RTE_UART1_CTS_PIN 71
+#define RTE_UART1_CTS_MUX 6
+#define RTE_UART1_CTS_PAD 29
+#else
+#error "Invalid UART1 RTE_UART1_CTS_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_UART1_CTS_PORT HP
+#if (UART1_CTS_LOC == 10)
+#define RTE_UART1_CTS_PIN UART1_CTS_PIN
+#define RTE_UART1_CTS_MUX 6
+#define RTE_UART1_CTS_PAD 6
+#endif
+#if (UART1_CTS_LOC == 11)
+#define RTE_UART1_CTS_PIN UART1_CTS_PIN
+#define RTE_UART1_CTS_MUX 6
+#define RTE_UART1_CTS_PAD 0 //no pad
+#endif
+#if (UART1_CTS_LOC == 12)
+#define RTE_UART1_CTS_PIN UART1_CTS_PIN
+#define RTE_UART1_CTS_MUX 9
+#define RTE_UART1_CTS_PAD 15
+#endif
+#if (UART1_CTS_LOC == 13)
+#define RTE_UART1_CTS_PIN (UART1_CTS_PIN + GPIO_MAX_PIN)
+#define RTE_UART1_CTS_MUX 9
+#define RTE_UART1_CTS_PAD 23
+#endif
+#if (UART1_CTS_LOC == 14)
+#define RTE_UART1_CTS_PIN (UART1_CTS_PIN + GPIO_MAX_PIN)
+#define RTE_UART1_CTS_MUX 6
+#define RTE_UART1_CTS_PAD 29
+#endif
+#if (UART1_CTS_LOC == 15)
+#define RTE_UART1_CTS_PIN (UART1_CTS_PIN + GPIO_MAX_PIN)
+#define RTE_UART1_CTS_MUX 9
+#define RTE_UART1_CTS_PAD 31
+#endif
+//Pintool data
+#endif
+
+// UART1_RTS <0=>P0_10 <1=>P0_27 <2=>P0_50 <3=>P0_64 <4=>P0_70 <5=>P0_72 <6=>P0_31
+// RTS of UART1
+#ifndef UART1_RTS_LOC
+#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
+#define RTE_UART1_RTS_PORT_ID 0
+#else
+#define RTE_UART1_RTS_PORT_ID 0
+#endif
+
+#if (RTE_UART1_RTS_PORT_ID == 0)
+#define RTE_UART1_RTS_PORT HP
+#define RTE_UART1_RTS_PIN 10
+#define RTE_UART1_RTS_MUX 6
+#define RTE_UART1_RTS_PAD 5
+#elif (RTE_UART1_RTS_PORT_ID == 1)
+#define RTE_UART1_RTS_PORT HP
+#define RTE_UART1_RTS_PIN 27
+#define RTE_UART1_RTS_MUX 6
+#define RTE_UART1_RTS_PAD 0 //no pad
+#elif (RTE_UART1_RTS_PORT_ID == 2)
+#define RTE_UART1_RTS_PORT HP
+#define RTE_UART1_RTS_PIN 50
+#define RTE_UART1_RTS_MUX 9
+#define RTE_UART1_RTS_PAD 14
+#elif (RTE_UART1_RTS_PORT_ID == 3)
+#define RTE_UART1_RTS_PORT HP
+#define RTE_UART1_RTS_PIN 70
+#define RTE_UART1_RTS_MUX 6
+#define RTE_UART1_RTS_PAD 28
+#elif (RTE_UART1_RTS_PORT_ID == 4)
+#define RTE_UART1_RTS_PORT HP
+#define RTE_UART1_RTS_PIN 72
+#define RTE_UART1_RTS_MUX 9
+#define RTE_UART1_RTS_PAD 30
+#else
+#error "Invalid UART1 RTE_UART1_RTS_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_UART1_RTS_PORT HP
+#if (UART1_RTS_LOC == 16)
+#define RTE_UART1_RTS_PIN UART1_RTS_PIN
+#define RTE_UART1_RTS_MUX 6
+#define RTE_UART1_RTS_PAD 5
+#endif
+#if (UART1_RTS_LOC == 17)
+#define RTE_UART1_RTS_PIN UART1_RTS_PIN
+#define RTE_UART1_RTS_MUX 6
+#define RTE_UART1_RTS_PAD 0 //no pad
+#endif
+#if (UART1_RTS_LOC == 18)
+#define RTE_UART1_RTS_PIN UART1_RTS_PIN
+#define RTE_UART1_RTS_MUX 9
+#define RTE_UART1_RTS_PAD 14
+#endif
+#if (UART1_RTS_LOC == 19)
+#define RTE_UART1_RTS_PIN (UART1_RTS_PIN + GPIO_MAX_PIN)
+#define RTE_UART1_RTS_MUX 9
+#define RTE_UART1_RTS_PAD 22
+#endif
+#if (UART1_RTS_LOC == 20)
+#define RTE_UART1_RTS_PIN (UART1_RTS_PIN + GPIO_MAX_PIN)
+#define RTE_UART1_RTS_MUX 6
+#define RTE_UART1_RTS_PAD 28
+#endif
+#if (UART1_RTS_LOC == 21)
+#define RTE_UART1_RTS_PIN (UART1_RTS_PIN + GPIO_MAX_PIN)
+#define RTE_UART1_RTS_MUX 9
+#define RTE_UART1_RTS_PAD 30
+#endif
+//Pintool data
+#endif
+
+//
+
+// ULP_UART [Driver_ULP_UART]
+// Configuration settings for Driver_ULP_UART in component ::CMSIS Driver:USART
+#define RTE_ULP_UART 1
+
+#define RTE_ULP_UART_CLK_SRC ULP_UART_REF_CLK
+#define RTE_ULP_UART_CLK_DIV_FACT 0
+#define RTE_ULP_UART_FRAC_SEL USART_FRACTIONAL_DIVIDER
+
+#define RTE_ULP_UART_LOOPBACK 0
+#define RTE_ULP_UART_DMA_MODE1_EN 0
+
+#define RTE_ULP_UART_TX_FIFO_THRESHOLD USART_TRIGGER_TX_EMPTY
+#define RTE_ULP_UART_RX_FIFO_THRESHOLD USART_TRIGGER_RX_AEMPTY
+
+#define RTE_ULP_UART_DMA_TX_LEN_PER_DES 1024
+#define RTE_ULP_UART_DMA_RX_LEN_PER_DES 1024
+
+#define RTE_ULPUART_CHNL_UDMA_TX_CH 1
+
+#define RTE_ULPUART_CHNL_UDMA_RX_CH 0
+
+/*ULPSS UART PINS*/
+// UART1_TX <0=>P0_3 <1=>P0_7 <2=>P0_11
+// TX of ULPSS UART
+#ifndef ULP_UART_TX_LOC
+#define RTE_ULP_UART_TX_PORT_ID 1
+#if (RTE_ULP_UART_TX_PORT_ID == 0)
+#define RTE_ULP_UART_TX_PORT RTE_ULP_PORT
+#define RTE_ULP_UART_TX_PIN (7 + GPIO_MAX_PIN)
+#define RTE_ULP_UART_TX_MUX 3
+#define RTE_ULP_UART_TX_PAD 0
+#elif (RTE_ULP_UART_TX_PORT_ID == 1)
+#define RTE_ULP_UART_TX_PORT RTE_ULP_PORT
+#define RTE_ULP_UART_TX_PIN (11 + GPIO_MAX_PIN)
+#define RTE_ULP_UART_TX_MUX 3
+#define RTE_ULP_UART_TX_PAD 0
+#elif (RTE_ULP_UART_TX_PORT_ID == 2)
+#define RTE_ULP_UART_TX_PORT RTE_ULP_PORT
+#define RTE_ULP_UART_TX_PIN 9
+#define RTE_ULP_UART_TX_MUX 3
+#define RTE_ULP_UART_TX_PAD 4
+#elif (RTE_ULP_UART_TX_PORT_ID == 3)
+#define RTE_ULP_UART_TX_PORT RTE_ULP_PORT
+#define RTE_ULP_UART_TX_PIN 15
+#define RTE_ULP_UART_TX_MUX 3
+#define RTE_ULP_UART_TX_PAD 8
+#elif (RTE_ULP_UART_TX_PORT_ID == 4)
+#define RTE_ULP_UART_TX_PORT RTE_ULP_PORT
+#define RTE_ULP_UART_TX_PIN 49
+#define RTE_ULP_UART_TX_MUX 3
+#define RTE_ULP_UART_TX_PAD 13
+#else
+#error "Invalid ULPSS UART RTE_ULP_UART_TX_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_ULP_UART_TX_PORT RTE_ULP_PORT
+#define RTE_ULP_UART_TX_MUX 3
+#if ((ULP_UART_TX_LOC == 0) || (ULP_UART_TX_LOC == 1))
+#define RTE_ULP_UART_TX_PIN (ULP_UART_TX_PIN + GPIO_MAX_PIN)
+#define RTE_ULP_UART_TX_PAD 0
+#endif
+#if (ULP_UART_TX_LOC == 11)
+#define RTE_ULP_UART_TX_PIN ULP_UART_TX_PIN
+#define RTE_ULP_UART_TX_PAD 4
+#endif
+#if (ULP_UART_TX_LOC == 12)
+#define RTE_ULP_UART_TX_PIN ULP_UART_TX_PIN
+#define RTE_ULP_UART_TX_PAD 8
+#endif
+#if (ULP_UART_TX_LOC == 13)
+#define RTE_ULP_UART_TX_PIN ULP_UART_TX_PIN
+#define RTE_ULP_UART_TX_PAD 13
+#endif
+//Pintool data
+#endif
+
+// UART1_RX <0=>P0_2 <1=>P0_6 <2=>P0_9
+// RX of ULPSS UART
+#ifndef ULP_UART_RX_LOC
+#define RTE_ULP_UART_RX_PORT_ID 2
+#if (RTE_ULP_UART_RX_PORT_ID == 0)
+#define RTE_ULP_UART_RX_PORT RTE_ULP_PORT
+#define RTE_ULP_UART_RX_PIN (2 + GPIO_MAX_PIN)
+#define RTE_ULP_UART_RX_MUX 3
+#define RTE_ULP_UART_RX_PAD 0
+#elif (RTE_ULP_UART_RX_PORT_ID == 1)
+#define RTE_ULP_UART_RX_PORT RTE_ULP_PORT
+#define RTE_ULP_UART_RX_PIN (6 + GPIO_MAX_PIN)
+#define RTE_ULP_UART_RX_MUX 3
+#define RTE_ULP_UART_RX_PAD 0
+#elif (RTE_ULP_UART_RX_PORT_ID == 2)
+#define RTE_ULP_UART_RX_PORT RTE_ULP_PORT
+#define RTE_ULP_UART_RX_PIN (9 + GPIO_MAX_PIN)
+#define RTE_ULP_UART_RX_MUX 3
+#define RTE_ULP_UART_RX_PAD 0
+#elif (RTE_ULP_UART_RX_PORT_ID == 3)
+#define RTE_ULP_UART_RX_PORT RTE_ULP_PORT
+#define RTE_ULP_UART_RX_PIN 8
+#define RTE_ULP_UART_RX_MUX 3
+#define RTE_ULP_UART_RX_PAD 3
+#elif (RTE_ULP_UART_RX_PORT_ID == 4)
+#define RTE_ULP_UART_RX_PORT RTE_ULP_PORT
+#define RTE_ULP_UART_RX_PIN 12
+#define RTE_ULP_UART_RX_MUX 3
+#define RTE_ULP_UART_RX_PAD 7
+#elif (RTE_ULP_UART_RX_PORT_ID == 5)
+#define RTE_ULP_UART_RX_PORT RTE_ULP_PORT
+#define RTE_ULP_UART_RX_PIN 47
+#define RTE_ULP_UART_RX_MUX 3
+#define RTE_ULP_UART_RX_PAD 11
+#else
+#error "Invalid ULPSS UART RTE_ULP_UART_RX_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_ULP_UART_RX_PORT RTE_ULP_PORT
+#define RTE_ULP_UART_RX_MUX 3
+#if ((ULP_UART_RX_LOC == 2) || (ULP_UART_RX_LOC == 3) || (ULP_UART_RX_LOC == 10))
+#define RTE_ULP_UART_RX_PIN (ULP_UART_RX_PIN + GPIO_MAX_PIN)
+#define RTE_ULP_UART_RX_PAD 0
+#endif
+#if (ULP_UART_RX_LOC == 14)
+#define RTE_ULP_UART_RX_PIN ULP_UART_RX_PIN
+#define RTE_ULP_UART_RX_PAD 3
+#endif
+#if (ULP_UART_RX_LOC == 15)
+#define RTE_ULP_UART_RX_PIN ULP_UART_RX_PIN
+#define RTE_ULP_UART_RX_PAD 7
+#endif
+#if (ULP_UART_RX_LOC == 16)
+#define RTE_ULP_UART_RX_PIN ULP_UART_RX_PIN
+#define RTE_ULP_UART_RX_PAD 11
+#endif
+//Pintool data
+#endif
+
+// UART1_CTS <0=>P0_1 <1=>P0_5 <2=>P0_8
+// CTS of ULPSS UART
+#ifndef ULP_UART_CTS_LOC
+#define RTE_ULP_UART_CTS_PORT_ID 0
+#if (RTE_ULP_UART_CTS_PORT_ID == 0)
+#define RTE_ULP_UART_CTS_PORT RTE_ULP_PORT
+#define RTE_ULP_UART_CTS_PIN (1 + GPIO_MAX_PIN)
+#define RTE_ULP_UART_CTS_MUX 3
+#define RTE_ULP_UART_CTS_PAD 0
+#elif (RTE_ULP_UART_CTS_PORT_ID == 1)
+#define RTE_ULP_UART_CTS_PORT RTE_ULP_PORT
+#define RTE_ULP_UART_CTS_PIN (8 + GPIO_MAX_PIN)
+#define RTE_ULP_UART_CTS_MUX 3
+#define RTE_ULP_UART_CTS_PAD 0
+#elif (RTE_ULP_UART_CTS_PORT_ID == 2)
+#define RTE_ULP_UART_CTS_PORT RTE_ULP_PORT
+#define RTE_ULP_UART_CTS_PIN 7
+#define RTE_ULP_UART_CTS_MUX 3
+#define RTE_ULP_UART_CTS_PAD 2
+#elif (RTE_ULP_UART_CTS_PORT_ID == 3)
+#define RTE_ULP_UART_CTS_PORT RTE_ULP_PORT
+#define RTE_ULP_UART_CTS_PIN 11
+#define RTE_ULP_UART_CTS_MUX 3
+#define RTE_ULP_UART_CTS_PAD 6
+#elif (RTE_ULP_UART_CTS_PORT_ID == 4)
+#define RTE_ULP_UART_CTS_PORT RTE_ULP_PORT
+#define RTE_ULP_UART_CTS_PIN 46
+#define RTE_ULP_UART_CTS_MUX 3
+#define RTE_ULP_UART_CTS_PAD 10
+#else
+#error "Invalid ULPSS UART RTE_ULP_UART_CTS_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_ULP_UART_CTS_PORT RTE_ULP_PORT
+#define RTE_ULP_UART_CTS_MUX 3
+#if ((ULP_UART_CTS_LOC == 4) || (ULP_UART_CTS_LOC == 5) || (ULP_UART_CTS_LOC == 6))
+#define RTE_ULP_UART_CTS_PIN (ULP_UART_CTS_PIN + GPIO_MAX_PIN)
+#define RTE_ULP_UART_CTS_PAD 0
+#endif
+#if (ULP_UART_CTS_LOC == 17)
+#define RTE_ULP_UART_CTS_PIN ULP_UART_CTS_PIN
+#define RTE_ULP_UART_CTS_PAD 2
+#endif
+#if (ULP_UART_CTS_LOC == 18)
+#define RTE_ULP_UART_CTS_PIN ULP_UART_CTS_PIN
+#define RTE_ULP_UART_CTS_PAD 6
+#endif
+#if (ULP_UART_CTS_LOC == 19)
+#define RTE_ULP_UART_CTS_PIN ULP_UART_CTS_PIN
+#define RTE_ULP_UART_CTS_PAD 10
+#endif
+//Pintool data
+#endif
+
+// UART1_RTS <0=>P0_0 <1=>P0_4 <2=>P0_10
+// RTS of ULPSS UART
+#ifndef ULP_UART_RTS_LOC
+#define RTE_ULP_UART_RTS_PORT_ID 0
+#if (RTE_ULP_UART_RTS_PORT_ID == 0)
+#define RTE_ULP_UART_RTS_PORT RTE_ULP_PORT
+#define RTE_ULP_UART_RTS_PIN (10 + GPIO_MAX_PIN)
+#define RTE_ULP_UART_RTS_MUX 3
+#define RTE_ULP_UART_RTS_PAD 0
+#elif (RTE_ULP_UART_RTS_PORT_ID == 1)
+#define RTE_ULP_UART_RTS_PORT RTE_ULP_PORT
+#define RTE_ULP_UART_RTS_PIN 6
+#define RTE_ULP_UART_RTS_MUX 3
+#define RTE_ULP_UART_RTS_PAD 1
+#elif (RTE_ULP_UART_RTS_PORT_ID == 2)
+#define RTE_ULP_UART_RTS_PORT RTE_ULP_PORT
+#define RTE_ULP_UART_RTS_PIN 10
+#define RTE_ULP_UART_RTS_MUX 3
+#define RTE_ULP_UART_RTS_PAD 5
+#elif (RTE_ULP_UART_RTS_PORT_ID == 3)
+#define RTE_ULP_UART_RTS_PORT RTE_ULP_PORT
+#define RTE_ULP_UART_RTS_PIN 48
+#define RTE_ULP_UART_RTS_MUX 3
+#define RTE_ULP_UART_RTS_PAD 12
+#else
+#error "Invalid ULPSS UART RTE_ULP_UART_RTS_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_ULP_UART_RTS_PORT RTE_ULP_PORT
+#define RTE_ULP_UART_RTS_MUX 3
+#if ((ULP_UART_RTS_LOC == 7) || (ULP_UART_RTS_LOC == 8) || (ULP_UART_RTS_LOC == 9))
+#define RTE_ULP_UART_RTS_PIN (ULP_UART_RTS_PIN + GPIO_MAX_PIN)
+#define RTE_ULP_UART_RTS_PAD 0
+#endif
+#if (ULP_UART_RTS_LOC == 20)
+#define RTE_ULP_UART_RTS_PIN ULP_UART_RTS_PIN
+#define RTE_ULP_UART_RTS_PAD 1
+#endif
+#if (ULP_UART_RTS_LOC == 21)
+#define RTE_ULP_UART_RTS_PIN ULP_UART_RTS_PIN
+#define RTE_ULP_UART_RTS_PAD 5
+#endif
+#if (ULP_UART_RTS_LOC == 22)
+#define RTE_ULP_UART_RTS_PIN ULP_UART_RTS_PIN
+#define RTE_ULP_UART_RTS_PAD 12
+#endif
+//Pintool data
+#endif
+
+//
+
+// SSI_MASTER (Serial Peripheral Interface 1) [Driver_SSI_MASTER]
+// Configuration settings for Driver_SSI_MASTER in component ::CMSIS Driver:SPI
+#define RTE_SSI_MASTER 1
+
+// SSI_MASTER_MISO Pin <0=>GPIO_12 <1=>GPIO_27 <2=>GPIO_57
+#ifndef SSI_MASTER_DATA1_LOC
+#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
+#define RTE_SSI_MASTER_MISO_PORT_ID 1
+#else
+#define RTE_SSI_MASTER_MISO_PORT_ID 0
+#endif
+
+#if (RTE_SSI_MASTER_MISO_PORT_ID == 0)
+#define RTE_SSI_MASTER_MISO 1
+#define RTE_SSI_MASTER_MISO_PORT HP
+#define RTE_SSI_MASTER_MISO_PIN 12
+#define RTE_SSI_MASTER_MISO_MODE EGPIO_PIN_MUX_MODE3
+#define RTE_SSI_MASTER_MISO_PADSEL 7
+#elif (RTE_SSI_MASTER_MISO_PORT_ID == 1)
+#define RTE_SSI_MASTER_MISO 1
+#define RTE_SSI_MASTER_MISO_PORT HP
+#define RTE_SSI_MASTER_MISO_PIN 27
+#define RTE_SSI_MASTER_MISO_MODE EGPIO_PIN_MUX_MODE3
+#define RTE_SSI_MASTER_MISO_PADSEL 0 //NO PAD
+#elif (RTE_SSI_MASTER_MISO_PORT_ID == 2)
+#define RTE_SSI_MASTER_MISO 1
+#define RTE_SSI_MASTER_MISO_PORT HP
+#define RTE_SSI_MASTER_MISO_PIN 57
+#define RTE_SSI_MASTER_MISO_MODE EGPIO_PIN_MUX_MODE3
+#define RTE_SSI_MASTER_MISO_PADSEL 21
+#else
+#error "Invalid SSI_MASTER_MISO Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_SSI_MASTER_MISO 1
+#define RTE_SSI_MASTER_MISO_PORT HP
+#define RTE_SSI_MASTER_MISO_PIN SSI_MASTER_MISO_DATA1_PIN
+#define RTE_SSI_MASTER_MISO_MODE EGPIO_PIN_MUX_MODE3
+#if (SSI_MASTER_DATA1_LOC == 3)
+#define RTE_SSI_MASTER_MISO_PADSEL 7
+#endif
+#if (SSI_MASTER_DATA1_LOC == 4)
+#define RTE_SSI_MASTER_MISO_PADSEL 0 //NO PAD
+#endif
+#if (SSI_MASTER_DATA1_LOC == 5)
+#define RTE_SSI_MASTER_MISO_PADSEL 21
+#endif
+//Pintool data
+#endif
+
+// SSI_MASTER_MOSI Pin <0=>GPIO_11 <1=>GPIO_26 <2=>GPIO_56
+#ifndef SSI_MASTER_DATA0_LOC
+#define RTE_SSI_MASTER_MOSI_PORT_ID 1
+
+#if (RTE_SSI_MASTER_MOSI_PORT_ID == 0)
+#define RTE_SSI_MASTER_MOSI 1
+#define RTE_SSI_MASTER_MOSI_PORT HP
+#define RTE_SSI_MASTER_MOSI_PIN 11
+#define RTE_SSI_MASTER_MOSI_MODE EGPIO_PIN_MUX_MODE3
+#define RTE_SSI_MASTER_MOSI_PADSEL 6
+#elif (RTE_SSI_MASTER_MOSI_PORT_ID == 1)
+#define RTE_SSI_MASTER_MOSI 1
+#define RTE_SSI_MASTER_MOSI_PORT HP
+#define RTE_SSI_MASTER_MOSI_PIN 26
+#define RTE_SSI_MASTER_MOSI_MODE EGPIO_PIN_MUX_MODE3
+#define RTE_SSI_MASTER_MOSI_PADSEL 0 //NO PAD
+#elif (RTE_SSI_MASTER_MOSI_PORT_ID == 2)
+#define RTE_SSI_MASTER_MOSI 1
+#define RTE_SSI_MASTER_MOSI_PORT HP
+#define RTE_SSI_MASTER_MOSI_PIN 56
+#define RTE_SSI_MASTER_MOSI_MODE EGPIO_PIN_MUX_MODE3
+#define RTE_SSI_MASTER_MOSI_PADSEL 20
+#else
+#error "Invalid SSI_MASTER_MOSI Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_SSI_MASTER_MOSI 1
+#define RTE_SSI_MASTER_MOSI_PORT HP
+#define RTE_SSI_MASTER_MOSI_PIN SSI_MASTER_MOSI_DATA0_PIN
+#define RTE_SSI_MASTER_MOSI_MODE EGPIO_PIN_MUX_MODE3
+#if (SSI_MASTER_DATA0_LOC == 0)
+#define RTE_SSI_MASTER_MOSI_PADSEL 6
+#endif
+#if (SSI_MASTER_DATA0_LOC == 1)
+#define RTE_SSI_MASTER_MOSI_PADSEL 0 //NO PAD
+#endif
+#if (SSI_MASTER_DATA0_LOC == 2)
+#define RTE_SSI_MASTER_MOSI_PADSEL 20
+#endif
+//Pintool data
+#endif
+
+// SSI_MASTER_DATA2 Pin <0=>GPIO_6 <1=>GPIO_29 <2=>GPIO_54
+#ifndef SSI_MASTER_DATA2_LOC
+#define RTE_SSI_MASTER_DATA2_PORT_ID 1
+
+#if (RTE_SSI_MASTER_DATA2_PORT_ID == 0)
+#define RTE_SSI_MASTER_DATA2 1
+#define RTE_SSI_MASTER_DATA2_PORT HP
+#define RTE_SSI_MASTER_DATA2_PIN 6
+#define RTE_SSI_MASTER_DATA2_MODE EGPIO_PIN_MUX_MODE3
+#define RTE_SSI_MASTER_DATA2_PADSEL 1
+#elif (RTE_SSI_MASTER_DATA2_PORT_ID == 1)
+#define RTE_SSI_MASTER_DATA2 1
+#define RTE_SSI_MASTER_DATA2_PORT HP
+#define RTE_SSI_MASTER_DATA2_PIN 29
+#define RTE_SSI_MASTER_DATA2_MODE EGPIO_PIN_MUX_MODE3
+#define RTE_SSI_MASTER_DATA2_PADSEL 0 //NO PAD
+#elif (RTE_SSI_MASTER_DATA2_PORT_ID == 2)
+#define RTE_SSI_MASTER_DATA2 1
+#define RTE_SSI_MASTER_DATA2_PORT HP
+#define RTE_SSI_MASTER_DATA2_PIN 54
+#define RTE_SSI_MASTER_DATA2_MODE EGPIO_PIN_MUX_MODE3
+#define RTE_SSI_MASTER_DATA2_PADSEL 18
+#else
+#error "Invalid SSI_MASTER_DATA2 Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_SSI_MASTER_DATA2 1
+#define RTE_SSI_MASTER_DATA2_PORT HP
+#define RTE_SSI_MASTER_DATA2_PIN SSI_MASTER_DATA2_PIN
+#define RTE_SSI_MASTER_DATA2_MODE EGPIO_PIN_MUX_MODE3
+#if (SSI_MASTER_DATA2_LOC == 16)
+#define RTE_SSI_MASTER_DATA2_PADSEL 1
+#endif
+#if (SSI_MASTER_DATA2_LOC == 17)
+#define RTE_SSI_MASTER_DATA2_PADSEL 0 //NO PAD
+#endif
+#if (SSI_MASTER_DATA2_LOC == 18)
+#define RTE_SSI_MASTER_DATA2_PADSEL 18
+#endif
+//Pintool data
+#endif
+
+// SSI_MASTER_DATA3 Pin <0=>GPIO_7 <1=>GPIO_30 <2=>GPIO_55
+#ifndef SSI_MASTER_DATA3_LOC
+#define RTE_SSI_MASTER_DATA3_PORT_ID 1
+
+#if (RTE_SSI_MASTER_DATA3_PORT_ID == 0)
+#define RTE_SSI_MASTER_DATA3 1
+#define RTE_SSI_MASTER_DATA3_PORT HP
+#define RTE_SSI_MASTER_DATA3_PIN 7
+#define RTE_SSI_MASTER_DATA3_MODE EGPIO_PIN_MUX_MODE3
+#define RTE_SSI_MASTER_DATA3_PADSEL 2
+#elif (RTE_SSI_MASTER_DATA3_PORT_ID == 1)
+#define RTE_SSI_MASTER_DATA3 1
+#define RTE_SSI_MASTER_DATA3_PORT HP
+#define RTE_SSI_MASTER_DATA3_PIN 30
+#define RTE_SSI_MASTER_DATA3_MODE EGPIO_PIN_MUX_MODE3
+#define RTE_SSI_MASTER_DATA3_PADSEL 0 //NO PAD
+#elif (RTE_SSI_MASTER_DATA3_PORT_ID == 2)
+#define RTE_SSI_MASTER_DATA3 1
+#define RTE_SSI_MASTER_DATA3_PORT HP
+#define RTE_SSI_MASTER_DATA3_PIN 55
+#define RTE_SSI_MASTER_DATA3_MODE EGPIO_PIN_MUX_MODE3
+#define RTE_SSI_MASTER_DATA3_PADSEL 19
+#else
+#error "Invalid SSI_MASTER_DATA3 Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_SSI_MASTER_DATA3 1
+#define RTE_SSI_MASTER_DATA3_PORT HP
+#define RTE_SSI_MASTER_DATA3_PIN SSI_MASTER_DATA3_PIN
+#define RTE_SSI_MASTER_DATA3_MODE EGPIO_PIN_MUX_MODE3
+#if (SSI_MASTER_DATA3_LOC == 19)
+#define RTE_SSI_MASTER_DATA3_PADSEL 2
+#endif
+#if (SSI_MASTER_DATA3_LOC == 20)
+#define RTE_SSI_MASTER_DATA3_PADSEL 0 //NO PAD
+#endif
+#if (SSI_MASTER_DATA3_LOC == 21)
+#define RTE_SSI_MASTER_DATA3_PADSEL 19
+#endif
+//Pintool data
+#endif
+
+// SSI_MASTER_SCK Pin <0=>GPIO_8 <1=>GPIO_25 <2=>GPIO_52
+#ifndef SSI_MASTER_SCK_LOC
+#define RTE_SSI_MASTER_SCK_PORT_ID 1
+
+#if (RTE_SSI_MASTER_SCK_PORT_ID == 0)
+#define RTE_SSI_MASTER_SCK 1
+#define RTE_SSI_MASTER_SCK_PORT HP
+#define RTE_SSI_MASTER_SCK_PIN 8
+#define RTE_SSI_MASTER_SCK_MODE EGPIO_PIN_MUX_MODE3
+#define RTE_SSI_MASTER_SCK_PADSEL 3
+#elif (RTE_SSI_MASTER_SCK_PORT_ID == 1)
+#define RTE_SSI_MASTER_SCK 1
+#define RTE_SSI_MASTER_SCK_PORT HP
+#define RTE_SSI_MASTER_SCK_PIN 25
+#define RTE_SSI_MASTER_SCK_MODE EGPIO_PIN_MUX_MODE3
+#define RTE_SSI_MASTER_SCK_PADSEL 0 //NO PAD
+#elif (RTE_SSI_MASTER_SCK_PORT_ID == 2)
+#define RTE_SSI_MASTER_SCK 1
+#define RTE_SSI_MASTER_SCK_PORT HP
+#define RTE_SSI_MASTER_SCK_PIN 52
+#define RTE_SSI_MASTER_SCK_MODE EGPIO_PIN_MUX_MODE3
+#define RTE_SSI_MASTER_SCK_PADSEL 16
+#else
+#error "Invalid SSI_MASTER_SCK Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_SSI_MASTER_SCK 1
+#define RTE_SSI_MASTER_SCK_PORT HP
+#define RTE_SSI_MASTER_SCK_PIN SSI_MASTER_SCK__PIN
+#define RTE_SSI_MASTER_SCK_MODE EGPIO_PIN_MUX_MODE3
+#if (SSI_MASTER_SCK_LOC == 6)
+#define RTE_SSI_MASTER_SCK_PADSEL 3
+#endif
+#if (SSI_MASTER_SCK_LOC == 7)
+#define RTE_SSI_MASTER_SCK_PADSEL 0 //NO PAD
+#endif
+#if (SSI_MASTER_SCK_LOC == 8)
+#define RTE_SSI_MASTER_SCK_PADSEL 16
+#endif
+//Pintool data
+#endif
+
+#define M4_SSI_CS0 1
+#define M4_SSI_CS1 1
+#define M4_SSI_CS2 1
+#define M4_SSI_CS3 1
+
+// SSI_MASTER_CS Pin <0=>GPIO_9 <1=>GPIO_28 <2=>GPIO_53 <3=>GPIO_10 <4=>GPIO_15 <5=>GPIO_50 <6=>GPIO_51
+#ifndef SSI_MASTER_CS0_LOC
+#define RTE_SSI_MASTER_CS0_PORT_ID 1
+
+#if (RTE_SSI_MASTER_CS0_PORT_ID == 0)
+#define RTE_SSI_MASTER_CS0 M4_SSI_CS0
+#define RTE_SSI_MASTER_CS0_PORT HP
+#define RTE_SSI_MASTER_CS0_PIN 9
+#define RTE_SSI_MASTER_CS0_MODE EGPIO_PIN_MUX_MODE3
+#define RTE_SSI_MASTER_CS0_PADSEL 4
+#elif (RTE_SSI_MASTER_CS0_PORT_ID == 1)
+#define RTE_SSI_MASTER_CS0 M4_SSI_CS0
+#define RTE_SSI_MASTER_CS0_PORT HP
+#define RTE_SSI_MASTER_CS0_PIN 28
+#define RTE_SSI_MASTER_CS0_MODE EGPIO_PIN_MUX_MODE3
+#define RTE_SSI_MASTER_CS0_PADSEL 0 //NO PAD
+#elif (RTE_SSI_MASTER_CS0_PORT_ID == 2)
+#define RTE_SSI_MASTER_CS0 M4_SSI_CS0
+#define RTE_SSI_MASTER_CS0_PORT HP
+#define RTE_SSI_MASTER_CS0_PIN 53
+#define RTE_SSI_MASTER_CS0_MODE EGPIO_PIN_MUX_MODE3
+#define RTE_SSI_MASTER_CS0_PADSEL 17
+#else
+#error "Invalid SSI_MASTER_CS0 Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_SSI_MASTER_CS0 M4_SSI_CS0
+#define RTE_SSI_MASTER_CS0_PORT HP
+#define RTE_SSI_MASTER_CS0_PIN SSI_MASTER_CS0__PIN
+#define RTE_SSI_MASTER_CS0_MODE EGPIO_PIN_MUX_MODE3
+#if (SSI_MASTER_CS0_LOC == 9)
+#define RTE_SSI_MASTER_CS0_PADSEL 4
+#endif
+#if (SSI_MASTER_CS0_LOC == 10)
+#define RTE_SSI_MASTER_CS0_PADSEL 0 //NO PAD
+#endif
+#if (SSI_MASTER_CS0_LOC == 11)
+#define RTE_SSI_MASTER_CS0_PADSEL 17
+#endif
+//Pintool data
+#endif
+
+//CS1
+#ifndef SSI_MASTER_CS1_LOC
+#define RTE_SSI_MASTER_CS1_PORT_ID 0
+#if (RTE_SSI_MASTER_CS1_PORT_ID == 0)
+#define RTE_SSI_MASTER_CS1_PORT HP
+#define RTE_SSI_MASTER_CS1_PIN 10
+#else
+#error "Invalid SSI_MASTER_CS1 Pin Configuration!"
+#endif
+#else
+#define RTE_SSI_MASTER_CS1_PORT HP
+#define RTE_SSI_MASTER_CS1_PIN SSI_MASTER_CS1__PIN
+#endif
+#define RTE_SSI_MASTER_CS1 M4_SSI_CS1
+#define RTE_SSI_MASTER_CS1_MODE EGPIO_PIN_MUX_MODE3
+#define RTE_SSI_MASTER_CS1_PADSEL 5
+
+//CS2
+#ifndef SSI_MASTER_CS2_LOC
+#define RTE_SSI_MASTER_CS2_PORT_ID 1
+#if (RTE_SSI_MASTER_CS2_PORT_ID == 0)
+#define RTE_SSI_MASTER_CS2 M4_SSI_CS2
+#define RTE_SSI_MASTER_CS2_PORT HP
+#define RTE_SSI_MASTER_CS2_PIN 15
+#define RTE_SSI_MASTER_CS2_MODE EGPIO_PIN_MUX_MODE3
+#define RTE_SSI_MASTER_CS2_PADSEL 8
+#elif (RTE_SSI_MASTER_CS2_PORT_ID == 1)
+#define RTE_SSI_MASTER_CS2 M4_SSI_CS2
+#define RTE_SSI_MASTER_CS2_PORT HP
+#define RTE_SSI_MASTER_CS2_PIN 50
+#define RTE_SSI_MASTER_CS2_MODE EGPIO_PIN_MUX_MODE3
+#define RTE_SSI_MASTER_CS2_PADSEL 14
+#else
+#error "Invalid SSI_MASTER_CS2 Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_SSI_MASTER_CS2 M4_SSI_CS2
+#define RTE_SSI_MASTER_CS2_PORT HP
+#define RTE_SSI_MASTER_CS2_PIN SSI_MASTER_CS2__PIN
+#define RTE_SSI_MASTER_CS2_MODE EGPIO_PIN_MUX_MODE3
+#if (SSI_MASTER_CS2_LOC == 13)
+#define RTE_SSI_MASTER_CS2_PADSEL 8
+#endif
+#if (SSI_MASTER_CS2_LOC == 14)
+#define RTE_SSI_MASTER_CS2_PADSEL 14
+#endif
+//Pintool data
+#endif
+
+//CS3
+#ifndef SSI_MASTER_CS3_LOC
+#define RTE_SSI_MASTER_CS3_PORT_ID 0
+#if (RTE_SSI_MASTER_CS3_PORT_ID == 0)
+#define RTE_SSI_MASTER_CS3_PORT HP
+#define RTE_SSI_MASTER_CS3_PIN 51
+#else
+#error "Invalid SSI_MASTER_CS3 Pin Configuration!"
+#endif
+#else
+#define RTE_SSI_MASTER_CS3_PORT HP
+#define RTE_SSI_MASTER_CS3_PIN SSI_MASTER_CS3__PIN
+#endif
+#define RTE_SSI_MASTER_CS3 M4_SSI_CS3
+#define RTE_SSI_MASTER_CS3_MODE EGPIO_PIN_MUX_MODE3
+#define RTE_SSI_MASTER_CS3_PADSEL 15
+
+// DMA Rx
+// Channel <28=>28
+// Selects DMA Channel (only Channel 28 can be used)
+//
+#define RTE_SSI_MASTER_UDMA_RX_CH 28
+
+// DMA Tx
+// Channel <29=>29
+// Selects DMA Channel (only Channel 29 can be used)
+//
+#define RTE_SSI_MASTER_UDMA_TX_CH 29
+//
+
+// SSI_SLAVE (Serial Peripheral Interface 2) [Driver_SSI_SLAVE]
+// Configuration settings for Driver_SSI_SLAVE in component ::CMSIS Driver:SPI
+#define RTE_SSI_SLAVE 1
+
+#define RTE_SSI_SLAVE_INPUT_CLOCK SSISLAVE_CLK
+
+// SSI_SLAVE_MISO Pin <0=>Not Used <1=>GPIO_11 <2=>GPIO_28 <3=>GPIO_49 <4=>GPIO_57
+#ifndef SSI_SLAVE_MISO_LOC
+#define RTE_SSI_SLAVE_MISO_PORT_ID 2
+
+#if (RTE_SSI_SLAVE_MISO_PORT_ID == 0)
+#define RTE_SSI_SLAVE_MISO 0
+#elif (RTE_SSI_SLAVE_MISO_PORT_ID == 1)
+#define RTE_SSI_SLAVE_MISO 1
+#define RTE_SSI_SLAVE_MISO_PORT HP
+#define RTE_SSI_SLAVE_MISO_PIN 11
+#define RTE_SSI_SLAVE_MISO_MODE EGPIO_PIN_MUX_MODE8
+#define RTE_SSI_SLAVE_MISO_PADSEL 6
+#elif (RTE_SSI_SLAVE_MISO_PORT_ID == 2)
+#define RTE_SSI_SLAVE_MISO 1
+#define RTE_SSI_SLAVE_MISO_PORT HP
+#define RTE_SSI_SLAVE_MISO_PIN 28
+#define RTE_SSI_SLAVE_MISO_MODE EGPIO_PIN_MUX_MODE8
+#define RTE_SSI_SLAVE_MISO_PADSEL 0 //no pad
+#elif (RTE_SSI_SLAVE_MISO_PORT_ID == 3)
+#define RTE_SSI_SLAVE_MISO 1
+#define RTE_SSI_SLAVE_MISO_PORT HP
+#define RTE_SSI_SLAVE_MISO_PIN 49
+#define RTE_SSI_SLAVE_MISO_MODE EGPIO_PIN_MUX_MODE8
+#define RTE_SSI_SLAVE_MISO_PADSEL 13
+#elif (RTE_SSI_SLAVE_MISO_PORT_ID == 4)
+#define RTE_SSI_SLAVE_MISO 1
+#define RTE_SSI_SLAVE_MISO_PORT HP
+#define RTE_SSI_SLAVE_MISO_PIN 57
+#define RTE_SSI_SLAVE_MISO_MODE EGPIO_PIN_MUX_MODE8
+#define RTE_SSI_SLAVE_MISO_PADSEL 21
+#else
+#error "Invalid SSI_SLAVE_MISO Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_SSI_SLAVE_MISO 1
+#define RTE_SSI_SLAVE_MISO_PORT HP
+#define RTE_SSI_SLAVE_MISO_PIN SSI_SLAVE_MISO__PIN
+#define RTE_SSI_SLAVE_MISO_MODE EGPIO_PIN_MUX_MODE8
+#if (SSI_SLAVE_MISO_LOC == 5)
+#define RTE_SSI_SLAVE_MISO_PADSEL 6
+#endif
+#if (SSI_SLAVE_MISO_LOC == 6)
+#define RTE_SSI_SLAVE_MISO_PADSEL 0 //no pad
+#endif
+#if (SSI_SLAVE_MISO_LOC == 7)
+#define RTE_SSI_SLAVE_MISO_PADSEL 13
+#endif
+#if (SSI_SLAVE_MISO_LOC == 8)
+#define RTE_SSI_SLAVE_MISO_PADSEL 21
+#endif
+//Pintool data
+#endif
+
+// SSI_SLAVE_MOSI Pin <0=>Not Used <1=>GPIO_10 <2=>GPIO_27 <3=>GPIO_48 <4=>GPIO_56
+#ifndef SSI_SLAVE_MOSI_LOC
+#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
+#define RTE_SSI_SLAVE_MOSI_PORT_ID 2
+#else
+#define RTE_SSI_SLAVE_MOSI_PORT_ID 1
+#endif
+
+#if (RTE_SSI_SLAVE_MOSI_PORT_ID == 0)
+#define RTE_SSI_SLAVE_MOSI 0
+#elif (RTE_SSI_SLAVE_MOSI_PORT_ID == 1)
+#define RTE_SSI_SLAVE_MOSI 1
+#define RTE_SSI_SLAVE_MOSI_PORT HP
+#define RTE_SSI_SLAVE_MOSI_PIN 10
+#define RTE_SSI_SLAVE_MOSI_MODE EGPIO_PIN_MUX_MODE8
+#define RTE_SSI_SLAVE_MOSI_PADSEL 5
+#elif (RTE_SSI_SLAVE_MOSI_PORT_ID == 2)
+#define RTE_SSI_SLAVE_MOSI 1
+#define RTE_SSI_SLAVE_MOSI_PORT HP
+#define RTE_SSI_SLAVE_MOSI_PIN 27
+#define RTE_SSI_SLAVE_MOSI_MODE EGPIO_PIN_MUX_MODE8
+#define RTE_SSI_SLAVE_MOSI_PADSEL 0 //no pad
+#elif (RTE_SSI_SLAVE_MOSI_PORT_ID == 3)
+#define RTE_SSI_SLAVE_MOSI 1
+#define RTE_SSI_SLAVE_MOSI_PORT HP
+#define RTE_SSI_SLAVE_MOSI_PIN 48
+#define RTE_SSI_SLAVE_MOSI_MODE EGPIO_PIN_MUX_MODE8
+#define RTE_SSI_SLAVE_MOSI_PADSEL 12
+#elif (RTE_SSI_SLAVE_MOSI_PORT_ID == 4)
+#define RTE_SSI_SLAVE_MOSI 1
+#define RTE_SSI_SLAVE_MOSI_PORT HP
+#define RTE_SSI_SLAVE_MOSI_PIN 56
+#define RTE_SSI_SLAVE_MOSI_MODE EGPIO_PIN_MUX_MODE8
+#define RTE_SSI_SLAVE_MOSI_PADSEL 20
+#else
+#error "Invalid SSI_SLAVE_MOSI Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_SSI_SLAVE_MOSI 1
+#define RTE_SSI_SLAVE_MOSI_PORT HP
+#define RTE_SSI_SLAVE_MOSI_PIN SSI_SLAVE_MOSI__PIN
+#define RTE_SSI_SLAVE_MOSI_MODE EGPIO_PIN_MUX_MODE8
+#if (SSI_SLAVE_MOSI_LOC == 1)
+#define RTE_SSI_SLAVE_MOSI_PADSEL 5
+#endif
+#if (SSI_SLAVE_MOSI_LOC == 2)
+#define RTE_SSI_SLAVE_MOSI_PADSEL 0 //no pad
+#endif
+#if (SSI_SLAVE_MOSI_LOC == 3)
+#define RTE_SSI_SLAVE_MOSI_PADSEL 12
+#endif
+#if (SSI_SLAVE_MOSI_LOC == 4)
+#define RTE_SSI_SLAVE_MOSI_PADSEL 20
+#endif
+//Pintool data
+#endif
+
+// SSI_SLAVE_SCK Pin <0=>Not Used <1=>GPIO_8 <2=>GPIO_26 <3=>GPIO_47 <4=>GPIO_52
+#ifndef SSI_SLAVE_SCK_LOC
+#define RTE_SSI_SLAVE_SCK_PORT_ID 2
+
+#if (RTE_SSI_SLAVE_SCK_PORT_ID == 0)
+#define RTE_SSI_SLAVE_SCK 0
+#elif (RTE_SSI_SLAVE_SCK_PORT_ID == 1)
+#define RTE_SSI_SLAVE_SCK 1
+#define RTE_SSI_SLAVE_SCK_PORT HP
+#define RTE_SSI_SLAVE_SCK_PIN 8
+#define RTE_SSI_SLAVE_SCK_MODE EGPIO_PIN_MUX_MODE8
+#define RTE_SSI_SLAVE_SCK_PADSEL 3
+#elif (RTE_SSI_SLAVE_SCK_PORT_ID == 2)
+#define RTE_SSI_SLAVE_SCK 1
+#define RTE_SSI_SLAVE_SCK_PORT HP
+#define RTE_SSI_SLAVE_SCK_PIN 26
+#define RTE_SSI_SLAVE_SCK_MODE EGPIO_PIN_MUX_MODE8
+#define RTE_SSI_SLAVE_SCK_PADSEL 0 //no pad
+#elif (RTE_SSI_SLAVE_SCK_PORT_ID == 3)
+#define RTE_SSI_SLAVE_SCK 1
+#define RTE_SSI_SLAVE_SCK_PORT HP
+#define RTE_SSI_SLAVE_SCK_PIN 47
+#define RTE_SSI_SLAVE_SCK_MODE EGPIO_PIN_MUX_MODE8
+#define RTE_SSI_SLAVE_SCK_PADSEL 11
+#elif (RTE_SSI_SLAVE_SCK_PORT_ID == 4)
+#define RTE_SSI_SLAVE_SCK 1
+#define RTE_SSI_SLAVE_SCK_PORT HP
+#define RTE_SSI_SLAVE_SCK_PIN 52
+#define RTE_SSI_SLAVE_SCK_MODE EGPIO_PIN_MUX_MODE8
+#define RTE_SSI_SLAVE_SCK_PADSEL 16
+#else
+#error "Invalid SSI_SLAVE_SCK Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_SSI_SLAVE_SCK 1
+#define RTE_SSI_SLAVE_SCK_PORT HP
+#define RTE_SSI_SLAVE_SCK_PIN SSI_SLAVE_SCK__PIN
+#define RTE_SSI_SLAVE_SCK_MODE EGPIO_PIN_MUX_MODE8
+#if (SSI_SLAVE_SCK_LOC == 9)
+#define RTE_SSI_SLAVE_SCK_PADSEL 3
+#endif
+#if (SSI_SLAVE_SCK_LOC == 10)
+#define RTE_SSI_SLAVE_SCK_PADSEL 0 //no pad
+#endif
+#if (SSI_SLAVE_SCK_LOC == 11)
+#define RTE_SSI_SLAVE_SCK_PADSEL 11
+#endif
+#if (SSI_SLAVE_SCK_LOC == 12)
+#define RTE_SSI_SLAVE_SCK_PADSEL 16
+#endif
+//Pintool data
+#endif
+
+// SSI_SLAVE_CS Pin <0=>Not Used <1=>GPIO_9 <2=>GPIO_25 <3=>GPIO_46 <4=>GPIO_53
+#ifndef SSI_SLAVE_CS0_LOC
+#define RTE_SSI_SLAVE_CS_PORT_ID 1
+
+#if (RTE_SSI_SLAVE_CS_PORT_ID == 0)
+#define RTE_SSI_SLAVE_CS 0
+#elif (RTE_SSI_SLAVE_CS_PORT_ID == 1)
+#define RTE_SSI_SLAVE_CS 1
+#define RTE_SSI_SLAVE_CS_PORT HP
+#define RTE_SSI_SLAVE_CS_PIN 9
+#define RTE_SSI_SLAVE_CS_MODE EGPIO_PIN_MUX_MODE8
+#define RTE_SSI_SLAVE_CS_PADSEL 4
+#elif (RTE_SSI_SLAVE_CS_PORT_ID == 2)
+#define RTE_SSI_SLAVE_CS 1
+#define RTE_SSI_SLAVE_CS_PORT HP
+#define RTE_SSI_SLAVE_CS_PIN 25
+#define RTE_SSI_SLAVE_CS_MODE EGPIO_PIN_MUX_MODE8
+#define RTE_SSI_SLAVE_CS_PADSEL 0 //no pad
+#elif (RTE_SSI_SLAVE_CS_PORT_ID == 3)
+#define RTE_SSI_SLAVE_CS 1
+#define RTE_SSI_SLAVE_CS_PORT HP
+#define RTE_SSI_SLAVE_CS_PIN 46
+#define RTE_SSI_SLAVE_CS_MODE EGPIO_PIN_MUX_MODE8
+#define RTE_SSI_SLAVE_CS_PADSEL 10
+#elif (RTE_SSI_SLAVE_CS_PORT_ID == 4)
+#define RTE_SSI_SLAVE_CS 1
+#define RTE_SSI_SLAVE_CS_PORT HP
+#define RTE_SSI_SLAVE_CS_PIN 53
+#define RTE_SSI_SLAVE_CS_MODE EGPIO_PIN_MUX_MODE8
+#define RTE_SSI_SLAVE_CS_PADSEL 17
+#else
+#error "Invalid SSI_SLAVE_CS Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_SSI_SLAVE_CS 1
+#define RTE_SSI_SLAVE_CS_PORT HP
+#define RTE_SSI_SLAVE_CS_PIN SSI_SLAVE_CS0__PIN
+#define RTE_SSI_SLAVE_CS_MODE EGPIO_PIN_MUX_MODE8
+#if (SSI_SLAVE_CS0_LOC == 13)
+#define RTE_SSI_SLAVE_CS_PADSEL 4
+#endif
+#if (SSI_SLAVE_CS0_LOC == 14)
+#define RTE_SSI_SLAVE_CS_PADSEL 0 //no pad
+#endif
+#if (SSI_SLAVE_CS0_LOC == 15)
+#define RTE_SSI_SLAVE_CS_PADSEL 10
+#endif
+#if (SSI_SLAVE_CS0_LOC == 16)
+#define RTE_SSI_SLAVE_CS_PADSEL 17
+#endif
+//Pintool data
+#endif
+
+// DMA Rx
+// Channel <22=>22
+// Selects DMA Channel (only Channel 22 can be used)
+//
+#define RTE_SSI_SLAVE_UDMA_RX_CH 22
+#define RTE_SSI_SLAVE_DMA_RX_LEN_PER_DES 1024
+
+// DMA Tx
+// Channel <23=>23
+// Selects DMA Channel (only Channel 23 can be used)
+//
+#define RTE_SSI_SLAVE_UDMA_TX_CH 23
+#define RTE_SSI_SLAVE_DMA_TX_LEN_PER_DES 1024
+
+//
+
+// ULP SPI Peripheral (Serial Peripheral Interface 3) [Driver_SSI_ULP_MASTER]
+// Configuration settings for Driver_SSI_ULP_MASTER in component ::CMSIS Driver:SPI
+#define RTE_SSI_ULP_MASTER 1
+
+// Enable multiple CSN lines
+#define ULP_SSI_CS0 1
+#define ULP_SSI_CS1 0
+#define ULP_SSI_CS2 0
+
+// SSI_ULP_MASTER_MISO Pin <0=>Not Used <1=>ULP_GPIO_2 <2=>ULP_GPIO_9
+#if !defined(ULP_SPI_MISO_LOC) && !defined(ULP_SSI_MISO_LOC)
+#define RTE_SSI_ULP_MASTER_MISO_PORT_ID 0
+#if (RTE_SSI_ULP_MASTER_MISO_PORT_ID == 0)
+#define RTE_SSI_ULP_MASTER_MISO 1
+#define RTE_SSI_ULP_MASTER_MISO_PORT RTE_ULP_PORT
+#define RTE_SSI_ULP_MASTER_MISO_PIN (2 + GPIO_MAX_PIN)
+#define RTE_SSI_ULP_MASTER_MISO_MODE 1
+#define RTE_SSI_ULP_MASTER_MISO_PADSEL 0
+#elif (RTE_SSI_ULP_MASTER_MISO_PORT_ID == 1)
+#define RTE_SSI_ULP_MASTER_MISO 1
+#define RTE_SSI_ULP_MASTER_MISO_PORT RTE_ULP_PORT
+#define RTE_SSI_ULP_MASTER_MISO_PIN (6 + GPIO_MAX_PIN)
+#define RTE_SSI_ULP_MASTER_MISO_MODE 8
+#define RTE_SSI_ULP_MASTER_MISO_PADSEL 0
+#elif (RTE_SSI_ULP_MASTER_MISO_PORT_ID == 2)
+#define RTE_SSI_ULP_MASTER_MISO 1
+#define RTE_SSI_ULP_MASTER_MISO_PORT RTE_ULP_PORT
+#define RTE_SSI_ULP_MASTER_MISO_PIN (9 + GPIO_MAX_PIN)
+#define RTE_SSI_ULP_MASTER_MISO_MODE 1
+#define RTE_SSI_ULP_MASTER_MISO_PADSEL 0
+#elif (RTE_SSI_ULP_MASTER_MISO_PORT_ID == 3)
+#define RTE_SSI_ULP_MASTER_MISO 1
+#define RTE_SSI_ULP_MASTER_MISO_PORT RTE_ULP_PORT
+#define RTE_SSI_ULP_MASTER_MISO_PIN 8
+#define RTE_SSI_ULP_MASTER_MISO_MODE 1
+#define RTE_SSI_ULP_MASTER_MISO_PADSEL 3
+#elif (RTE_SSI_ULP_MASTER_MISO_PORT_ID == 4)
+#define RTE_SSI_ULP_MASTER_MISO 1
+#define RTE_SSI_ULP_MASTER_MISO_PORT RTE_ULP_PORT
+#define RTE_SSI_ULP_MASTER_MISO_PIN 47
+#define RTE_SSI_ULP_MASTER_MISO_MODE 1
+#define RTE_SSI_ULP_MASTER_MISO_PADSEL 11
+#else
+#error "Invalid SSI_ULP_MISO Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_SSI_ULP_MASTER_MISO 1
+#define RTE_SSI_ULP_MASTER_MISO_PORT RTE_ULP_PORT
+#if (ULP_SSI_MISO_LOC == 3)
+#define RTE_SSI_ULP_MASTER_MISO_PIN (ULP_SSI_MISO__PIN + GPIO_MAX_PIN)
+#define RTE_SSI_ULP_MASTER_MISO_MODE 8
+#define RTE_SSI_ULP_MASTER_MISO_PADSEL 0
+#endif
+#if (ULP_SSI_MISO_LOC == 4)
+#define RTE_SSI_ULP_MASTER_MISO_PIN (ULP_SSI_MISO__PIN + GPIO_MAX_PIN)
+#define RTE_SSI_ULP_MASTER_MISO_MODE 1
+#define RTE_SSI_ULP_MASTER_MISO_PADSEL 0
+#endif
+#if (ULP_SSI_MISO_LOC == 12)
+#define RTE_SSI_ULP_MASTER_MISO_PIN (ULP_SSI_MISO__PIN + GPIO_MAX_PIN)
+#define RTE_SSI_ULP_MASTER_MISO_MODE 1
+#define RTE_SSI_ULP_MASTER_MISO_PADSEL 0
+#endif
+#if (ULP_SSI_MISO_LOC == 15)
+#define RTE_SSI_ULP_MASTER_MISO_PIN ULP_SSI_MISO__PIN
+#define RTE_SSI_ULP_MASTER_MISO_MODE 1
+#define RTE_SSI_ULP_MASTER_MISO_PADSEL 3
+#endif
+#if (ULP_SSI_MISO_LOC == 16)
+#define RTE_SSI_ULP_MASTER_MISO_PIN ULP_SSI_MISO__PIN
+#define RTE_SSI_ULP_MASTER_MISO_MODE 1
+#define RTE_SSI_ULP_MASTER_MISO_PADSEL 11
+#endif
+//Pintool data
+#endif
+
+// SSI_ULP_MASTER_MOSI Pin <0=>Not Used <1=>ULP_GPIO_1 <2=>ULP_GPIO_11
+#if !defined(ULP_SPI_MOSI_LOC) && !defined(ULP_SSI_MOSI_LOC)
+#define RTE_SSI_ULP_MASTER_MOSI_PORT_ID 0
+#if (RTE_SSI_ULP_MASTER_MOSI_PORT_ID == 0)
+#define RTE_SSI_ULP_MASTER_MOSI 1
+#define RTE_SSI_ULP_MASTER_MOSI_PORT RTE_ULP_PORT
+#define RTE_SSI_ULP_MASTER_MOSI_PIN (1 + GPIO_MAX_PIN)
+#define RTE_SSI_ULP_MASTER_MOSI_MODE 1
+#define RTE_SSI_ULP_MASTER_MOSI_PADSEL 0
+#elif (RTE_SSI_ULP_MASTER_MOSI_PORT_ID == 1)
+#define RTE_SSI_ULP_MASTER_MOSI 1
+#define RTE_SSI_ULP_MASTER_MOSI_PORT RTE_ULP_PORT
+#define RTE_SSI_ULP_MASTER_MOSI_PIN (5 + GPIO_MAX_PIN)
+#define RTE_SSI_ULP_MASTER_MOSI_MODE 8
+#define RTE_SSI_ULP_MASTER_MOSI_PADSEL 0
+#elif (RTE_SSI_ULP_MASTER_MOSI_PORT_ID == 2)
+#define RTE_SSI_ULP_MASTER_MOSI 1
+#define RTE_SSI_ULP_MASTER_MOSI_PORT RTE_ULP_PORT
+#define RTE_SSI_ULP_MASTER_MOSI_PIN (11 + GPIO_MAX_PIN)
+#define RTE_SSI_ULP_MASTER_MOSI_MODE 1
+#define RTE_SSI_ULP_MASTER_MOSI_PADSEL 0
+#elif (RTE_SSI_ULP_MASTER_MOSI_PORT_ID == 3)
+#define RTE_SSI_ULP_MASTER_MOSI 1
+#define RTE_SSI_ULP_MASTER_MOSI_PORT RTE_ULP_PORT
+#define RTE_SSI_ULP_MASTER_MOSI_PIN 7
+#define RTE_SSI_ULP_MASTER_MOSI_MODE 1
+#define RTE_SSI_ULP_MASTER_MOSI_PADSEL 2
+#elif (RTE_SSI_ULP_MASTER_MOSI_PORT_ID == 4)
+#define RTE_SSI_ULP_MASTER_MOSI 1
+#define RTE_SSI_ULP_MASTER_MOSI_PORT RTE_ULP_PORT
+#define RTE_SSI_ULP_MASTER_MOSI_PIN 49
+#define RTE_SSI_ULP_MASTER_MOSI_MODE 1
+#define RTE_SSI_ULP_MASTER_MOSI_PADSEL 13
+#else
+#error "Invalid SSI_ULP_MOSI Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_SSI_ULP_MASTER_MOSI 1
+#define RTE_SSI_ULP_MASTER_MOSI_PORT RTE_ULP_PORT
+#if (ULP_SSI_MOSI_LOC == 0)
+#define RTE_SSI_ULP_MASTER_MOSI_PIN (ULP_SSI_MOSI__PIN + GPIO_MAX_PIN)
+#define RTE_SSI_ULP_MASTER_MOSI_MODE 1
+#define RTE_SSI_ULP_MASTER_MOSI_PADSEL 0
+#endif
+#if (ULP_SSI_MOSI_LOC == 1)
+#define RTE_SSI_ULP_MASTER_MOSI_PIN (ULP_SSI_MOSI__PIN + GPIO_MAX_PIN)
+#define RTE_SSI_ULP_MASTER_MOSI_MODE 8
+#define RTE_SSI_ULP_MASTER_MOSI_PADSEL 0
+#endif
+#if (ULP_SSI_MOSI_LOC == 2)
+#define RTE_SSI_ULP_MASTER_MOSI_PIN (ULP_SSI_MOSI__PIN + GPIO_MAX_PIN)
+#define RTE_SSI_ULP_MASTER_MOSI_MODE 1
+#define RTE_SSI_ULP_MASTER_MOSI_PADSEL 0
+#endif
+#if (ULP_SSI_MOSI_LOC == 13)
+#define RTE_SSI_ULP_MASTER_MOSI_PIN ULP_SSI_MOSI__PIN
+#define RTE_SSI_ULP_MASTER_MOSI_MODE 1
+#define RTE_SSI_ULP_MASTER_MOSI_PADSEL 2
+#endif
+#if (ULP_SSI_MOSI_LOC == 14)
+#define RTE_SSI_ULP_MASTER_MOSI_PIN ULP_SSI_MOSI__PIN
+#define RTE_SSI_ULP_MASTER_MOSI_MODE 1
+#define RTE_SSI_ULP_MASTER_MOSI_PADSEL 13
+#endif
+//Pintool data
+#endif
+
+// SSI_ULP_MASTER_SCK Pin <0=>Not Used <1=>ULP_GPIO_0 <2=>ULP_GPIO_8
+#if !defined(ULP_SPI_SCK_LOC) && !defined(ULP_SSI_SCK_LOC)
+#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
+#define RTE_SSI_ULP_MASTER_SCK_PORT_ID 3
+#else
+#define RTE_SSI_ULP_MASTER_SCK_PORT_ID 3
+#endif
+#if (RTE_SSI_ULP_MASTER_SCK_PORT_ID == 0)
+#define RTE_SSI_ULP_MASTER_SCK 0
+#elif (RTE_SSI_ULP_MASTER_SCK_PORT_ID == 1)
+#define RTE_SSI_ULP_MASTER_SCK 1
+#define RTE_SSI_ULP_MASTER_SCK_PORT RTE_ULP_PORT
+#define RTE_SSI_ULP_MASTER_SCK_PIN (0 + GPIO_MAX_PIN)
+#define RTE_SSI_ULP_MASTER_SCK_MODE 1
+#define RTE_SSI_ULP_MASTER_SCK_PADSEL 0
+#elif (RTE_SSI_ULP_MASTER_SCK_PORT_ID == 2)
+#define RTE_SSI_ULP_MASTER_SCK 1
+#define RTE_SSI_ULP_MASTER_SCK_PORT RTE_ULP_PORT
+#define RTE_SSI_ULP_MASTER_SCK_PIN (4 + GPIO_MAX_PIN)
+#define RTE_SSI_ULP_MASTER_SCK_MODE 8
+#define RTE_SSI_ULP_MASTER_SCK_PADSEL 0
+#elif (RTE_SSI_ULP_MASTER_SCK_PORT_ID == 3)
+#define RTE_SSI_ULP_MASTER_SCK 1
+#define RTE_SSI_ULP_MASTER_SCK_PORT RTE_ULP_PORT
+#define RTE_SSI_ULP_MASTER_SCK_PIN (8 + GPIO_MAX_PIN)
+#define RTE_SSI_ULP_MASTER_SCK_MODE 1
+#define RTE_SSI_ULP_MASTER_SCK_PADSEL 0
+#elif (RTE_SSI_ULP_MASTER_SCK_PORT_ID == 4)
+#define RTE_SSI_ULP_MASTER_SCK 1
+#define RTE_SSI_ULP_MASTER_SCK_PORT RTE_ULP_PORT
+#define RTE_SSI_ULP_MASTER_SCK_PIN 6
+#define RTE_SSI_ULP_MASTER_SCK_MODE 1
+#define RTE_SSI_ULP_MASTER_SCK_PADSEL 1
+#elif (RTE_SSI_ULP_MASTER_SCK_PORT_ID == 5)
+#define RTE_SSI_ULP_MASTER_SCK 1
+#define RTE_SSI_ULP_MASTER_SCK_PORT RTE_ULP_PORT
+#define RTE_SSI_ULP_MASTER_SCK_PIN 46
+#define RTE_SSI_ULP_MASTER_SCK_MODE 1
+#define RTE_SSI_ULP_MASTER_SCK_PADSEL 10
+#else
+#error "Invalid SSI_ULP_SCK Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_SSI_ULP_MASTER_SCK 1
+#define RTE_SSI_ULP_MASTER_SCK_PORT RTE_ULP_PORT
+#if (ULP_SSI_SCK_LOC == 5)
+#define RTE_SSI_ULP_MASTER_SCK_PIN (ULP_SSI_SCK__PIN + GPIO_MAX_PIN)
+#define RTE_SSI_ULP_MASTER_SCK_MODE 1
+#define RTE_SSI_ULP_MASTER_SCK_PADSEL 0
+#endif
+#if (ULP_SSI_SCK_LOC == 6)
+#define RTE_SSI_ULP_MASTER_SCK_PIN (ULP_SSI_SCK__PIN + GPIO_MAX_PIN)
+#define RTE_SSI_ULP_MASTER_SCK_MODE 8
+#define RTE_SSI_ULP_MASTER_SCK_PADSEL 0
+#endif
+#if (ULP_SSI_SCK_LOC == 7)
+#define RTE_SSI_ULP_MASTER_SCK_PIN (ULP_SSI_SCK__PIN + GPIO_MAX_PIN)
+#define RTE_SSI_ULP_MASTER_SCK_MODE 1
+#define RTE_SSI_ULP_MASTER_SCK_PADSEL 0
+#endif
+#if (ULP_SSI_SCK_LOC == 17)
+#define RTE_SSI_ULP_MASTER_SCK_PIN ULP_SSI_SCK__PIN
+#define RTE_SSI_ULP_MASTER_SCK_MODE 1
+#define RTE_SSI_ULP_MASTER_SCK_PADSEL 1
+#endif
+#if (ULP_SSI_SCK_LOC == 18)
+#define RTE_SSI_ULP_MASTER_SCK_PIN ULP_SSI_SCK__PIN
+#define RTE_SSI_ULP_MASTER_SCK_MODE 1
+#define RTE_SSI_ULP_MASTER_SCK_PADSEL 10
+#endif
+//Pintool data
+#endif
+
+// CS0
+#if !defined(ULP_SPI_CS0_LOC) && !defined(ULP_SSI_CS0_LOC)
+#define RTE_SSI_ULP_MASTER_CS0_PORT_ID 2
+#if (RTE_SSI_ULP_MASTER_CS0_PORT_ID == 0)
+#define RTE_SSI_ULP_MASTER_CS0 ULP_SSI_CS0
+#define RTE_SSI_ULP_MASTER_CS0_PORT RTE_ULP_PORT
+#define RTE_SSI_ULP_MASTER_CS0_PIN (3 + GPIO_MAX_PIN)
+#define RTE_SSI_ULP_MASTER_CS0_MODE 1
+#define RTE_SSI_ULP_MASTER_CS0_PADSEL 0
+#elif (RTE_SSI_ULP_MASTER_CS0_PORT_ID == 1)
+#define RTE_SSI_ULP_MASTER_CS0 ULP_SSI_CS0
+#define RTE_SSI_ULP_MASTER_CS0_PORT RTE_ULP_PORT
+#define RTE_SSI_ULP_MASTER_CS0_PIN (7 + GPIO_MAX_PIN)
+#define RTE_SSI_ULP_MASTER_CS0_MODE 8
+#define RTE_SSI_ULP_MASTER_CS0_PADSEL 0
+#elif (RTE_SSI_ULP_MASTER_CS0_PORT_ID == 2)
+#define RTE_SSI_ULP_MASTER_CS0 ULP_SSI_CS0
+#define RTE_SSI_ULP_MASTER_CS0_PORT RTE_ULP_PORT
+#define RTE_SSI_ULP_MASTER_CS0_PIN (10 + GPIO_MAX_PIN)
+#define RTE_SSI_ULP_MASTER_CS0_MODE 1
+#define RTE_SSI_ULP_MASTER_CS0_PADSEL 0
+#elif (RTE_SSI_ULP_MASTER_CS0_PORT_ID == 3)
+#define RTE_SSI_ULP_MASTER_CS0 ULP_SSI_CS0
+#define RTE_SSI_ULP_MASTER_CS0_PORT RTE_ULP_PORT
+#define RTE_SSI_ULP_MASTER_CS0_PIN 48
+#define RTE_SSI_ULP_MASTER_CS0_MODE 1
+#define RTE_SSI_ULP_MASTER_CS0_PADSEL 12
+#else
+#error "Change RTE_SSI_ULP_MASTER_CS_PORT_ID other than '1' or'3' as per PACKAGE_TYPE"
+#endif
+#else
+//Pintool data
+#define RTE_SSI_ULP_MASTER_CS0 1
+#define RTE_SSI_ULP_MASTER_CS0_PORT RTE_ULP_PORT
+#if (ULP_SSI_CS0_LOC == 8)
+#define RTE_SSI_ULP_MASTER_CS0_PIN (ULP_SSI_CS0__PIN + GPIO_MAX_PIN)
+#define RTE_SSI_ULP_MASTER_CS0_MODE 8
+#define RTE_SSI_ULP_MASTER_CS0_PADSEL 0
+#endif
+#if (ULP_SSI_CS0_LOC == 9)
+#define RTE_SSI_ULP_MASTER_CS0_PIN (ULP_SSI_CS0__PIN + GPIO_MAX_PIN)
+#define RTE_SSI_ULP_MASTER_CS0_MODE 1
+#define RTE_SSI_ULP_MASTER_CS0_PADSEL 0
+#endif
+#if (ULP_SSI_CS0_LOC == 19)
+#define RTE_SSI_ULP_MASTER_CS0_PIN ULP_SSI_CS0__PIN
+#define RTE_SSI_ULP_MASTER_CS0_MODE 1
+#define RTE_SSI_ULP_MASTER_CS0_PADSEL 12
+#endif
+//Pintool data
+#endif
+
+// CS1
+#if !defined(ULP_SPI_CS1_LOC) && !defined(ULP_SSI_CS1_LOC)
+#define RTE_SSI_ULP_MASTER_CS1_PORT_ID 1
+#if (RTE_SSI_ULP_MASTER_CS1_PORT_ID == 0)
+#define RTE_SSI_ULP_MASTER_CS1 ULP_SSI_CS1
+#define RTE_SSI_ULP_MASTER_CS1_PORT RTE_ULP_PORT
+#define RTE_SSI_ULP_MASTER_CS1_PIN (4 + GPIO_MAX_PIN)
+#define RTE_SSI_ULP_MASTER_CS1_PADSEL 0
+#elif (RTE_SSI_ULP_MASTER_CS1_PORT_ID == 1)
+#define RTE_SSI_ULP_MASTER_CS1 ULP_SSI_CS1
+#define RTE_SSI_ULP_MASTER_CS1_PORT RTE_ULP_PORT
+#define RTE_SSI_ULP_MASTER_CS1_PIN 10
+#define RTE_SSI_ULP_MASTER_CS1_PADSEL 5
+#else
+#error "Invalid SSI_ULP_CS1 Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_SSI_ULP_MASTER_CS1_PORT RTE_ULP_PORT
+#define RTE_SSI_ULP_MASTER_CS1 1
+#if (ULP_SSI_CS1_LOC == 10)
+#define RTE_SSI_ULP_MASTER_CS1_PIN (ULP_SSI_CS1__PIN + GPIO_MAX_PIN)
+#define RTE_SSI_ULP_MASTER_CS1_PADSEL 0
+#endif
+#if (ULP_SSI_CS1_LOC == 20)
+#define RTE_SSI_ULP_MASTER_CS1_PIN ULP_SSI_CS1__PIN
+#define RTE_SSI_ULP_MASTER_CS1_PADSEL 5
+#endif
+//Pintool data
+#endif
+#define RTE_SSI_ULP_MASTER_CS1_MODE 1
+
+// CS2
+#if !defined(ULP_SPI_CS2_LOC) && !defined(ULP_SSI_CS2_LOC)
+#define RTE_SSI_ULP_MASTER_CS2_PORT_ID 0
+#if (RTE_SSI_ULP_MASTER_CS2_PORT_ID == 0)
+#define RTE_SSI_ULP_MASTER_CS2 ULP_SSI_CS2
+#define RTE_SSI_ULP_MASTER_CS2_PORT RTE_ULP_PORT
+#define RTE_SSI_ULP_MASTER_CS2_PIN (6 + GPIO_MAX_PIN)
+#define RTE_SSI_ULP_MASTER_CS2_PADSEL 0
+#elif (RTE_SSI_ULP_MASTER_CS1_PORT_ID == 1)
+#define RTE_SSI_ULP_MASTER_CS2 ULP_SSI_CS2
+#define RTE_SSI_ULP_MASTER_CS2_PORT RTE_ULP_PORT
+#define RTE_SSI_ULP_MASTER_CS2_PIN 12
+#define RTE_SSI_ULP_MASTER_CS2_PADSEL 7
+#else
+#error "Invalid SSI_ULP_CS2 Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_SSI_ULP_MASTER_CS2_PORT RTE_ULP_PORT
+#define RTE_SSI_ULP_MASTER_CS2 1
+#if (ULP_SSI_CS2_LOC == 11)
+#define RTE_SSI_ULP_MASTER_CS2_PIN (ULP_SSI_CS2__PIN + GPIO_MAX_PIN)
+#define RTE_SSI_ULP_MASTER_CS2_PADSEL 0
+#endif
+#if (ULP_SSI_CS2_LOC == 21)
+#define RTE_SSI_ULP_MASTER_CS2_PIN ULP_SSI_CS2__PIN
+#define RTE_SSI_ULP_MASTER_CS2_PADSEL 7
+#endif
+//Pintool data
+#endif
+#define RTE_SSI_ULP_MASTER_CS2_MODE 1
+
+// DMA Rx
+// Channel <2=>2
+// Selects DMA Channel (only Channel 2 can be used)
+//
+#define RTE_SSI_ULP_MASTER_UDMA_RX_CH 2
+#define RTE_SSI_ULP_MASTER_DMA_RX_LEN_PER_DES 96
+
+// DMA Tx
+// Channel <3=>3
+// Selects DMA Channel (only Channel 3 can be used)
+//
+#define RTE_SSI_ULP_MASTER_UDMA_TX_CH 3
+#define RTE_SSI_ULP_MASTER_DMA_TX_LEN_PER_DES 96
+
+//
+/*===================================================================
+ UDMA Defines
+====================================================================*/
+// UDMA [Driver_UDMA]
+#define DESC_MAX_LEN 0x400
+#define RTE_UDMA0 1
+#define UDMA0_IRQHandler IRQ033_Handler
+#define CHNL_MASK_REQ0 0
+#define CHNL_PRIORITY0 0
+#define DMA_PERI_ACK0 0
+#define BURST_REQ0_EN 1
+#define UDMA0_CHNL_PRIO_LVL 1
+#define UDMA0_SRAM_BASE 0x1FC00
+
+#define RTE_UDMA1 1
+#define UDMA1_IRQHandler IRQ010_Handler
+#define CHNL_MASK_REQ1 0
+#define CHNL_PRIORITY1 0
+#define BURST_REQ1_EN 1
+#define CHNL_HIGH_PRIO_EN1 1
+#define UDMA1_CHNL_PRIO_LVL 1
+#define ULP_SRAM_START_ADDR 0x24060000
+#define ULP_SRAM_END_ADDR 0x24063E00
+// RTE_UDMA1_BASE_MEM <0=>PS2 <1=>PS4
+#define RTE_UDMA1_BASE_MEM 0
+#if (RTE_UDMA1_BASE_MEM == 0)
+#define UDMA1_SRAM_BASE 0x24061C00
+#elif (RTE_UDMA1_BASE_MEM == 1)
+#define UDMA1_SRAM_BASE 0x1CC00
+#else
+#error "Invalid UDMA1 Control Base Address!"
+#endif
+//
+
+// I2S0 [Driver_I2S0]
+// Configuration settings for Driver_I2S0 in component ::CMSIS Driver:I2S
+
+#define RTE_I2S0 1
+#define I2S0_IRQHandler IRQ064_Handler
+/*I2S0 PINS*/
+
+// I2S0_SCLK <0=>P0_8 <1=>P0_25 <2=>P0_46 <3=>P0_52
+// SCLK of I2S0
+#ifndef I2S0_SCLK_LOC
+#define RTE_I2S0_SCLK_PORT_ID 1
+
+#if (RTE_I2S0_SCLK_PORT_ID == 0)
+#define RTE_I2S0_SCLK_PORT HP
+#define RTE_I2S0_SCLK_PIN 8
+#define RTE_I2S0_SCLK_MUX 7
+#define RTE_I2S0_SCLK_PAD 3
+#elif (RTE_I2S0_SCLK_PORT_ID == 1)
+#define RTE_I2S0_SCLK_PORT HP
+#define RTE_I2S0_SCLK_PIN 25
+#define RTE_I2S0_SCLK_MUX 7
+#define RTE_I2S0_SCLK_PAD 0 //no pad
+#elif (RTE_I2S0_SCLK_PORT_ID == 2)
+#define RTE_I2S0_SCLK_PORT HP
+#define RTE_I2S0_SCLK_PIN 46
+#define RTE_I2S0_SCLK_MUX 7
+#define RTE_I2S0_SCLK_PAD 10
+#elif (RTE_I2S0_SCLK_PORT_ID == 3)
+#define RTE_I2S0_SCLK_PORT HP
+#define RTE_I2S0_SCLK_PIN 52
+#define RTE_I2S0_SCLK_MUX 7
+#define RTE_I2S0_SCLK_PAD 16
+#else
+#error "Invalid I2S0 RTE_I2S0_SCLK Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_I2S0_SCLK_PORT HP
+#define RTE_I2S0_SCLK_PIN I2S0_SCLK_PIN
+#define RTE_I2S0_SCLK_MUX 7
+#if (I2S0_SCLK_LOC == 0)
+#define RTE_I2S0_SCLK_PAD 3
+#endif
+#if (I2S0_SCLK_LOC == 1)
+#define RTE_I2S0_SCLK_PAD 0 //no pad
+#endif
+#if (I2S0_SCLK_LOC == 2)
+#define RTE_I2S0_SCLK_PAD 10
+#endif
+#if (I2S0_SCLK_LOC == 3)
+#define RTE_I2S0_SCLK_PAD 16
+#endif
+//Pintool data
+#endif
+
+// I2S0_WSCLK <0=>P0_9 <1=>P0_26 <2=>P0_47 <3=>P0_53
+// WSCLK for I2S0
+#ifndef I2S0_WSCLK_LOC
+#define RTE_I2S0_WSCLK_PORT_ID 1
+
+#if (RTE_I2S0_WSCLK_PORT_ID == 0)
+#define RTE_I2S0_WSCLK_PORT HP
+#define RTE_I2S0_WSCLK_PIN 9
+#define RTE_I2S0_WSCLK_MUX 7
+#define RTE_I2S0_WSCLK_PAD 4
+#elif (RTE_I2S0_WSCLK_PORT_ID == 1)
+#define RTE_I2S0_WSCLK_PORT HP
+#define RTE_I2S0_WSCLK_PIN 26
+#define RTE_I2S0_WSCLK_MUX 7
+#define RTE_I2S0_WSCLK_PAD 0 //no pad
+#elif (RTE_I2S0_WSCLK_PORT_ID == 2)
+#define RTE_I2S0_WSCLK_PORT HP
+#define RTE_I2S0_WSCLK_PIN 47
+#define RTE_I2S0_WSCLK_MUX 7
+#define RTE_I2S0_WSCLK_PAD 11
+#elif (RTE_I2S0_WSCLK_PORT_ID == 3)
+#define RTE_I2S0_WSCLK_PORT HP
+#define RTE_I2S0_WSCLK_PIN 53
+#define RTE_I2S0_WSCLK_MUX 7
+#define RTE_I2S0_WSCLK_PAD 17
+#else
+#error "Invalid I2S0 RTE_I2S0_WSCLK Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_I2S0_WSCLK_PORT HP
+#define RTE_I2S0_WSCLK_PIN I2S0_WSCLK_PIN
+#define RTE_I2S0_WSCLK_MUX 7
+#if (I2S0_WSCLK_LOC == 4)
+#define RTE_I2S0_WSCLK_PAD 4
+#endif
+#if (I2S0_WSCLK_LOC == 5)
+#define RTE_I2S0_WSCLK_PAD 0
+#endif
+#if (I2S0_WSCLK_LOC == 6)
+#define RTE_I2S0_WSCLK_PAD 11
+#endif
+#if (I2S0_WSCLK_LOC == 7)
+#define RTE_I2S0_WSCLK_PAD 17
+#endif
+//Pintool data
+#endif
+
+// I2S0_DOUT0 <0=>P0_11 <1=>P0_28 <2=>P0_49 <3=>P0_57
+// DOUT0 for I2S0
+#ifndef I2S0_DOUT0_LOC
+#define RTE_I2S0_DOUT0_PORT_ID 1
+
+#if (RTE_I2S0_DOUT0_PORT_ID == 0)
+#define RTE_I2S0_DOUT0_PORT HP
+#define RTE_I2S0_DOUT0_PIN 11
+#define RTE_I2S0_DOUT0_MUX 7
+#define RTE_I2S0_DOUT0_PAD 6
+#elif (RTE_I2S0_DOUT0_PORT_ID == 1)
+#define RTE_I2S0_DOUT0_PORT HP
+#define RTE_I2S0_DOUT0_PIN 28
+#define RTE_I2S0_DOUT0_MUX 7
+#define RTE_I2S0_DOUT0_PAD 0 // no pad
+#elif (RTE_I2S0_DOUT0_PORT_ID == 2)
+#define RTE_I2S0_DOUT0_PORT HP
+#define RTE_I2S0_DOUT0_PIN 49
+#define RTE_I2S0_DOUT0_MUX 7
+#define RTE_I2S0_DOUT0_PAD 13
+#elif (RTE_I2S0_DOUT0_PORT_ID == 3)
+#define RTE_I2S0_DOUT0_PORT HP
+#define RTE_I2S0_DOUT0_PIN 57
+#define RTE_I2S0_DOUT0_MUX 7
+#define RTE_I2S0_DOUT0_PAD 21
+#else
+#error "Invalid I2S0 RTE_I2S0_DOUT0 Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_I2S0_DOUT0_PORT HP
+#define RTE_I2S0_DOUT0_PIN I2S0_DOUT0_PIN
+#define RTE_I2S0_DOUT0_MUX 7
+#if (I2S0_DOUT0_LOC == 8)
+#define RTE_I2S0_DOUT0_PAD 6
+#endif
+#if (I2S0_DOUT0_LOC == 9)
+#define RTE_I2S0_DOUT0_PAD 0
+#endif
+#if (I2S0_DOUT0_LOC == 10)
+#define RTE_I2S0_DOUT0_PAD 13
+#endif
+#if (I2S0_DOUT0_LOC == 11)
+#define RTE_I2S0_DOUT0_PAD 21
+#endif
+//Pintool data
+#endif
+
+// I2S0_DIN0 <0=>P0_10 <1=>P0_27 <2=>P0_48 <3=>P0_56
+// DIN0 for I2S0
+#ifndef I2S0_DIN0_LOC
+#define RTE_I2S0_DIN0_PORT_ID 1
+
+#if (RTE_I2S0_DIN0_PORT_ID == 0)
+#define RTE_I2S0_DIN0_PORT HP
+#define RTE_I2S0_DIN0_PIN 10
+#define RTE_I2S0_DIN0_MUX 7
+#define RTE_I2S0_DIN0_PAD 5
+#elif (RTE_I2S0_DIN0_PORT_ID == 1)
+#define RTE_I2S0_DIN0_PORT HP
+#define RTE_I2S0_DIN0_PIN 27
+#define RTE_I2S0_DIN0_MUX 7
+#define RTE_I2S0_DIN0_PAD 0 // no pad
+#elif (RTE_I2S0_DIN0_PORT_ID == 2)
+#define RTE_I2S0_DIN0_PORT HP
+#define RTE_I2S0_DIN0_PIN 48
+#define RTE_I2S0_DIN0_MUX 7
+#define RTE_I2S0_DIN0_PAD 12
+#elif (RTE_I2S0_DIN0_PORT_ID == 3)
+#define RTE_I2S0_DIN0_PORT HP
+#define RTE_I2S0_DIN0_PIN 56
+#define RTE_I2S0_DIN0_MUX 7
+#define RTE_I2S0_DIN0_PAD 20
+#else
+#error "Invalid I2S0 RTE_I2S0_DIN0 Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_I2S0_DIN0_PORT HP
+#define RTE_I2S0_DIN0_PIN I2S0_DIN0_PIN
+#define RTE_I2S0_DIN0_MUX 7
+#if (I2S0_DIN0_LOC == 12)
+#define RTE_I2S0_DIN0_PAD 5
+#endif
+#if (I2S0_DIN0_LOC == 13)
+#define RTE_I2S0_DIN0_PAD 0
+#endif
+#if (I2S0_DIN0_LOC == 14)
+#define RTE_I2S0_DIN0_PAD 12
+#endif
+#if (I2S0_DIN0_LOC == 15)
+#define RTE_I2S0_DIN0_PAD 20
+#endif
+//Pintool data
+#endif
+
+// I2S0_DOUT1 <0=>P0_7 <1=>P0_30 <2=>P0_51 <3=>P0_55
+// DOUT1 for I2S0
+#ifndef I2S0_DOUT1_LOC
+#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
+#define RTE_I2S0_DOUT1_PORT_ID 1
+#else
+#define RTE_I2S0_DOUT1_PORT_ID 0
+#endif
+
+#if (RTE_I2S0_DOUT1_PORT_ID == 0)
+#define RTE_I2S0_DOUT1_PORT HP
+#define RTE_I2S0_DOUT1_PIN 7
+#define RTE_I2S0_DOUT1_MUX 7
+#define RTE_I2S0_DOUT1_PAD 2
+#elif (RTE_I2S0_DOUT1_PORT_ID == 1)
+#define RTE_I2S0_DOUT1_PORT HP
+#define RTE_I2S0_DOUT1_PIN 30
+#define RTE_I2S0_DOUT1_MUX 7
+#define RTE_I2S0_DOUT1_PAD 0 //no pad
+#elif (RTE_I2S0_DOUT1_PORT_ID == 2)
+#define RTE_I2S0_DOUT1_PORT HP
+#define RTE_I2S0_DOUT1_PIN 51
+#define RTE_I2S0_DOUT1_MUX 7
+#define RTE_I2S0_DOUT1_PAD 15
+#elif (RTE_I2S0_DOUT1_PORT_ID == 3)
+#define RTE_I2S0_DOUT1_PORT HP
+#define RTE_I2S0_DOUT1_PIN 55
+#define RTE_I2S0_DOUT1_MUX 7
+#define RTE_I2S0_DOUT1_PAD 19
+#else
+#error "Invalid I2S0 RTE_I2S0_DOUT1 Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_I2S0_DOUT1_PORT HP
+#define RTE_I2S0_DOUT1_PIN I2S0_DOUT1_PIN
+#define RTE_I2S0_DOUT1_MUX 7
+#if (I2S0_DOUT1_LOC == 16)
+#define RTE_I2S0_DOUT1_PAD 2
+#endif
+#if (I2S0_DOUT1_LOC == 17)
+#define RTE_I2S0_DOUT1_PAD 0
+#endif
+#if (I2S0_DOUT1_LOC == 18)
+#define RTE_I2S0_DOUT1_PAD 15
+#endif
+#if (I2S0_DOUT1_LOC == 19)
+#define RTE_I2S0_DOUT1_PAD 19
+#endif
+//Pintool data
+#endif
+
+// I2S0_DIN1 <0=>P0_6 <1=>P0_29 <2=>P0_50 <3=>P0_54
+// DIN1 for I2S0
+#ifndef I2S0_DIN1_LOC
+#define RTE_I2S0_DIN1_PORT_ID 0
+
+#if (RTE_I2S0_DIN1_PORT_ID == 0)
+#define RTE_I2S0_DIN1_PORT HP
+#define RTE_I2S0_DIN1_PIN 6
+#define RTE_I2S0_DIN1_MUX 7
+#define RTE_I2S0_DIN1_PAD 1
+#elif (RTE_I2S0_DIN1_PORT_ID == 1)
+#define RTE_I2S0_DIN1_PORT HP
+#define RTE_I2S0_DIN1_PIN 29
+#define RTE_I2S0_DIN1_MUX 7
+#define RTE_I2S0_DIN1_PAD 0 //no pad
+#elif (RTE_I2S0_DIN1_PORT_ID == 2)
+#define RTE_I2S0_DIN1_PORT HP
+#define RTE_I2S0_DIN1_PIN 50
+#define RTE_I2S0_DIN1_MUX 7
+#define RTE_I2S0_DIN1_PAD 14
+#elif (RTE_I2S0_DIN1_PORT_ID == 3)
+#define RTE_I2S0_DIN1_PORT HP
+#define RTE_I2S0_DIN1_PIN 54
+#define RTE_I2S0_DIN1_MUX 7
+#define RTE_I2S0_DIN1_PAD 18
+#else
+#error "Invalid I2S0 RTE_I2S0_DIN1 Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_I2S0_DIN1_PORT HP
+#define RTE_I2S0_DIN1_PIN I2S0_DIN1_PIN
+#define RTE_I2S0_DIN1_MUX 7
+#if (I2S0_DIN1_LOC == 20)
+#define RTE_I2S0_DIN1_PAD 1
+#endif
+#if (I2S0_DIN1_LOC == 21)
+#define RTE_I2S0_DIN1_PAD 0
+#endif
+#if (I2S0_DIN1_LOC == 22)
+#define RTE_I2S0_DIN1_PAD 14
+#endif
+#if (I2S0_DIN1_LOC == 23)
+#define RTE_I2S0_DIN1_PAD 18
+#endif
+//Pintool data
+#endif
+// FIFO level can have value 0 to 7
+#define I2S0_TX_FIFO_LEVEL (0U)
+#define I2S0_RX_FIFO_LEVEL (2U)
+
+// I2S0_TX_RES <0=>12
+// <1=>16
+// <2=>20
+// <3=>24
+#define RTE_I2S0_TX_RES 1
+#if (RTE_I2S0_TX_RES == 0)
+#define I2S0_TX_RES RES_12_BIT
+#elif (RTE_I2S0_TX_RES == 1)
+#define I2S0_TX_RES RES_16_BIT
+#elif (RTE_I2S0_TX_RES == 2)
+#define I2S0_TX_RES RES_20_BIT
+#elif (RTE_I2S0_TX_RES == 3)
+#define I2S0_TX_RES RES_24_BIT
+#else
+#error "Invalid I2S0 TX channel resolution!"
+#endif
+
+// I2S0_RX_RES <0=>12
+// <1=>16
+// <2=>20
+// <3=>24
+#define RTE_I2S0_RX_RES 1
+#if (RTE_I2S0_RX_RES == 0)
+#define I2S0_RX_RES RES_12_BIT
+#elif (RTE_I2S0_RX_RES == 1)
+#define I2S0_RX_RES RES_16_BIT
+#elif (RTE_I2S0_RX_RES == 2)
+#define I2S0_RX_RES RES_20_BIT
+#elif (RTE_I2S0_RX_RES == 3)
+#define I2S0_RX_RES RES_24_BIT
+#else
+#error "Invalid I2S0 RX channel resolution!"
+#endif
+
+#define RTE_I2S0_CHNL_UDMA_TX_EN 1
+#define RTE_I2S0_CHNL_UDMA_TX_CH 15
+
+#define RTE_I2S0_CHNL_UDMA_RX_EN 1
+#define RTE_I2S0_CHNL_UDMA_RX_CH 14
+
+#define RTE_I2S0_DMA_TX_LEN_PER_DES 1024
+#define RTE_I2S0_DMA_RX_LEN_PER_DES 1024
+
+//
+
+// ULP I2S [Driver_I2S1]
+// Configuration settings for Driver_I2S1 in component ::Drivers:I2S
+#define RTE_I2S1 1
+#define I2S1_IRQHandler IRQ014_Handler
+
+// I2S1_SCLK Pin <0=>P0_3 <1=>P0_7 <2=>P0_8
+/*I2S1 PINS*/
+#ifndef ULP_I2S_SCLK_LOC
+#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
+#define RTE_I2S1_SCLK_PORT_ID 0
+#else
+#define RTE_I2S1_SCLK_PORT_ID 2
+#endif
+#if (RTE_I2S1_SCLK_PORT_ID == 0)
+#define RTE_I2S1_SCLK_PORT RTE_ULP_PORT
+#define RTE_I2S1_SCLK_PIN (3 + GPIO_MAX_PIN)
+#define RTE_I2S1_SCLK_MUX 2
+#define RTE_I2S1_SCLK_PAD 0
+#elif (RTE_I2S1_SCLK_PORT_ID == 1)
+#define RTE_I2S1_SCLK_PORT RTE_ULP_PORT
+#define RTE_I2S1_SCLK_PIN (7 + GPIO_MAX_PIN)
+#define RTE_I2S1_SCLK_MUX 2
+#define RTE_I2S1_SCLK_PAD 0
+#elif (RTE_I2S1_SCLK_PORT_ID == 2)
+#define RTE_I2S1_SCLK_PORT RTE_ULP_PORT
+#define RTE_I2S1_SCLK_PIN (8 + GPIO_MAX_PIN)
+#define RTE_I2S1_SCLK_MUX 2
+#define RTE_I2S1_SCLK_PAD 0
+#elif (RTE_I2S1_SCLK_PORT_ID == 3)
+#define RTE_I2S1_SCLK_PORT RTE_ULP_PORT
+#define RTE_I2S1_SCLK_PIN 15
+#define RTE_I2S1_SCLK_MUX 2
+#define RTE_I2S1_SCLK_PAD 8
+#elif (RTE_I2S1_SCLK_PORT_ID == 4)
+#define RTE_I2S1_SCLK_PORT RTE_ULP_PORT
+#define RTE_I2S1_SCLK_PIN 46
+#define RTE_I2S1_SCLK_MUX 2
+#define RTE_I2S1_SCLK_PAD 10
+#else
+#error "Invalid I2S1 RTE_I2S1_SCLK Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_I2S1_SCLK_PORT RTE_ULP_PORT
+#define RTE_I2S1_SCLK_MUX 2
+#if ((ULP_I2S_SCLK_LOC == 0) || (ULP_I2S_SCLK_LOC == 1))
+#define RTE_I2S1_SCLK_PIN (ULP_I2S_SCLK_PIN + GPIO_MAX_PIN)
+#define RTE_I2S1_SCLK_PAD 0
+#endif
+#if (ULP_I2S_SCLK_LOC == 10)
+#define RTE_I2S1_SCLK_PIN ULP_I2S_SCLK_PIN
+#define RTE_I2S1_SCLK_PAD 8
+#endif
+#if (ULP_I2S_SCLK_LOC == 11)
+#define RTE_I2S1_SCLK_PIN ULP_I2S_SCLK_PIN
+#define RTE_I2S1_SCLK_PAD 10
+#endif
+//Pintool data
+#endif
+
+// I2S1_WSCLK Pin <0=>P0_2 <1=>P0_4 <2=>P0_10
+#ifndef ULP_I2S_WSCLK_LOC
+#define RTE_I2S1_WSCLK_PORT_ID 0
+#if (RTE_I2S1_WSCLK_PORT_ID == 0)
+#define RTE_I2S1_WSCLK_PORT RTE_ULP_PORT
+#define RTE_I2S1_WSCLK_PIN (2 + GPIO_MAX_PIN)
+#define RTE_I2S1_WSCLK_MUX 2
+#define RTE_I2S1_WSCLK_PAD 0
+#elif (RTE_I2S1_WSCLK_PORT_ID == 1)
+#define RTE_I2S1_WSCLK_PORT RTE_ULP_PORT
+#define RTE_I2S1_WSCLK_PIN (10 + GPIO_MAX_PIN)
+#define RTE_I2S1_WSCLK_MUX 2
+#define RTE_I2S1_WSCLK_PAD 0
+#elif (RTE_I2S1_WSCLK_PORT_ID == 2)
+#define RTE_I2S1_WSCLK_PORT RTE_ULP_PORT
+#define RTE_I2S1_WSCLK_PIN 8
+#define RTE_I2S1_WSCLK_MUX 2
+#define RTE_I2S1_WSCLK_PAD 3
+#elif (RTE_I2S1_WSCLK_PORT_ID == 3)
+#define RTE_I2S1_WSCLK_PORT RTE_ULP_PORT
+#define RTE_I2S1_WSCLK_PIN 10
+#define RTE_I2S1_WSCLK_MUX 2
+#define RTE_I2S1_WSCLK_PAD 5
+#elif (RTE_I2S1_WSCLK_PORT_ID == 4)
+#define RTE_I2S1_WSCLK_PORT RTE_ULP_PORT
+#define RTE_I2S1_WSCLK_PIN 48
+#define RTE_I2S1_WSCLK_MUX 2
+#define RTE_I2S1_WSCLK_PAD 12
+#else
+#error "Invalid I2S1 RTE_I2S1_WSCLK Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_I2S1_WSCLK_PORT RTE_ULP_PORT
+#define RTE_I2S1_WSCLK_MUX 2
+#if ((ULP_I2S_WSCLK_LOC == 2) || (ULP_I2S_WSCLK_LOC == 3))
+#define RTE_I2S1_WSCLK_PIN (ULP_I2S_WSCLK_PIN + GPIO_MAX_PIN)
+#define RTE_I2S1_WSCLK_PAD 0
+#endif
+#if (ULP_I2S_WSCLK_LOC == 12)
+#define RTE_I2S1_WSCLK_PIN ULP_I2S_WSCLK_PIN
+#define RTE_I2S1_WSCLK_PAD 3
+#endif
+#if (ULP_I2S_WSCLK_LOC == 13)
+#define RTE_I2S1_WSCLK_PIN ULP_I2S_WSCLK_PIN
+#define RTE_I2S1_WSCLK_PAD 5
+#endif
+#if (ULP_I2S_WSCLK_LOC == 14)
+#define RTE_I2S1_WSCLK_PIN ULP_I2S_WSCLK_PIN
+#define RTE_I2S1_WSCLK_PAD 12
+#endif
+//Pintool data
+#endif
+
+// I2S1_DOUT0 Pin <0=>P0_1 <1=>P0_5 <2=>P0_11
+#ifndef ULP_I2S_DOUT0_LOC
+#define RTE_I2S1_DOUT0_PORT_ID 0
+#if (RTE_I2S1_DOUT0_PORT_ID == 0)
+#define RTE_I2S1_DOUT0_PORT RTE_ULP_PORT
+#define RTE_I2S1_DOUT0_PIN (1 + GPIO_MAX_PIN)
+#define RTE_I2S1_DOUT0_MUX 2
+#define RTE_I2S1_DOUT0_PAD 0
+#elif (RTE_I2S1_DOUT0_PORT_ID == 1)
+#define RTE_I2S1_DOUT0_PORT RTE_ULP_PORT
+#define RTE_I2S1_DOUT0_PIN (11 + GPIO_MAX_PIN)
+#define RTE_I2S1_DOUT0_MUX 2
+#define RTE_I2S1_DOUT0_PAD 0
+#elif (RTE_I2S1_DOUT0_PORT_ID == 2)
+#define RTE_I2S1_DOUT0_PORT RTE_ULP_PORT
+#define RTE_I2S1_DOUT0_PIN 7
+#define RTE_I2S1_DOUT0_MUX 2
+#define RTE_I2S1_DOUT0_PAD 2
+#elif (RTE_I2S1_DOUT0_PORT_ID == 3)
+#define RTE_I2S1_DOUT0_PORT RTE_ULP_PORT
+#define RTE_I2S1_DOUT0_PIN 11
+#define RTE_I2S1_DOUT0_MUX 2
+#define RTE_I2S1_DOUT0_PAD 6
+#elif (RTE_I2S1_DOUT0_PORT_ID == 4)
+#define RTE_I2S1_DOUT0_PORT RTE_ULP_PORT
+#define RTE_I2S1_DOUT0_PIN 49
+#define RTE_I2S1_DOUT0_MUX 2
+#define RTE_I2S1_DOUT0_PAD 13
+#else
+#error "Invalid I2S1 RTE_I2S1_DOUT0 Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_I2S1_DOUT0_PORT RTE_ULP_PORT
+#define RTE_I2S1_DOUT0_MUX 2
+#if ((ULP_I2S_DOUT0_LOC == 4) || (ULP_I2S_DOUT0_LOC == 5) || (ULP_I2S_DOUT0_LOC == 6))
+#define RTE_I2S1_DOUT0_PIN (ULP_I2S_DOUT0_PIN + GPIO_MAX_PIN)
+#define RTE_I2S1_DOUT0_PAD 0
+#endif
+#if (ULP_I2S_DOUT0_LOC == 15)
+#define RTE_I2S1_DOUT0_PIN ULP_I2S_DOUT0_PIN
+#define RTE_I2S1_DOUT0_PAD 2
+#endif
+#if (ULP_I2S_DOUT0_LOC == 16)
+#define RTE_I2S1_DOUT0_PIN ULP_I2S_DOUT0_PIN
+#define RTE_I2S1_DOUT0_PAD 6
+#endif
+#if (ULP_I2S_DOUT0_LOC == 17)
+#define RTE_I2S1_DOUT0_PIN ULP_I2S_DOUT0_PIN
+#define RTE_I2S1_DOUT0_PAD 13
+#endif
+//Pintool data
+#endif
+
+// I2S1_DIN0 Pin <0=>P0_0 <1=>P0_6 <2=>P0_9 <3=>P0_13
+#ifndef ULP_I2S_DIN0_LOC
+#define RTE_I2S1_DIN0_PORT_ID 1
+#if (RTE_I2S1_DIN0_PORT_ID == 0)
+#define RTE_I2S1_DIN0_PORT RTE_ULP_PORT
+#define RTE_I2S1_DIN0_PIN (0 + GPIO_MAX_PIN)
+#define RTE_I2S1_DIN0_MUX 2
+#define RTE_I2S1_DIN0_PAD 0
+#elif (RTE_I2S1_DIN0_PORT_ID == 1)
+#define RTE_I2S1_DIN0_PORT RTE_ULP_PORT
+#define RTE_I2S1_DIN0_PIN (6 + GPIO_MAX_PIN)
+#define RTE_I2S1_DIN0_MUX 2
+#define RTE_I2S1_DIN0_PAD 0
+#elif (RTE_I2S1_DIN0_PORT_ID == 2)
+#define RTE_I2S1_DIN0_PORT RTE_ULP_PORT
+#define RTE_I2S1_DIN0_PIN (9 + GPIO_MAX_PIN)
+#define RTE_I2S1_DIN0_MUX 2
+#define RTE_I2S1_DIN0_PAD 0
+#elif (RTE_I2S1_DIN0_PORT_ID == 3)
+#define RTE_I2S1_DIN0_PORT RTE_ULP_PORT
+#define RTE_I2S1_DIN0_PIN 6
+#define RTE_I2S1_DIN0_MUX 2
+#define RTE_I2S1_DIN0_PAD 1
+#elif (RTE_I2S1_DIN0_PORT_ID == 4)
+#define RTE_I2S1_DIN0_PORT RTE_ULP_PORT
+#define RTE_I2S1_DIN0_PIN 12
+#define RTE_I2S1_DIN0_MUX 2
+#define RTE_I2S1_DIN0_PAD 7
+#elif (RTE_I2S1_DIN0_PORT_ID == 5)
+#define RTE_I2S1_DIN0_PORT RTE_ULP_PORT
+#define RTE_I2S1_DIN0_PIN 47
+#define RTE_I2S1_DIN0_MUX 2
+#define RTE_I2S1_DIN0_PAD 11
+#else
+#error "Invalid I2S1 RTE_I2S1_DIN0 Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_I2S1_DIN0_PORT RTE_ULP_PORT
+#define RTE_I2S1_DIN0_MUX 2
+#if ((ULP_I2S_DIN0_LOC == 7) || (ULP_I2S_DIN0_LOC == 8) || (ULP_I2S_DIN0_LOC == 9))
+#define RTE_I2S1_DIN0_PIN (ULP_I2S_DIN0_PIN + GPIO_MAX_PIN)
+#define RTE_I2S1_DIN0_PAD 0
+#endif
+#if (ULP_I2S_DIN0_LOC == 18)
+#define RTE_I2S1_DIN0_PIN ULP_I2S_DIN0_PIN
+#define RTE_I2S1_DIN0_PAD 1
+#endif
+#if (ULP_I2S_DIN0_LOC == 19)
+#define RTE_I2S1_DIN0_PIN ULP_I2S_DIN0_PIN
+#define RTE_I2S1_DIN0_PAD 7
+#endif
+#if (ULP_I2S_DIN0_LOC == 20)
+#define RTE_I2S1_DIN0_PIN ULP_I2S_DIN0_PIN
+#define RTE_I2S1_DIN0_PAD 11
+#endif
+//Pintool data
+#endif
+
+// FIFO level can have value 0 to 7
+#define I2S1_TX_FIFO_LEVEL (0U)
+#define I2S1_RX_FIFO_LEVEL (2U)
+
+// I2S1_TX_RES <0=>12
+// <1=>16
+// <2=>20
+// <3=>24
+#define RTE_I2S1_TX_RES 1
+#if (RTE_I2S1_TX_RES == 0)
+#define I2S1_TX_RES RES_12_BIT
+#elif (RTE_I2S1_TX_RES == 1)
+#define I2S1_TX_RES RES_16_BIT
+#elif (RTE_I2S1_TX_RES == 2)
+#define I2S1_TX_RES RES_20_BIT
+#elif (RTE_I2S1_TX_RES == 3)
+#define I2S1_TX_RES RES_24_BIT
+#else
+#error "Invalid I2S1 TX channel resolution!"
+#endif
+
+// I2S1_RX_RES <0=>12
+// <1=>16
+// <2=>20
+// <3=>24
+#define RTE_I2S1_RX_RES 1
+#if (RTE_I2S1_RX_RES == 0)
+#define I2S1_RX_RES RES_12_BIT
+#elif (RTE_I2S1_RX_RES == 1)
+#define I2S1_RX_RES RES_16_BIT
+#elif (RTE_I2S1_RX_RES == 2)
+#define I2S1_RX_RES RES_20_BIT
+#elif (RTE_I2S1_RX_RES == 3)
+#define I2S1_RX_RES RES_24_BIT
+#else
+#error "Invalid I2S1 RX channel resolution!"
+#endif
+
+#define RTE_I2S1_CHNL_UDMA_TX_EN 1
+#define RTE_I2S1_CHNL_UDMA_TX_CH 7
+
+#define RTE_I2S1_CHNL_UDMA_RX_EN 1
+#define RTE_I2S1_CHNL_UDMA_RX_CH 6
+
+#define RTE_I2S1_DMA_TX_LEN_PER_DES 1024
+#define RTE_I2S1_DMA_RX_LEN_PER_DES 1024
+
+// I2S1 [Driver_I2S1]
+
+// I2C0 (Inter-integrated Circuit Interface 0) [Driver_I2C0]
+// Configuration settings for Driver_I2C0 in component ::Drivers:I2C
+
+#define RTE_I2C0 1
+#define I2C0_IRQHandler IRQ042_Handler
+
+// I2C0_SCL Pin <0=>P0_7 <1=>P0_65 <2=>P0_66 <3=>P0_75 <4=>P0_32
+#ifndef I2C0_SCL_LOC
+#define RTE_I2C0_SCL_PORT_ID 1
+
+#if (RTE_I2C0_SCL_PORT_ID == 0)
+#define RTE_I2C0_SCL_PORT 0
+#define RTE_I2C0_SCL_PIN 7
+#define RTE_I2C0_SCL_MUX 4
+#define RTE_I2C0_SCL_PAD 2
+#define RTE_I2C0_SCL_I2C_REN 7
+#elif (RTE_I2C0_SCL_PORT_ID == 1)
+#define RTE_I2C0_SCL_PORT 0
+#define RTE_I2C0_SCL_PIN 65
+#define RTE_I2C0_SCL_MUX 4
+#define RTE_I2C0_SCL_PAD 23
+#define RTE_I2C0_SCL_I2C_REN 1
+#elif (RTE_I2C0_SCL_PORT_ID == 2)
+#define RTE_I2C0_SCL_PORT 0
+#define RTE_I2C0_SCL_PIN 66
+#define RTE_I2C0_SCL_MUX 4
+#define RTE_I2C0_SCL_PAD 24
+#define RTE_I2C0_SCL_I2C_REN 2
+#elif (RTE_I2C0_SCL_PORT_ID == 3)
+#define RTE_I2C0_SCL_PORT 0
+#define RTE_I2C0_SCL_PIN 75
+#define RTE_I2C0_SCL_MUX 4
+#define RTE_I2C0_SCL_PAD 33
+#define RTE_I2C0_SCL_I2C_REN 11
+#elif (RTE_I2C0_SCL_PORT_ID == 4)
+#define RTE_I2C0_SCL_PORT 0
+#define RTE_I2C0_SCL_PIN 32
+#define RTE_I2C0_SCL_MUX 11
+#define RTE_I2C0_SCL_PAD 9
+#define RTE_I2C0_SCL_I2C_REN 32
+#else
+#error "Invalid I2C0 RTE_I2C0_SCL Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_I2C0_SCL_PORT HP
+#if (I2C0_SCL_LOC == 0)
+#define RTE_I2C0_SCL_PIN I2C0_SCL_PIN
+#define RTE_I2C0_SCL_MUX 4
+#define RTE_I2C0_SCL_PAD 2
+#define RTE_I2C0_SCL_I2C_REN 7
+#endif
+#if (I2C0_SCL_LOC == 1)
+#define RTE_I2C0_SCL_PIN (I2C0_SCL_PIN + GPIO_MAX_PIN)
+#define RTE_I2C0_SCL_MUX 4
+#define RTE_I2C0_SCL_PAD 23
+#define RTE_I2C0_SCL_I2C_REN 1
+#endif
+#if (I2C0_SCL_LOC == 2)
+#define RTE_I2C0_SCL_PIN (I2C0_SCL_PIN + GPIO_MAX_PIN)
+#define RTE_I2C0_SCL_MUX 4
+#define RTE_I2C0_SCL_PAD 33
+#define RTE_I2C0_SCL_I2C_REN 11
+#endif
+#if (I2C0_SCL_LOC == 7)
+#define RTE_I2C0_SCL_PIN I2C0_SCL_PIN
+#define RTE_I2C0_SCL_MUX 11
+#define RTE_I2C0_SCL_PAD 9
+#define RTE_I2C0_SCL_I2C_REN 32
+#endif
+//Pintool data
+#endif
+
+// I2C0_SCL Pin <0=>P0_6 <1=>P0_64 <2=>P0_67 <3=>P0_74 <4=>P0_31
+#ifndef I2C0_SDA_LOC
+#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
+#define RTE_I2C0_SDA_PORT_ID 2
+#else
+#define RTE_I2C0_SDA_PORT_ID 0
+#endif
+
+#if (RTE_I2C0_SDA_PORT_ID == 0)
+#define RTE_I2C0_SDA_PORT 0
+#define RTE_I2C0_SDA_PIN 6
+#define RTE_I2C0_SDA_MUX 4
+#define RTE_I2C0_SDA_PAD 1
+#define RTE_I2C0_SDA_I2C_REN 6
+#elif (RTE_I2C0_SDA_PORT_ID == 1)
+#define RTE_I2C0_SDA_PORT 0
+#define RTE_I2C0_SDA_PIN 67
+#define RTE_I2C0_SDA_MUX 4
+#define RTE_I2C0_SDA_PAD 25
+#define RTE_I2C0_SDA_I2C_REN 3
+#elif (RTE_I2C0_SDA_PORT_ID == 2)
+#define RTE_I2C0_SDA_PORT 0
+#define RTE_I2C0_SDA_PIN 74
+#define RTE_I2C0_SDA_MUX 4
+#define RTE_I2C0_SDA_PAD 32
+#define RTE_I2C0_SDA_I2C_REN 10
+#elif (RTE_I2C0_SDA_PORT_ID == 3)
+#define RTE_I2C0_SDA_PORT 0
+#define RTE_I2C0_SDA_PIN 31
+#define RTE_I2C0_SDA_MUX 11
+#define RTE_I2C0_SDA_PAD 9
+#define RTE_I2C0_SDA_I2C_REN 31
+#else
+#error "Invalid I2C0 RTE_I2C0_SDA Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_I2C0_SDA_PORT HP
+#if (I2C0_SDA_LOC == 3)
+#define RTE_I2C0_SDA_PIN I2C0_SDA_PIN
+#define RTE_I2C0_SDA_MUX 4
+#define RTE_I2C0_SDA_PAD 1
+#define RTE_I2C0_SDA_I2C_REN 6
+#endif
+#if (I2C0_SDA_LOC == 4)
+#define RTE_I2C0_SDA_PIN (I2C0_SDA_PIN + GPIO_MAX_PIN)
+#define RTE_I2C0_SDA_MUX 4
+#define RTE_I2C0_SDA_PAD 22
+#define RTE_I2C0_SDA_I2C_REN 3
+#endif
+#if (I2C0_SDA_LOC == 5)
+#define RTE_I2C0_SDA_PIN (I2C0_SDA_PIN + GPIO_MAX_PIN)
+#define RTE_I2C0_SDA_MUX 4
+#define RTE_I2C0_SDA_PAD 32
+#define RTE_I2C0_SDA_I2C_REN 10
+#endif
+#if (I2C0_SDA_LOC == 6)
+#define RTE_I2C0_SDA_PIN I2C0_SDA_PIN
+#define RTE_I2C0_SDA_MUX 11
+#define RTE_I2C0_SDA_PAD 9
+#define RTE_I2C0_SDA_I2C_REN 31
+#endif
+//Pintool data
+#endif
+
+#define IC_SCL_STUCK_TIMEOUT 20
+#define IC_SDA_STUCK_TIMEOUT 20
+
+#define I2C_DMA 0
+#if (I2C_DMA == 1)
+#define DMA_TX_TL 1
+#define DMA_RX_TL 1
+#endif
+// I2C1 [Driver_I2C0]
+
+// I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1]
+// Configuration settings for Driver_I2C1 in component ::Drivers:I2C
+
+#define RTE_I2C1 1
+#define I2C1_IRQHandler IRQ061_Handler
+// I2C1_SCL Pin <0=>P0_6 <1=>P0_29 <2=>P0_50 <3=>P0_54 <4=>P0_64 <4=>P0_66 <4=>P0_70 <7=>P0_33
+#ifndef I2C1_SCL_LOC
+#define RTE_I2C1_SCL_PORT_ID 2
+
+#if (RTE_I2C1_SCL_PORT_ID == 0)
+#define RTE_I2C1_SCL_PORT HP
+#define RTE_I2C1_SCL_PIN 6
+#define RTE_I2C1_SCL_MUX 5
+#define RTE_I2C1_SCL_PAD 1
+#define RTE_I2C1_SCL_REN 6
+#elif (RTE_I2C1_SCL_PORT_ID == 1)
+#define RTE_I2C1_SCL_PORT HP
+#define RTE_I2C1_SCL_PIN 29
+#define RTE_I2C1_SCL_MUX 5
+#define RTE_I2C1_SCL_PAD 0 //no pad
+#define RTE_I2C1_SCL_REN 29
+#elif (RTE_I2C1_SCL_PORT_ID == 2)
+#define RTE_I2C1_SCL_PORT HP
+#define RTE_I2C1_SCL_PIN 50
+#define RTE_I2C1_SCL_MUX 5
+#define RTE_I2C1_SCL_PAD 14
+#define RTE_I2C1_SCL_REN 50
+#elif (RTE_I2C1_SCL_PORT_ID == 3)
+#define RTE_I2C1_SCL_PORT HP
+#define RTE_I2C1_SCL_PIN 54
+#define RTE_I2C1_SCL_MUX 5
+#define RTE_I2C1_SCL_PAD 18
+#define RTE_I2C1_SCL_REN 54
+#elif (RTE_I2C1_SCL_PORT_ID == 5)
+#define RTE_I2C1_SCL_PORT HP
+#define RTE_I2C1_SCL_PIN 66
+#define RTE_I2C1_SCL_MUX 5
+#define RTE_I2C1_SCL_PAD 24
+#define RTE_I2C1_SCL_REN 2
+#elif (RTE_I2C1_SCL_PORT_ID == 6)
+#define RTE_I2C1_SCL_PORT HP
+#define RTE_I2C1_SCL_PIN 70
+#define RTE_I2C1_SCL_MUX 5
+#define RTE_I2C1_SCL_PAD 28
+#define RTE_I2C1_SCL_REN 6
+#elif (RTE_I2C1_SCL_PORT_ID == 7)
+#define RTE_I2C1_SCL_PORT HP
+#define RTE_I2C1_SCL_PIN 33
+#define RTE_I2C1_SCL_MUX 11
+#define RTE_I2C1_SCL_PAD 9
+#define RTE_I2C1_SCL_REN 33
+#else
+#error "Invalid I2C1_SCL Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_I2C1_SCL_PORT HP
+#if (I2C1_SCL_LOC == 0)
+#define RTE_I2C1_SCL_PIN I2C1_SCL_PIN
+#define RTE_I2C1_SCL_MUX 5
+#define RTE_I2C1_SCL_PAD 1
+#define RTE_I2C1_SCL_REN 6
+#endif
+#if (I2C1_SCL_LOC == 1)
+#define RTE_I2C1_SCL_PIN I2C1_SCL_PIN
+#define RTE_I2C1_SCL_MUX 5
+#define RTE_I2C1_SCL_PAD 0 //no pad
+#define RTE_I2C1_SCL_REN 29
+#endif
+#if (I2C1_SCL_LOC == 2)
+#define RTE_I2C1_SCL_PIN I2C1_SCL_PIN
+#define RTE_I2C1_SCL_MUX 5
+#define RTE_I2C1_SCL_PAD 14
+#define RTE_I2C1_SCL_REN 50
+#endif
+#if (I2C1_SCL_LOC == 3)
+#define RTE_I2C1_SCL_PIN I2C1_SCL_PIN
+#define RTE_I2C1_SCL_MUX 5
+#define RTE_I2C1_SCL_PAD 18
+#define RTE_I2C1_SCL_REN 54
+#endif
+#if (I2C1_SCL_LOC == 4)
+#define RTE_I2C1_SCL_PIN (I2C1_SCL_PIN + GPIO_MAX_PIN)
+#define RTE_I2C1_SCL_MUX 5
+#define RTE_I2C1_SCL_PAD 22
+#define RTE_I2C1_SCL_REN 2
+#endif
+#if (I2C1_SCL_LOC == 5)
+#define RTE_I2C1_SCL_PIN (I2C1_SCL_PIN + GPIO_MAX_PIN)
+#define RTE_I2C1_SCL_MUX 5
+#define RTE_I2C1_SCL_PAD 28
+#define RTE_I2C1_SCL_REN 6
+#endif
+#if (I2C1_SCL_LOC == 12)
+#define RTE_I2C1_SCL_PIN I2C1_SCL_PIN
+#define RTE_I2C1_SCL_MUX 11
+#define RTE_I2C1_SCL_PAD 9
+#define RTE_I2C1_SCL_REN 33
+#endif
+//Pintool data
+#endif
+
+// I2C1_SCL Pin <0=>P0_7 <1=>P0_30 <2=>P0_51 <3=>P0_55 <4=>P0_65 <4=>P0_67 <4=>P0_71 <7=>P0_34
+#ifndef I2C1_SDA_LOC
+#define RTE_I2C1_SDA_PORT_ID 2
+
+#if (RTE_I2C1_SDA_PORT_ID == 0)
+#define RTE_I2C1_SDA_PORT HP
+#define RTE_I2C1_SDA_PIN 7
+#define RTE_I2C1_SDA_MUX 5
+#define RTE_I2C1_SDA_PAD 2
+#define RTE_I2C1_SDA_REN 7
+#elif (RTE_I2C1_SDA_PORT_ID == 1)
+#define RTE_I2C1_SDA_PORT HP
+#define RTE_I2C1_SDA_PIN 30
+#define RTE_I2C1_SDA_MUX 5
+#define RTE_I2C1_SDA_PAD 0 //no pad
+#define RTE_I2C1_SDA_REN 30
+#elif (RTE_I2C1_SDA_PORT_ID == 2)
+#define RTE_I2C1_SDA_PORT HP
+#define RTE_I2C1_SDA_PIN 51
+#define RTE_I2C1_SDA_MUX 5
+#define RTE_I2C1_SDA_PAD 15
+#define RTE_I2C1_SDA_REN 51
+#elif (RTE_I2C1_SDA_PORT_ID == 3)
+#define RTE_I2C1_SDA_PORT HP
+#define RTE_I2C1_SDA_PIN 55
+#define RTE_I2C1_SDA_MUX 5
+#define RTE_I2C1_SDA_PAD 19
+#define RTE_I2C1_SDA_REN 55
+#elif (RTE_I2C1_SDA_PORT_ID == 4)
+#define RTE_I2C1_SDA_PORT HP
+#define RTE_I2C1_SDA_PIN 65
+#define RTE_I2C1_SDA_MUX 5
+#define RTE_I2C1_SDA_PAD 23
+#define RTE_I2C1_SDA_REN 1
+#elif (RTE_I2C1_SDA_PORT_ID == 5)
+#define RTE_I2C1_SDA_PORT HP
+#define RTE_I2C1_SDA_PIN 67
+#define RTE_I2C1_SDA_MUX 5
+#define RTE_I2C1_SDA_PAD 25
+#define RTE_I2C1_SDA_REN 3
+#elif (RTE_I2C1_SDA_PORT_ID == 6)
+#define RTE_I2C1_SDA_PORT HP
+#define RTE_I2C1_SDA_PIN 71
+#define RTE_I2C1_SDA_MUX 5
+#define RTE_I2C1_SDA_PAD 29
+#define RTE_I2C1_SDA_REN 7
+#elif (RTE_I2C1_SDA_PORT_ID == 7)
+#define RTE_I2C1_SDA_PORT HP
+#define RTE_I2C1_SDA_PIN 34
+#define RTE_I2C1_SDA_MUX 11
+#define RTE_I2C1_SDA_PAD 9
+#define RTE_I2C1_SDA_REN 34
+#else
+#error "Invalid I2C1_SDA Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_I2C1_SDA_PORT HP
+#if (I2C1_SDA_LOC == 6)
+#define RTE_I2C1_SDA_PIN I2C1_SDA_PIN
+#define RTE_I2C1_SDA_MUX 5
+#define RTE_I2C1_SDA_PAD 2
+#define RTE_I2C1_SDA_REN 7
+#endif
+#if (I2C1_SDA_LOC == 7)
+#define RTE_I2C1_SDA_PIN I2C1_SDA_PIN
+#define RTE_I2C1_SDA_MUX 5
+#define RTE_I2C1_SDA_PAD 0 //no pad
+#define RTE_I2C1_SDA_REN 30
+#endif
+#if (I2C1_SDA_LOC == 8)
+#define RTE_I2C1_SDA_PIN I2C1_SDA_PIN
+#define RTE_I2C1_SDA_MUX 5
+#define RTE_I2C1_SDA_PAD 15
+#define RTE_I2C1_SDA_REN 51
+#endif
+#if (I2C1_SDA_LOC == 9)
+#define RTE_I2C1_SDA_PIN I2C1_SDA_PIN
+#define RTE_I2C1_SDA_MUX 5
+#define RTE_I2C1_SDA_PAD 19
+#define RTE_I2C1_SDA_REN 55
+#endif
+#if (I2C1_SDA_LOC == 10)
+#define RTE_I2C1_SDA_PIN (I2C1_SDA_PIN + GPIO_MAX_PIN)
+#define RTE_I2C1_SDA_MUX 5
+#define RTE_I2C1_SDA_PAD 23
+#define RTE_I2C1_SDA_REN 1
+#endif
+#if (I2C1_SDA_LOC == 11)
+#define RTE_I2C1_SDA_PIN (I2C1_SDA_PIN + GPIO_MAX_PIN)
+#define RTE_I2C1_SDA_MUX 5
+#define RTE_I2C1_SDA_PAD 29
+#define RTE_I2C1_SDA_REN 7
+#endif
+#if (I2C1_SDA_LOC == 13)
+#define RTE_I2C1_SDA_PIN I2C1_SDA_PIN
+#define RTE_I2C1_SDA_MUX 11
+#define RTE_I2C1_SDA_PAD 9
+#define RTE_I2C1_SDA_REN 34
+#endif
+//Pintool data
+#endif
+
+#define IC_SCL_STUCK_TIMEOUT 20
+#define IC_SDA_STUCK_TIMEOUT 20
+
+#define DMA_EN 0
+#if (DMA_EN == 1)
+#define DMA_TX_TL 1
+#define DMA_RX_TL 1
+#endif
+
+// I2C1 [Driver_I2C1]
+
+// ULP I2C (Inter-integrated Circuit Interface 2) [Driver_I2C2]
+// Configuration settings for Driver_I2C2 in component ::Drivers:I2C
+#define RTE_I2C2 1
+#define I2C2_IRQHandler IRQ013_Handler
+
+// I2C2_SCL Pin <0=>P0_1 <1=>P0_5 <2=>P0_7 <3=>P0_8 <4=>P0_13
+#ifndef ULP_I2C_SCL_LOC
+#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
+#define RTE_I2C2_SCL_PORT_ID 0
+#else
+#define RTE_I2C2_SCL_PORT_ID 0
+#endif
+#if (RTE_I2C2_SCL_PORT_ID == 0)
+#define RTE_I2C2_SCL_PORT RTE_ULP_PORT
+#define RTE_I2C2_SCL_PIN (7 + GPIO_MAX_PIN)
+#define RTE_I2C2_SCL_MUX 4
+#define RTE_I2C2_SCL_REN 7
+#define RTE_I2C2_SCL_PAD 0
+#elif (RTE_I2C2_SCL_PORT_ID == 1)
+#define RTE_I2C2_SCL_PORT RTE_ULP_PORT
+#define RTE_I2C2_SCL_PIN (8 + GPIO_MAX_PIN)
+#define RTE_I2C2_SCL_MUX 4
+#define RTE_I2C2_SCL_REN 8
+#define RTE_I2C2_SCL_PAD 0
+#elif (RTE_I2C2_SCL_PORT_ID == 2)
+#define RTE_I2C2_SCL_PORT RTE_ULP_PORT
+#define RTE_I2C2_SCL_PIN (1 + GPIO_MAX_PIN)
+#define RTE_I2C2_SCL_MUX 4
+#define RTE_I2C2_SCL_REN 1
+#define RTE_I2C2_SCL_PAD 0
+#elif (RTE_I2C2_SCL_PORT_ID == 3)
+#define RTE_I2C2_SCL_PORT RTE_ULP_PORT
+#define RTE_I2C2_SCL_PIN 7
+#define RTE_I2C2_SCL_MUX 4
+#define RTE_I2C2_SCL_REN 7
+#define RTE_I2C2_SCL_PAD 2
+#elif (RTE_I2C2_SCL_PORT_ID == 4)
+#define RTE_I2C2_SCL_PORT RTE_ULP_PORT
+#define RTE_I2C2_SCL_PIN 11
+#define RTE_I2C2_SCL_MUX 4
+#define RTE_I2C2_SCL_REN 11
+#define RTE_I2C2_SCL_PAD 6
+#elif (RTE_I2C2_SCL_PORT_ID == 5)
+#define RTE_I2C2_SCL_PORT RTE_ULP_PORT
+#define RTE_I2C2_SCL_PIN 15
+#define RTE_I2C2_SCL_MUX 4
+#define RTE_I2C2_SCL_REN 15
+#define RTE_I2C2_SCL_PAD 8
+#elif (RTE_I2C2_SCL_PORT_ID == 6)
+#define RTE_I2C2_SCL_PORT RTE_ULP_PORT
+#define RTE_I2C2_SCL_PIN 46
+#define RTE_I2C2_SCL_MUX 4
+#define RTE_I2C2_SCL_REN 46
+#define RTE_I2C2_SCL_PAD 10
+#else
+#error "Invalid I2C2_SCL Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_I2C2_SCL_PORT RTE_ULP_PORT
+#define RTE_I2C2_SCL_MUX 4
+#if (ULP_I2C_SCL_LOC == 0)
+#define RTE_I2C2_SCL_PIN (ULP_I2C_SCL_PIN + GPIO_MAX_PIN)
+#define RTE_I2C2_SCL_REN 1
+#define RTE_I2C2_SCL_PAD 0
+#endif
+#if (ULP_I2C_SCL_LOC == 1)
+#define RTE_I2C2_SCL_PIN (ULP_I2C_SCL_PIN + GPIO_MAX_PIN)
+#define RTE_I2C2_SCL_REN 5
+#define RTE_I2C2_SCL_PAD 0
+#endif
+#if (ULP_I2C_SCL_LOC == 2)
+#define RTE_I2C2_SCL_PIN (ULP_I2C_SCL_PIN + GPIO_MAX_PIN)
+#define RTE_I2C2_SCL_REN 7
+#define RTE_I2C2_SCL_PAD 0
+#endif
+#if (ULP_I2C_SCL_LOC == 3)
+#define RTE_I2C2_SCL_PIN (ULP_I2C_SCL_PIN + GPIO_MAX_PIN)
+#define RTE_I2C2_SCL_REN 8
+#define RTE_I2C2_SCL_PAD 0
+#endif
+#if (ULP_I2C_SCL_LOC == 9)
+#define RTE_I2C2_SCL_PIN ULP_I2C_SCL_PIN
+#define RTE_I2C2_SCL_REN 7
+#define RTE_I2C2_SCL_PAD 2
+#endif
+#if (ULP_I2C_SCL_LOC == 10)
+#define RTE_I2C2_SCL_PIN ULP_I2C_SCL_PIN
+#define RTE_I2C2_SCL_REN 11
+#define RTE_I2C2_SCL_PAD 6
+#endif
+#if (ULP_I2C_SCL_LOC == 11)
+#define RTE_I2C2_SCL_PIN ULP_I2C_SCL_PIN
+#define RTE_I2C2_SCL_REN 15
+#define RTE_I2C2_SCL_PAD 8
+#endif
+#if (ULP_I2C_SCL_LOC == 12)
+#define RTE_I2C2_SCL_PIN ULP_I2C_SCL_PIN
+#define RTE_I2C2_SCL_REN 46
+#define RTE_I2C2_SCL_PAD 10
+#endif
+//Pintool data
+#endif
+
+// I2C2_SDA Pin <0=>P0_0 <1=>P0_4 <2=>P0_6 <3=>P0_9 <4=>P0_11 <5=>P0_12
+#ifndef ULP_I2C_SDA_LOC
+#define RTE_I2C2_SDA_PORT_ID 0
+#if (RTE_I2C2_SDA_PORT_ID == 0)
+#define RTE_I2C2_SDA_PORT RTE_ULP_PORT
+#define RTE_I2C2_SDA_PIN (6 + GPIO_MAX_PIN)
+#define RTE_I2C2_SDA_MUX 4
+#define RTE_I2C2_SDA_REN 6
+#define RTE_I2C2_SDA_PAD 0
+#elif (RTE_I2C2_SDA_PORT_ID == 1)
+#define RTE_I2C2_SDA_PORT RTE_ULP_PORT
+#define RTE_I2C2_SDA_PIN (9 + GPIO_MAX_PIN)
+#define RTE_I2C2_SDA_MUX 4
+#define RTE_I2C2_SDA_REN 9
+#define RTE_I2C2_SDA_PAD 0
+#elif (RTE_I2C2_SDA_PORT_ID == 2)
+#define RTE_I2C2_SDA_PORT RTE_ULP_PORT
+#define RTE_I2C2_SDA_PIN (11 + GPIO_MAX_PIN)
+#define RTE_I2C2_SDA_MUX 4
+#define RTE_I2C2_SDA_REN 11
+#define RTE_I2C2_SDA_PAD 0
+#elif (RTE_I2C2_SDA_PORT_ID == 3)
+#define RTE_I2C2_SDA_PORT RTE_ULP_PORT
+#define RTE_I2C2_SDA_PIN 6
+#define RTE_I2C2_SDA_MUX 4
+#define RTE_I2C2_SDA_REN 6
+#define RTE_I2C2_SDA_PAD 1
+#elif (RTE_I2C2_SDA_PORT_ID == 4)
+#define RTE_I2C2_SDA_PORT RTE_ULP_PORT
+#define RTE_I2C2_SDA_PIN 10
+#define RTE_I2C2_SDA_MUX 4
+#define RTE_I2C2_SDA_REN 10
+#define RTE_I2C2_SDA_PAD 5
+#elif (RTE_I2C2_SDA_PORT_ID == 5)
+#define RTE_I2C2_SDA_PORT RTE_ULP_PORT
+#define RTE_I2C2_SDA_PIN 12
+#define RTE_I2C2_SDA_MUX 4
+#define RTE_I2C2_SDA_REN 12
+#define RTE_I2C2_SDA_PAD 7
+#elif (RTE_I2C2_SDA_PORT_ID == 6)
+#define RTE_I2C2_SDA_PORT RTE_ULP_PORT
+#define RTE_I2C2_SDA_PIN 47
+#define RTE_I2C2_SDA_MUX 4
+#define RTE_I2C2_SDA_REN 47
+#define RTE_I2C2_SDA_PAD 11
+#elif (RTE_I2C2_SDA_PORT_ID == 7)
+#define RTE_I2C2_SDA_PORT RTE_ULP_PORT
+#define RTE_I2C2_SDA_PIN 49
+#define RTE_I2C2_SDA_MUX 4
+#define RTE_I2C2_SDA_REN 49
+#define RTE_I2C2_SDA_PAD 13
+#else
+#error "Invalid I2C2_SDA Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_I2C2_SDA_PORT RTE_ULP_PORT
+#define RTE_I2C2_SDA_MUX 4
+#if (ULP_I2C_SDA_LOC == 4)
+#define RTE_I2C2_SDA_PIN (ULP_I2C_SDA_PIN + GPIO_MAX_PIN)
+#define RTE_I2C2_SDA_REN 0
+#define RTE_I2C2_SDA_PAD 0
+#endif
+#if (ULP_I2C_SCL_LOC == 5)
+#define RTE_I2C2_SDA_PIN (ULP_I2C_SDA_PIN + GPIO_MAX_PIN)
+#define RTE_I2C2_SDA_REN 4
+#define RTE_I2C2_SDA_PAD 0
+#endif
+#if (ULP_I2C_SDA_LOC == 6)
+#define RTE_I2C2_SDA_PIN (ULP_I2C_SDA_PIN + GPIO_MAX_PIN)
+#define RTE_I2C2_SDA_REN 0
+#define RTE_I2C2_SDA_PAD 0
+#endif
+#if (ULP_I2C_SDA_LOC == 7)
+#define RTE_I2C2_SDA_PIN (ULP_I2C_SDA_PIN + GPIO_MAX_PIN)
+#define RTE_I2C2_SDA_REN 9
+#define RTE_I2C2_SDA_PAD 0
+#endif
+#if (ULP_I2C_SDA_LOC == 8)
+#define RTE_I2C2_SDA_PIN (ULP_I2C_SDA_PIN + GPIO_MAX_PIN)
+#define RTE_I2C2_SDA_REN 11
+#define RTE_I2C2_SDA_PAD 0
+#endif
+#if (ULP_I2C_SDA_LOC == 13)
+#define RTE_I2C2_SDA_PIN ULP_I2C_SDA_PIN
+#define RTE_I2C2_SDA_REN 6
+#define RTE_I2C2_SDA_PAD 1
+#endif
+#if (ULP_I2C_SDA_LOC == 14)
+#define RTE_I2C2_SDA_PIN ULP_I2C_SDA_PIN
+#define RTE_I2C2_SDA_REN 10
+#define RTE_I2C2_SDA_PAD 5
+#endif
+#if (ULP_I2C_SDA_LOC == 15)
+#define RTE_I2C2_SDA_PIN ULP_I2C_SDA_PIN
+#define RTE_I2C2_SDA_REN 12
+#define RTE_I2C2_SDA_PAD 7
+#endif
+#if (ULP_I2C_SDA_LOC == 16)
+#define RTE_I2C2_SDA_PIN ULP_I2C_SDA_PIN
+#define RTE_I2C2_SDA_REN 47
+#define RTE_I2C2_SDA_PAD 11
+#endif
+#if (ULP_I2C_SDA_LOC == 17)
+#define RTE_I2C2_SDA_PIN ULP_I2C_SDA_PIN
+#define RTE_I2C2_SDA_REN 49
+#define RTE_I2C2_SDA_PAD 13
+#endif
+//Pintool data
+#endif
+
+#define IC_SCL_STUCK_TIMEOUT 20
+#define IC_SDA_STUCK_TIMEOUT 20
+
+#define DMA_EN 0
+#if (DMA_EN == 1)
+#define DMA_TX_TL 1
+#define DMA_RX_TL 1
+#endif
+
+// I2C2 [Driver_I2C2]
+
+// GSPI (Generic SPI master) [Driver_GSPI_MASTER]
+// Configuration settings for Driver_GSPI_MASTER in component ::Drivers:GSPI
+#define RTE_GSPI_MASTER 1
+
+// GSPI_MASTER_CLK <0=>P0_8 <1=>P0_25 <2=>P0_46 <3=>P0_52
+// CLK of GSPI0
+#ifndef GSPI_MASTER_SCK_LOC
+#define RTE_GSPI_MASTER_CLK_PORT_ID 1
+
+#if (RTE_GSPI_MASTER_CLK_PORT_ID == 0)
+#define RTE_GSPI_MASTER_CLK_PORT HP
+#define RTE_GSPI_MASTER_CLK_PIN 8
+#define RTE_GSPI_MASTER_CLK_MUX 4
+#define RTE_GSPI_MASTER_CLK_PAD 3
+#elif (RTE_GSPI_MASTER_CLK_PORT_ID == 1)
+#define RTE_GSPI_MASTER_CLK_PORT HP
+#define RTE_GSPI_MASTER_CLK_PIN 25
+#define RTE_GSPI_MASTER_CLK_MUX 4
+#define RTE_GSPI_MASTER_CLK_PAD 0 //NO PAD
+#elif (RTE_GSPI_MASTER_CLK_PORT_ID == 2)
+#define RTE_GSPI_MASTER_CLK_PORT HP
+#define RTE_GSPI_MASTER_CLK_PIN 46
+#define RTE_GSPI_MASTER_CLK_MUX 4
+#define RTE_GSPI_MASTER_CLK_PAD 10
+#elif (RTE_GSPI_MASTER_CLK_PORT_ID == 3)
+#define RTE_GSPI_MASTER_CLK_PORT HP
+#define RTE_GSPI_MASTER_CLK_PIN 52
+#define RTE_GSPI_MASTER_CLK_MUX 4
+#define RTE_GSPI_MASTER_CLK_PAD 16
+#else
+#error "Invalid GSPI0 RTE_GSPI_MASTER_CLK_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_GSPI_MASTER_CLK_PORT HP
+#define RTE_GSPI_MASTER_CLK_PIN GSPI_MASTER_SCK__PIN
+#define RTE_GSPI_MASTER_CLK_MUX 4
+#if (GSPI_MASTER_SCK_LOC == 0)
+#define RTE_GSPI_MASTER_CLK_PAD 3
+#endif
+#if (GSPI_MASTER_SCK_LOC == 1)
+#define RTE_GSPI_MASTER_CLK_PAD 0
+#endif
+#if (GSPI_MASTER_SCK_LOC == 2)
+#define RTE_GSPI_MASTER_CLK_PAD 10
+#endif
+#if (GSPI_MASTER_SCK_LOC == 3)
+#define RTE_GSPI_MASTER_CLK_PAD 16
+#endif
+//Pintool data
+#endif
+
+// GSPI_MASTER_CS0
+// <0=>P0_9 <1=>P0_28 <2=>P0_49 <3=>P0_53
+// CS0 of GSPI0
+//
+#ifndef GSPI_MASTER_CS0_LOC
+#define RTE_GSPI_MASTER_CS0_PORT_ID 1
+
+#if (RTE_GSPI_MASTER_CS0_PORT_ID == 0)
+#define RTE_GSPI_MASTER_CS0 1
+#define RTE_GSPI_MASTER_CS0_PORT HP
+#define RTE_GSPI_MASTER_CS0_PIN 9
+#define RTE_GSPI_MASTER_CS0_MUX 4
+#define RTE_GSPI_MASTER_CS0_PAD 4
+#elif (RTE_GSPI_MASTER_CS0_PORT_ID == 1)
+#define RTE_GSPI_MASTER_CS0 1
+#define RTE_GSPI_MASTER_CS0_PORT HP
+#define RTE_GSPI_MASTER_CS0_PIN 28
+#define RTE_GSPI_MASTER_CS0_MUX 4
+#define RTE_GSPI_MASTER_CS0_PAD 0 //NO PAD
+#elif (RTE_GSPI_MASTER_CS0_PORT_ID == 2)
+#define RTE_GSPI_MASTER_CS0 1
+#define RTE_GSPI_MASTER_CS0_PORT HP
+#define RTE_GSPI_MASTER_CS0_PIN 49
+#define RTE_GSPI_MASTER_CS0_MUX 4
+#define RTE_GSPI_MASTER_CS0_PAD 13
+#elif (RTE_GSPI_MASTER_CS0_PORT_ID == 3)
+#define RTE_GSPI_MASTER_CS0 1
+#define RTE_GSPI_MASTER_CS0_PORT HP
+#define RTE_GSPI_MASTER_CS0_PIN 53
+#define RTE_GSPI_MASTER_CS0_MUX 4
+#define RTE_GSPI_MASTER_CS0_PAD 17
+#else
+#error "Invalid GSPI0 RTE_GSPI_MASTER_CS0_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_GSPI_MASTER_CS0 1
+#define RTE_GSPI_MASTER_CS0_PORT HP
+#define RTE_GSPI_MASTER_CS0_PIN GSPI_MASTER_CS0__PIN
+#define RTE_GSPI_MASTER_CS0_MUX 4
+#if (GSPI_MASTER_CS0_LOC == 4)
+#define RTE_GSPI_MASTER_CS0_PAD 4
+#endif
+#if (GSPI_MASTER_CS0_LOC == 5)
+#define RTE_GSPI_MASTER_CS0_PAD 0
+#endif
+#if (GSPI_MASTER_CS0_LOC == 6)
+#define RTE_GSPI_MASTER_CS0_PAD 13
+#endif
+#if (GSPI_MASTER_CS0_LOC == 7)
+#define RTE_GSPI_MASTER_CS0_PAD 17
+#endif
+//Pintool data
+#endif
+
+// GSPI_MASTER_CS1
+// <0=>P0_10 <1=>P0_29 <2=>P0_50 <3=>P0_54
+// CS1 of GSPI0
+//
+#ifndef GSPI_MASTER_CS1_LOC
+#define RTE_GSPI_MASTER_CS1_PORT_ID 1
+#if (RTE_GSPI_MASTER_CS1_PORT_ID == 0)
+#define RTE_GSPI_MASTER_CS1 1
+#define RTE_GSPI_MASTER_CS1_PORT HP
+#define RTE_GSPI_MASTER_CS1_PIN 10
+#define RTE_GSPI_MASTER_CS1_MUX 4
+#define RTE_GSPI_MASTER_CS1_PAD 5
+#elif (RTE_GSPI_MASTER_CS1_PORT_ID == 1)
+#define RTE_GSPI_MASTER_CS1 1
+#define RTE_GSPI_MASTER_CS1_PORT HP
+#define RTE_GSPI_MASTER_CS1_PIN 29
+#define RTE_GSPI_MASTER_CS1_MUX 4
+#define RTE_GSPI_MASTER_CS1_PAD 0 //NO PAD
+#elif (RTE_GSPI_MASTER_CS1_PORT_ID == 2)
+#define RTE_GSPI_MASTER_CS1 1
+#define RTE_GSPI_MASTER_CS1_PORT HP
+#define RTE_GSPI_MASTER_CS1_PIN 50
+#define RTE_GSPI_MASTER_CS1_MUX 4
+#define RTE_GSPI_MASTER_CS1_PAD 14
+#elif (RTE_GSPI_MASTER_CS1_PORT_ID == 3)
+#define RTE_GSPI_MASTER_CS1 1
+#define RTE_GSPI_MASTER_CS1_PORT HP
+#define RTE_GSPI_MASTER_CS1_PIN 54
+#define RTE_GSPI_MASTER_CS1_MUX 4
+#define RTE_GSPI_MASTER_CS1_PAD 18
+#else
+#error "Invalid GSPI0 RTE_GSPI_MASTER_CS1_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_GSPI_MASTER_CS1 1
+#define RTE_GSPI_MASTER_CS1_PORT HP
+#define RTE_GSPI_MASTER_CS1_PIN GSPI_MASTER_CS1__PIN
+#define RTE_GSPI_MASTER_CS1_MUX 4
+#if (GSPI_MASTER_CS1_LOC == 8)
+#define RTE_GSPI_MASTER_CS1_PAD 5
+#endif
+#if (GSPI_MASTER_CS1_LOC == 9)
+#define RTE_GSPI_MASTER_CS1_PAD 0
+#endif
+#if (GSPI_MASTER_CS1_LOC == 10)
+#define RTE_GSPI_MASTER_CS1_PAD 14
+#endif
+#if (GSPI_MASTER_CS1_LOC == 11)
+#define RTE_GSPI_MASTER_CS1_PAD 18
+#endif
+//Pintool data
+#endif
+
+// GSPI_MASTER_CS2
+// <0=>P0_15 <1=>P0_30 <2=>P0_51 <3=>P0_55
+// CS2 of GSPI0
+//
+#ifndef GSPI_MASTER_CS2_LOC
+#define RTE_GSPI_MASTER_CS2_PORT_ID 1
+#if (RTE_GSPI_MASTER_CS2_PORT_ID == 0)
+#define RTE_GSPI_MASTER_CS2 1
+#define RTE_GSPI_MASTER_CS2_PORT HP
+#define RTE_GSPI_MASTER_CS2_PIN 15
+#define RTE_GSPI_MASTER_CS2_MUX 4
+#define RTE_GSPI_MASTER_CS2_PAD 8
+#elif (RTE_GSPI_MASTER_CS2_PORT_ID == 1)
+#define RTE_GSPI_MASTER_CS2 1
+#define RTE_GSPI_MASTER_CS2_PORT HP
+#define RTE_GSPI_MASTER_CS2_PIN 30
+#define RTE_GSPI_MASTER_CS2_MUX 4
+#define RTE_GSPI_MASTER_CS2_PAD 0 //NO PAD
+#elif (RTE_GSPI_MASTER_CS2_PORT_ID == 2)
+#define RTE_GSPI_MASTER_CS2 1
+#define RTE_GSPI_MASTER_CS2_PORT HP
+#define RTE_GSPI_MASTER_CS2_PIN 51
+#define RTE_GSPI_MASTER_CS2_MUX 4
+#define RTE_GSPI_MASTER_CS2_PAD 15
+#elif (RTE_GSPI_MASTER_CS2_PORT_ID == 3)
+#define RTE_GSPI_MASTER_CS2 1
+#define RTE_GSPI_MASTER_CS2_PORT HP
+#define RTE_GSPI_MASTER_CS2_PIN 55
+#define RTE_GSPI_MASTER_CS2_MUX 4
+#define RTE_GSPI_MASTER_CS2_PAD 19
+#else
+#error "Invalid GSPI0 RTE_GSPI_MASTER_CS2_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_GSPI_MASTER_CS2 1
+#define RTE_GSPI_MASTER_CS2_PORT HP
+#define RTE_GSPI_MASTER_CS2_PIN GSPI_MASTER_CS2__PIN
+#define RTE_GSPI_MASTER_CS2_MUX 4
+#if (GSPI_MASTER_CS2_LOC == 12)
+#define RTE_GSPI_MASTER_CS2_PAD 8
+#endif
+#if (GSPI_MASTER_CS2_LOC == 13)
+#define RTE_GSPI_MASTER_CS2_PAD 0
+#endif
+#if (GSPI_MASTER_CS2_LOC == 14)
+#define RTE_GSPI_MASTER_CS2_PAD 15
+#endif
+#if (GSPI_MASTER_CS2_LOC == 15)
+#define RTE_GSPI_MASTER_CS2_PAD 19
+#endif
+//Pintool data
+#endif
+
+// GSPI_MASTER_MOSI <0=>P0_12 <1=>P0_27 <2=>P0_48 <3=>P0_57 <4=>P0_6
+// MOSI of GSPI0
+#ifndef GSPI_MASTER_MOSI_LOC
+#define RTE_GSPI_MASTER_MOSI_PORT_ID 1
+
+#if (RTE_GSPI_MASTER_MOSI_PORT_ID == 0)
+#define RTE_GSPI_MASTER_MOSI_PORT HP
+#define RTE_GSPI_MASTER_MOSI_PIN 12
+#define RTE_GSPI_MASTER_MOSI_MUX 4
+#define RTE_GSPI_MASTER_MOSI_PAD 7
+#elif (RTE_GSPI_MASTER_MOSI_PORT_ID == 1)
+#define RTE_GSPI_MASTER_MOSI_PORT HP
+#define RTE_GSPI_MASTER_MOSI_PIN 27
+#define RTE_GSPI_MASTER_MOSI_MUX 4
+#define RTE_GSPI_MASTER_MOSI_PAD 0 //NO PAD
+#elif (RTE_GSPI_MASTER_MOSI_PORT_ID == 2)
+#define RTE_GSPI_MASTER_MOSI_PORT HP
+#define RTE_GSPI_MASTER_MOSI_PIN 48
+#define RTE_GSPI_MASTER_MOSI_MUX 4
+#define RTE_GSPI_MASTER_MOSI_PAD 12
+#elif (RTE_GSPI_MASTER_MOSI_PORT_ID == 3)
+#define RTE_GSPI_MASTER_MOSI_PORT HP
+#define RTE_GSPI_MASTER_MOSI_PIN 57
+#define RTE_GSPI_MASTER_MOSI_MUX 4
+#define RTE_GSPI_MASTER_MOSI_PAD 21
+#elif (RTE_GSPI_MASTER_MOSI_PORT_ID == 4)
+#define RTE_GSPI_MASTER_MOSI_PORT HP
+#define RTE_GSPI_MASTER_MOSI_PIN 6
+#define RTE_GSPI_MASTER_MOSI_MUX 12
+#define RTE_GSPI_MASTER_MOSI_PAD 1
+#else
+#error "Invalid GSPI0 RTE_GSPI_MASTER_MOSI_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_GSPI_MASTER_MOSI_PORT HP
+#define RTE_GSPI_MASTER_MOSI_PIN GSPI_MASTER_MOSI__PIN
+#if (GSPI_MASTER_MOSI_LOC == 16)
+#define RTE_GSPI_MASTER_MOSI_MUX 4
+#define RTE_GSPI_MASTER_MOSI_PAD 7
+#endif
+#if (GSPI_MASTER_MOSI_LOC == 17)
+#define RTE_GSPI_MASTER_MOSI_MUX 4
+#define RTE_GSPI_MASTER_MOSI_PAD 0
+#endif
+#if (GSPI_MASTER_MOSI_LOC == 18)
+#define RTE_GSPI_MASTER_MOSI_MUX 4
+#define RTE_GSPI_MASTER_MOSI_PAD 12
+#endif
+#if (GSPI_MASTER_MOSI_LOC == 19)
+#define RTE_GSPI_MASTER_MOSI_MUX 4
+#define RTE_GSPI_MASTER_MOSI_PAD 21
+#endif
+#if (GSPI_MASTER_MOSI_LOC == 20)
+#define RTE_GSPI_MASTER_MOSI_MUX 12
+#define RTE_GSPI_MASTER_MOSI_PAD 1
+#endif
+//Pintool data
+#endif
+
+// GSPI_MASTER_MISO <0=>P0_11 <1=>P0_26 <2=>P0_47 <3=>P0_56
+// MISO of GSPI0
+#ifndef GSPI_MASTER_MISO_LOC
+#define RTE_GSPI_MASTER_MISO_PORT_ID 1
+
+#if (RTE_GSPI_MASTER_MISO_PORT_ID == 0)
+#define RTE_GSPI_MASTER_MISO_PORT HP
+#define RTE_GSPI_MASTER_MISO_PIN 11
+#define RTE_GSPI_MASTER_MISO_MUX 4
+#define RTE_GSPI_MASTER_MISO_PAD 6
+#elif (RTE_GSPI_MASTER_MISO_PORT_ID == 1)
+#define RTE_GSPI_MASTER_MISO_PORT HP
+#define RTE_GSPI_MASTER_MISO_PIN 26
+#define RTE_GSPI_MASTER_MISO_MUX 4
+#define RTE_GSPI_MASTER_MISO_PAD 0 //NO PAD
+#elif (RTE_GSPI_MASTER_MISO_PORT_ID == 2)
+#define RTE_GSPI_MASTER_MISO_PORT HP
+#define RTE_GSPI_MASTER_MISO_PIN 47
+#define RTE_GSPI_MASTER_MISO_MUX 4
+#define RTE_GSPI_MASTER_MISO_PAD 11
+#elif (RTE_GSPI_MASTER_MISO_PORT_ID == 3)
+#define RTE_GSPI_MASTER_MISO_PORT HP
+#define RTE_GSPI_MASTER_MISO_PIN 56
+#define RTE_GSPI_MASTER_MISO_MUX 4
+#define RTE_GSPI_MASTER_MISO_PAD 20
+#else
+#error "Invalid GSPI0 RTE_GSPI_MASTER_MISO_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_GSPI_MASTER_MISO_PORT HP
+#define RTE_GSPI_MASTER_MISO_PIN GSPI_MASTER_MISO__PIN
+#define RTE_GSPI_MASTER_MISO_MUX 4
+#if (GSPI_MASTER_MISO_LOC == 21)
+#define RTE_GSPI_MASTER_MISO_PAD 6
+#endif
+#if (GSPI_MASTER_MISO_LOC == 22)
+#define RTE_GSPI_MASTER_MISO_PAD 0
+#endif
+#if (GSPI_MASTER_MISO_LOC == 23)
+#define RTE_GSPI_MASTER_MISO_PAD 11
+#endif
+#if (GSPI_MASTER_MISO_LOC == 24)
+#define RTE_GSPI_MASTER_MISO_PAD 20
+#endif
+//Pintool data
+#endif
+
+#if defined(HIGH_THROUGHPUT_EN) && (HIGH_THROUGHPUT_EN == ENABLE)
+#define RTE_GSPI_MASTER_CHNL_UDMA_TX_EN 1
+#define RTE_GSPI_MASTER_CHNL_UDMA_TX_CH 11
+
+#define RTE_GSPI_MASTER_CHNL_UDMA_RX_EN 1
+#define RTE_GSPI_MASTER_CHNL_UDMA_RX_CH 10
+
+#define RTE_FIFO_AFULL_THRLD 3
+#define RTE_FIFO_AEMPTY_THRLD 7
+
+#define TX_DMA_ARB_SIZE ARBSIZE_4
+#define RX_DMA_ARB_SIZE ARBSIZE_8
+#else
+#define RTE_GSPI_MASTER_CHNL_UDMA_TX_EN 0
+#define RTE_GSPI_MASTER_CHNL_UDMA_TX_CH 11
+
+#define RTE_GSPI_MASTER_CHNL_UDMA_RX_EN 0
+#define RTE_GSPI_MASTER_CHNL_UDMA_RX_CH 10
+
+#define RTE_FIFO_AFULL_THRLD 0
+#define RTE_FIFO_AEMPTY_THRLD 0
+
+#define TX_DMA_ARB_SIZE ARBSIZE_1
+#define RX_DMA_ARB_SIZE ARBSIZE_1
+#endif
+
+// (Generic SPI master)[Driver_GSPI_MASTER]
+
+// (State Configurable Timer) Interface
+#define SCT_CLOCK_SOURCE CT_INTFPLLCLK
+#define SCT_CLOCK_DIV_FACT 2
+
+//SCT_IN_0 <0=>GPIO_25 <1=>GPIO_64 <2=>GPIO_68
+
+#ifndef SCT_IN0_LOC
+#define RTE_SCT_IN_0_PORT_ID 0
+
+#if (RTE_SCT_IN_0_PORT_ID == 0)
+#define RTE_SCT_IN_0_PORT HP
+#define RTE_SCT_IN_0_PIN 25
+#define RTE_SCT_IN_0_MUX 9
+#define RTE_SCT_IN_0_PAD 0 //no pad
+#else
+#error "Invalid RTE_SCT_IN_0_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_SCT_IN_0_PORT HP
+#if (SCT_IN0_LOC == 0)
+#define RTE_SCT_IN_0_PIN SCT_IN0_PIN
+#define RTE_SCT_IN_0_MUX 9
+#define RTE_SCT_IN_0_PAD 0 //no pad
+#elif (SCT_IN0_LOC == 1)
+#define RTE_SCT_IN_0_PIN (SCT_IN0_PIN + GPIO_MAX_PIN)
+#define RTE_SCT_IN_0_MUX 7
+#define RTE_SCT_IN_0_PAD 22
+#elif (SCT_IN0_LOC == 2)
+#define RTE_SCT_IN_0_PIN (SCT_IN0_PIN + GPIO_MAX_PIN)
+#define RTE_SCT_IN_0_MUX 9
+#define RTE_SCT_IN_0_PAD 26
+#endif
+//Pintool data
+#endif
+
+//SCT_IN_1 <0=>GPIO_26 <1=>GPIO_65 <2=>GPIO_69
+#ifndef SCT_IN1_LOC
+#define RTE_SCT_IN_1_PORT_ID 1
+
+#if (RTE_SCT_IN_1_PORT_ID == 0)
+#define RTE_SCT_IN_1_PORT HP
+#define RTE_SCT_IN_1_PIN 26
+#define RTE_SCT_IN_1_MUX 9
+#define RTE_SCT_IN_1_PAD 0 //no pad
+#elif (RTE_SCT_IN_1_PORT_ID == 1)
+#define RTE_SCT_IN_1_PORT HP
+#define RTE_SCT_IN_1_PIN 65
+#define RTE_SCT_IN_1_MUX 7
+#define RTE_SCT_IN_1_PAD 23
+#else
+#error "Invalid RTE_SCT_IN_1_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_SCT_IN_1_PORT HP
+#if (SCT_IN1_LOC == 3)
+#define RTE_SCT_IN_1_PIN SCT_IN1_PIN
+#define RTE_SCT_IN_1_MUX 9
+#define RTE_SCT_IN_1_PAD 0 //no pad
+#endif
+#if (SCT_IN1_LOC == 4)
+#define RTE_SCT_IN_1_PIN (SCT_IN1_PIN + GPIO_MAX_PIN)
+#define RTE_SCT_IN_1_MUX 7
+#define RTE_SCT_IN_1_PAD 23
+#endif
+#if (SCT_IN1_LOC == 5)
+#define RTE_SCT_IN_1_PIN (SCT_IN1_PIN + GPIO_MAX_PIN)
+#define RTE_SCT_IN_1_MUX 9
+#define RTE_SCT_IN_1_PAD 27
+#endif
+//Pintool data
+#endif
+
+//SCT_IN_2 <0=>GPIO_27 <1=>GPIO_66 <2=>GPIO_70
+#ifndef SCT_IN2_LOC
+#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
+#define RTE_SCT_IN_2_PORT_ID 0
+#else
+#define RTE_SCT_IN_2_PORT_ID 1
+#endif
+
+#if (RTE_SCT_IN_2_PORT_ID == 0)
+#define RTE_SCT_IN_2_PORT HP
+#define RTE_SCT_IN_2_PIN 27
+#define RTE_SCT_IN_2_MUX 9
+#define RTE_SCT_IN_2_PAD 0 //no pad
+#elif (RTE_SCT_IN_2_PORT_ID == 1)
+#define RTE_SCT_IN_2_PORT HP
+#define RTE_SCT_IN_2_PIN 66
+#define RTE_SCT_IN_2_MUX 7
+#define RTE_SCT_IN_2_PAD 24
+#elif (RTE_SCT_IN_2_PORT_ID == 2)
+#define RTE_SCT_IN_2_PORT HP
+#define RTE_SCT_IN_2_PIN 70
+#define RTE_SCT_IN_2_MUX 9
+#define RTE_SCT_IN_2_PAD 28
+#else
+#error "Invalid RTE_SCT_IN_0_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_SCT_IN_2_PORT HP
+#if (SCT_IN2_LOC == 6)
+#define RTE_SCT_IN_2_PIN SCT_IN2_PIN
+#define RTE_SCT_IN_2_MUX 9
+#define RTE_SCT_IN_2_PAD 0 //no pad
+#endif
+#if (SCT_IN2_LOC == 7)
+#define RTE_SCT_IN_2_PIN (SCT_IN2_PIN + GPIO_MAX_PIN)
+#define RTE_SCT_IN_2_MUX 9
+#define RTE_SCT_IN_2_PAD 28
+#endif
+//Pintool data
+#endif
+
+//SCT_IN_3 <0=>GPIO_28 <1=>GPIO_67 <2=>GPIO_71
+#ifndef SCT_IN3_LOC
+#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
+#define RTE_SCT_IN_3_PORT_ID 0
+#else
+#define RTE_SCT_IN_3_PORT_ID 1
+#endif
+
+#if (RTE_SCT_IN_3_PORT_ID == 0)
+#define RTE_SCT_IN_3_PORT HP
+#define RTE_SCT_IN_3_PIN 28
+#define RTE_SCT_IN_3_MUX 9
+#define RTE_SCT_IN_3_PAD 0 //no pad
+#elif (RTE_SCT_IN_3_PORT_ID == 1)
+#define RTE_SCT_IN_3_PORT HP
+#define RTE_SCT_IN_3_PIN 67
+#define RTE_SCT_IN_3_MUX 7
+#define RTE_SCT_IN_3_PAD 25
+#elif (RTE_SCT_IN_3_PORT_ID == 2)
+#define RTE_SCT_IN_3_PORT HP
+#define RTE_SCT_IN_3_PIN 71
+#define RTE_SCT_IN_3_MUX 9
+#define RTE_SCT_IN_3_PAD 29
+#else
+#error "Invalid RTE_SCT_IN_0_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_SCT_IN_3_PORT HP
+#if (SCT_IN3_LOC == 8)
+#define RTE_SCT_IN_3_PIN SCT_IN3_PIN
+#define RTE_SCT_IN_3_MUX 9
+#define RTE_SCT_IN_3_PAD 0 //no pad
+#endif
+#if (SCT_IN3_LOC == 9)
+#define RTE_SCT_IN_3_PIN (SCT_IN3_PIN + GPIO_MAX_PIN)
+#define RTE_SCT_IN_3_MUX 9
+#define RTE_SCT_IN_3_PAD 29
+#endif
+//Pintool data
+#endif
+
+// SCT_OUT_0 <0=>GPIO_29 <1=>GPIO_68
+#ifndef SCT_OUT0_LOC
+#define RTE_SCT_OUT_0_PORT_ID 0
+#if (RTE_SCT_OUT_0_PORT_ID == 0)
+#define RTE_SCT_OUT_0_PORT HP
+#define RTE_SCT_OUT_0_PIN 29
+#define RTE_SCT_OUT_0_MUX 9
+#define RTE_SCT_OUT_0_PAD 0 //no pad
+#else
+#error "Invalid RTE_SCT_OUT_0_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_SCT_OUT_0_PORT HP
+#if (SCT_OUT0_LOC == 10)
+#define RTE_SCT_OUT_0_PIN SCT_OUT0_PIN
+#define RTE_SCT_OUT_0_MUX 9
+#define RTE_SCT_OUT_0_PAD 0 //no pad
+#elif (SCT_OUT0_LOC == 11)
+#define RTE_SCT_OUT_0_PIN (SCT_OUT0_PIN + GPIO_MAX_PIN)
+#define RTE_SCT_OUT_0_MUX 7
+#define RTE_SCT_OUT_0_PAD 26
+#endif
+//Pintool data
+#endif
+
+// SCT_OUT_1 <0=>GPIO_30 <1=>GPIO_69
+#ifndef SCT_OUT1_LOC
+#define RTE_SCT_OUT_1_PORT_ID 0
+#if (RTE_SCT_OUT_1_PORT_ID == 0)
+#define RTE_SCT_OUT_1_PORT HP
+#define RTE_SCT_OUT_1_PIN 30
+#define RTE_SCT_OUT_1_MUX 9
+#define RTE_SCT_OUT_1_PAD 0 //no pad
+#else
+#error "Invalid RTE_SCT_OUT_1_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_SCT_OUT_1_PORT HP
+#if (SCT_OUT1_LOC == 12)
+#define RTE_SCT_OUT_1_PIN SCT_OUT1_PIN
+#define RTE_SCT_OUT_1_MUX 9
+#define RTE_SCT_OUT_1_PAD 0 //no pad
+#elif (SCT_OUT1_LOC == 13)
+#define RTE_SCT_OUT_1_PIN (SCT_OUT1_PIN + GPIO_MAX_PIN)
+#define RTE_SCT_OUT_1_MUX 7
+#define RTE_SCT_OUT_1_PAD 27
+#endif
+//Pintool data
+#endif
+
+//Pintool data
+#define RTE_SCT_OUT_2_PORT HP
+#define RTE_SCT_OUT_2_PIN SCT_OUT2_PIN
+#define RTE_SCT_OUT_2_MUX 7
+#define RTE_SCT_OUT_2_PAD 28
+//Pintool data
+
+//Pintool data
+#define RTE_SCT_OUT_3_PORT HP
+#define RTE_SCT_OUT_3_PIN SCT_OUT3_PIN
+#define RTE_SCT_OUT_3_MUX 7
+#define RTE_SCT_OUT_3_PAD 29
+//Pintool data
+
+//Pintool data
+#define RTE_SCT_OUT_4_PORT HP
+#define RTE_SCT_OUT_4_PIN SCT_OUT4_PIN
+#define RTE_SCT_OUT_4_MUX 7
+#define RTE_SCT_OUT_4_PAD 30
+//Pintool data
+
+//Pintool data
+#define RTE_SCT_OUT_5_PORT HP
+#define RTE_SCT_OUT_5_PIN SCT_OUT5_PIN
+#define RTE_SCT_OUT_5_MUX 7
+#define RTE_SCT_OUT_5_PAD 31
+//Pintool data
+
+//Pintool data
+#define RTE_SCT_OUT_6_PORT HP
+#define RTE_SCT_OUT_6_PIN SCT_OUT6_PIN
+#define RTE_SCT_OUT_6_MUX 7
+#define RTE_SCT_OUT_6_PAD 32
+//Pintool data
+
+//Pintool data
+#define RTE_SCT_OUT_7_PORT HP
+#define RTE_SCT_OUT_7_PIN SCT_OUT7_PIN
+#define RTE_SCT_OUT_7_MUX 7
+#define RTE_SCT_OUT_7_PAD 33
+//Pintool data
+
+// SIO //
+//<> Serial Input Output
+//SIO_0 <0=>GPIO_6 <1=>GPIO_25 <2=>GPIO_64 <3=>GPIO_72
+#ifndef SIO_0_LOC
+#define RTE_SIO_0_PORT_ID 0
+
+#if (RTE_SIO_0_PORT_ID == 0)
+#define RTE_SIO_0_PORT HP
+#define RTE_SIO_0_PIN 6
+#define RTE_SIO_0_MUX 1
+#define RTE_SIO_0_PAD 1
+#elif (RTE_SIO_0_PORT_ID == 1)
+#define RTE_SIO_0_PORT HP
+#define RTE_SIO_0_PIN 25
+#define RTE_SIO_0_MUX 1
+#define RTE_SIO_0_PAD 0 //no pad
+#elif (RTE_SIO_0_PORT_ID == 2)
+#define RTE_SIO_0_PORT HP
+#define RTE_SIO_0_PIN 72
+#define RTE_SIO_0_MUX 1
+#define RTE_SIO_0_PAD 30
+#else
+#error "Invalid RTE_SIO_0_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_SIO_0_PORT SIO_SIO0_PORT
+#define RTE_SIO_0_MUX 1
+#if (SIO_0_LOC == 0)
+#define RTE_SIO_0_PIN SIO_SIO0_PIN
+#define RTE_SIO_0_PAD 1
+#endif
+#if (SIO_0_LOC == 1)
+#define RTE_SIO_0_PIN SIO_SIO0_PIN
+#define RTE_SIO_0_PAD 0
+#endif
+#if (SIO_0_LOC == 2)
+#define RTE_SIO_0_PIN (SIO_SIO0_PIN + GPIO_MAX_PIN)
+#define RTE_SIO_0_PAD 22
+#endif
+#if (SIO_0_LOC == 3)
+#define RTE_SIO_0_PIN (SIO_SIO0_PIN + GPIO_MAX_PIN)
+#define RTE_SIO_0_PAD 30
+#endif
+//Pintool data
+#endif
+
+//SIO_1 <0=>GPIO_7 <1=>GPIO_26 <2=>GPIO_65 <3=>GPIO_73
+#ifndef SIO_1_LOC
+#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
+#define RTE_SIO_1_PORT_ID 1
+#else
+#define RTE_SIO_1_PORT_ID 0
+#endif
+
+#if (RTE_SIO_1_PORT_ID == 0)
+#define RTE_SIO_1_PORT HP
+#define RTE_SIO_1_PIN 7
+#define RTE_SIO_1_MUX 1
+#define RTE_SIO_1_PAD 2
+#elif (RTE_SIO_1_PORT_ID == 1)
+#define RTE_SIO_1_PORT HP
+#define RTE_SIO_1_PIN 26
+#define RTE_SIO_1_MUX 1
+#define RTE_SIO_1_PAD 0 // no pad
+#elif (RTE_SIO_1_PORT_ID == 2)
+#define RTE_SIO_1_PORT HP
+#define RTE_SIO_1_PIN 65
+#define RTE_SIO_1_MUX 1
+#define RTE_SIO_1_PAD 23
+#elif (RTE_SIO_1_PORT_ID == 3)
+#define RTE_SIO_1_PORT HP
+#define RTE_SIO_1_PIN 73
+#define RTE_SIO_1_MUX 1
+#define RTE_SIO_1_PAD 31
+#else
+#error "Invalid RTE_SIO_1_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_SIO_1_PORT SIO_SIO1_PORT
+#define RTE_SIO_1_MUX 1
+#if (SIO_1_LOC == 4)
+#define RTE_SIO_1_PIN SIO_SIO1_PIN
+#define RTE_SIO_1_PAD 2
+#endif
+#if (SIO_1_LOC == 5)
+#define RTE_SIO_1_PIN SIO_SIO1_PIN
+#define RTE_SIO_1_PAD 0
+#endif
+#if (SIO_1_LOC == 6)
+#define RTE_SIO_1_PIN (SIO_SIO1_PIN + GPIO_MAX_PIN)
+#define RTE_SIO_1_PAD 23
+#endif
+#if (SIO_1_LOC == 7)
+#define RTE_SIO_1_PIN (SIO_SIO1_PIN + GPIO_MAX_PIN)
+#define RTE_SIO_1_PAD 31
+#endif
+//Pintool data
+#endif
+
+// SIO_2 <0=>GPIO_8 <1=>GPIO_27 <2=>GPIO_66 <3=>GPIO_74
+#ifndef SIO_2_LOC
+#define RTE_SIO_2_PORT_ID 1
+
+#if (RTE_SIO_2_PORT_ID == 0)
+#define RTE_SIO_2_PORT HP
+#define RTE_SIO_2_PIN 8
+#define RTE_SIO_2_MUX 1
+#define RTE_SIO_2_PAD 3
+#elif (RTE_SIO_2_PORT_ID == 1)
+#define RTE_SIO_2_PORT HP
+#define RTE_SIO_2_PIN 27
+#define RTE_SIO_2_MUX 1
+#define RTE_SIO_2_PAD 0 //no pad
+#elif (RTE_SIO_2_PORT_ID == 2)
+#define RTE_SIO_2_PORT HP
+#define RTE_SIO_2_PIN 66
+#define RTE_SIO_2_MUX 1
+#define RTE_SIO_2_PAD 24
+#elif (RTE_SIO_2_PORT_ID == 3)
+#define RTE_SIO_2_PORT HP
+#define RTE_SIO_2_PIN 74
+#define RTE_SIO_2_MUX 1
+#define RTE_SIO_2_PAD 32
+#else
+#error "Invalid RTE_SIO_2_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_SIO_2_PORT SIO_SIO2_PORT
+#define RTE_SIO_2_MUX 1
+#if (SIO_2_LOC == 8)
+#define RTE_SIO_2_PIN SIO_SIO2_PIN
+#define RTE_SIO_2_PAD 3
+#endif
+#if (SIO_2_LOC == 9)
+#define RTE_SIO_2_PIN SIO_SIO2_PIN
+#define RTE_SIO_2_PAD 0
+#endif
+#if (SIO_2_LOC == 10)
+#define RTE_SIO_2_PIN (SIO_SIO2_PIN + GPIO_MAX_PIN)
+#define RTE_SIO_2_PAD 32
+#endif
+//Pintool data
+#endif
+
+//SIO_3 <0=>GPIO_9 <1=>GPIO_28 <2=>GPIO_67 <3=>GPIO_75
+#ifndef SIO_3_LOC
+#define RTE_SIO_3_PORT_ID 1
+
+#if (RTE_SIO_3_PORT_ID == 0)
+#define RTE_SIO_3_PORT HP
+#define RTE_SIO_3_PIN 9
+#define RTE_SIO_3_MUX 1
+#define RTE_SIO_3_PAD 4
+#elif (RTE_SIO_3_PORT_ID == 1)
+#define RTE_SIO_3_PORT HP
+#define RTE_SIO_3_PIN 28
+#define RTE_SIO_3_MUX 1
+#define RTE_SIO_3_PAD 0 //no pad
+#elif (RTE_SIO_3_PORT_ID == 2)
+#define RTE_SIO_3_PORT HP
+#define RTE_SIO_3_PIN 67
+#define RTE_SIO_3_MUX 1
+#define RTE_SIO_3_PAD 25
+#elif (RTE_SIO_3_PORT_ID == 3)
+#define RTE_SIO_3_PORT HP
+#define RTE_SIO_3_PIN 75
+#define RTE_SIO_3_MUX 1
+#define RTE_SIO_3_PAD 33
+#else
+#error "Invalid RTE_SIO_3_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_SIO_3_PORT SIO_SIO3_PORT
+#define RTE_SIO_3_MUX 1
+#if (SIO_3_LOC == 11)
+#define RTE_SIO_3_PIN SIO_SIO3_PIN
+#define RTE_SIO_3_PAD 4
+#endif
+#if (SIO_3_LOC == 12)
+#define RTE_SIO_3_PIN SIO_SIO3_PIN
+#define RTE_SIO_3_PAD 0
+#endif
+#if (SIO_3_LOC == 13)
+#define RTE_SIO_3_PIN (SIO_SIO3_PIN + GPIO_MAX_PIN)
+#define RTE_SIO_3_PAD 33
+#endif
+//Pintool data
+#endif
+
+//SIO_4 <0=>GPIO_10 <1=>GPIO_29 <2=>GPIO_68
+#ifndef SIO_4_LOC
+#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
+#define RTE_SIO_4_PORT_ID 1
+#else
+#define RTE_SIO_4_PORT_ID 0
+#endif
+#if (RTE_SIO_4_PORT_ID == 0)
+#define RTE_SIO_4_PORT HP
+#define RTE_SIO_4_PIN 10
+#define RTE_SIO_4_MUX 1
+#define RTE_SIO_4_PAD 5
+#elif (RTE_SIO_4_PORT_ID == 1)
+#define RTE_SIO_4_PORT HP
+#define RTE_SIO_4_PIN 29
+#define RTE_SIO_4_MUX 1
+#define RTE_SIO_4_PAD 0 //NO PAD
+#else
+#error "Invalid RTE_SIO_3_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_SIO_4_PORT SIO_SIO4_PORT
+#define RTE_SIO_4_MUX 1
+#if (SIO_4_LOC == 14)
+#define RTE_SIO_4_PAD 5
+#define RTE_SIO_4_PIN SIO_SIO4_PIN
+#endif
+#if (SIO_4_LOC == 15)
+#define RTE_SIO_4_PAD 0
+#define RTE_SIO_4_PIN SIO_SIO4_PIN
+#endif
+#if (SIO_4_LOC == 16)
+#define RTE_SIO_4_PAD 26
+#define RTE_SIO_4_PIN (SIO_SIO4_PIN + GPIO_MAX_PIN)
+#endif
+//Pintool data
+#endif
+
+// SIO_5 <0=>GPIO_11 <1=>GPIO_30 <2=>GPIO_69
+#ifndef SIO_5_LOC
+#define RTE_SIO_5_PORT_ID 0
+#if (RTE_SIO_5_PORT_ID == 0)
+#define RTE_SIO_5_PORT HP
+#define RTE_SIO_5_PIN 11
+#define RTE_SIO_5_MUX 1
+#define RTE_SIO_5_PAD 6
+#elif (RTE_SIO_5_PORT_ID == 1)
+#define RTE_SIO_5_PORT HP
+#define RTE_SIO_5_PIN 30
+#define RTE_SIO_5_MUX 1
+#define RTE_SIO_5_PAD 0 //no pad
+#else
+#error "Invalid RTE_SIO_5_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_SIO_5_PORT SIO_SIO5_PORT
+#define RTE_SIO_5_MUX 1
+#if (SIO_5_LOC == 17)
+#define RTE_SIO_5_PAD 6
+#define RTE_SIO_5_PIN SIO_SIO5_PIN
+#endif
+#if (SIO_5_LOC == 18)
+#define RTE_SIO_5_PAD 0
+#define RTE_SIO_5_PIN SIO_SIO5_PIN
+#endif
+#if (SIO_5_LOC == 19)
+#define RTE_SIO_5_PAD 0
+#define RTE_SIO_5_PIN (SIO_SIO5_PIN + GPIO_MAX_PIN)
+#endif
+//Pintool data
+#endif
+
+// SIO_6 GPIO_70
+#ifndef SIO_6_LOC
+#define RTE_SIO_6_PORT HP
+#define RTE_SIO_6_PIN 70
+#else
+#define RTE_SIO_6_PORT SIO_SIO6_PORT
+#define RTE_SIO_6_PIN (SIO_SIO6_PIN + GPIO_MAX_PIN)
+#endif
+#define RTE_SIO_6_MUX 1
+#define RTE_SIO_6_PAD 28
+
+// SIO_7 <0=>GPIO_15 <1=>GPIO_71
+#ifndef SIO_7_LOC
+#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
+#define RTE_SIO_7_PORT_ID 1
+#else
+#define RTE_SIO_7_PORT_ID 0
+#endif
+
+#if (RTE_SIO_7_PORT_ID == 0)
+#define RTE_SIO_7_PORT HP
+#define RTE_SIO_7_PIN 15
+#define RTE_SIO_7_MUX 1
+#define RTE_SIO_7_PAD 8
+#elif (RTE_SIO_7_PORT_ID == 1)
+#define RTE_SIO_7_PORT HP
+#define RTE_SIO_7_PIN 71
+#define RTE_SIO_7_MUX 1
+#define RTE_SIO_7_PAD 29
+#else
+#error "Invalid RTE_SIO_7_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_SIO_7_PORT SIO_SIO7_PORT
+#define RTE_SIO_7_MUX 1
+#if (SIO_7_LOC == 21)
+#define RTE_SIO_7_PIN SIO_SIO7_PIN
+#define RTE_SIO_7_PAD 8
+#endif
+#if (SIO_7_LOC == 22)
+#define RTE_SIO_7_PIN (SIO_SIO7_PIN + GPIO_MAX_PIN)
+#define RTE_SIO_7_PAD 29
+#endif
+//Pintool data
+#endif
+
+//<> Pulse Width Modulation
+//PWM_1H <0=>GPIO_7 <1=>GPIO_64 <2=>GPIO_65
+#ifndef PWM_CH0_0H_LOC
+#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
+#define RTE_PWM_1H_PORT_ID 0
+#else
+#define RTE_PWM_1H_PORT_ID 0
+#endif
+
+#if (RTE_PWM_1H_PORT_ID == 0)
+#define RTE_PWM_1H_PORT HP
+#define RTE_PWM_1H_PIN 7
+#define RTE_PWM_1H_MUX 10
+#define RTE_PWM_1H_PAD 2
+#elif (RTE_PWM_1H_PORT_ID == 1)
+#define RTE_PWM_1H_PORT HP
+#define RTE_PWM_1H_PIN 65
+#define RTE_PWM_1H_MUX 8
+#define RTE_PWM_1H_PAD 23
+#else
+#error "Invalid RTE_PWM_1H_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_PWM_1H_PORT HP
+#if (PWM_CH0_0H_LOC == 0)
+#define RTE_PWM_1H_PIN PWM_CH0_0H_PIN
+#define RTE_PWM_1H_MUX 10
+#define RTE_PWM_1H_PAD 2
+#endif
+#if (PWM_CH0_0H_LOC == 1)
+#define RTE_PWM_1H_PIN (PWM_CH0_0H_PIN + GPIO_MAX_PIN)
+#define RTE_PWM_1H_MUX 8
+#define RTE_PWM_1H_PAD 23
+#endif
+//Pintool data
+#endif
+
+// PWM_1L <0=>GPIO_6 <1=>GPIO_64 <2=>GPIO_64
+#ifndef PWM_CH0_0L_LOC
+#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
+#define RTE_PWM_1L_PORT_ID 0
+#else
+#define RTE_PWM_1L_PORT_ID 1
+#endif
+
+#if (RTE_PWM_1L_PORT_ID == 0)
+#define RTE_PWM_1L_PORT HP
+#define RTE_PWM_1L_PIN 6
+#define RTE_PWM_1L_MUX 10
+#define RTE_PWM_1L_PAD 1
+#else
+#error "Invalid RTE_PWM_1L_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_PWM_1L_PORT HP
+#if (PWM_CH0_0L_LOC == 2)
+#define RTE_PWM_1L_PIN PWM_CH0_0L_PIN
+#define RTE_PWM_1L_MUX 10
+#define RTE_PWM_1L_PAD 1
+#elif (PWM_CH0_0L_LOC == 3)
+#define RTE_PWM_1L_PIN (PWM_CH0_0L_PIN + GPIO_MAX_PIN)
+#define RTE_PWM_1L_MUX 8
+#define RTE_PWM_1L_PAD 22
+#endif
+//Pintool data
+#endif
+
+//PWM_2H <0=>GPIO_9 <1=>GPIO_67 <2=>GPIO_69
+#ifndef PWM_CH1_1H_LOC
+#define RTE_PWM_2H_PORT_ID 0
+#if ((RTE_PWM_2H_PORT_ID == 2))
+#error "Invalid RTE_PWM_2H_PIN pin Configuration!"
+#endif
+
+#if (RTE_PWM_2H_PORT_ID == 0)
+#define RTE_PWM_2H_PORT HP
+#define RTE_PWM_2H_PIN 9
+#define RTE_PWM_2H_MUX 10
+#define RTE_PWM_2H_PAD 4
+#elif (RTE_PWM_2H_PORT_ID == 1)
+#define RTE_PWM_2H_PORT HP
+#define RTE_PWM_2H_PIN 67
+#define RTE_PWM_2H_MUX 8
+#define RTE_PWM_2H_PAD 25
+#else
+#error "Invalid RTE_PWM_2H_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_PWM_2H_PORT HP
+#if (PWM_CH1_1H_LOC == 4)
+#define RTE_PWM_2H_PIN PWM_CH1_1H_PIN
+#define RTE_PWM_2H_MUX 10
+#define RTE_PWM_2H_PAD 4
+#endif
+#if (PWM_CH1_1H_LOC == 5)
+#define RTE_PWM_2H_PIN (PWM_CH1_1H_PIN + GPIO_MAX_PIN)
+#define RTE_PWM_2H_MUX 12
+#define RTE_PWM_2H_PAD 27
+#endif
+//Pintool data
+#endif
+
+// PWM_2L <0=>GPIO_8 <1=>GPIO_66 <2=>GPIO_68
+#ifndef PWM_CH1_1L_LOC
+#define RTE_PWM_2L_PORT_ID 0
+#if ((RTE_PWM_2L_PORT_ID == 2))
+#error "Invalid RTE_PWM_2L_PIN pin Configuration!"
+#endif
+
+#if (RTE_PWM_2L_PORT_ID == 0)
+#define RTE_PWM_2L_PORT HP
+#define RTE_PWM_2L_PIN 8
+#define RTE_PWM_2L_MUX 10
+#define RTE_PWM_2L_PAD 3
+#elif (RTE_PWM_2L_PORT_ID == 1)
+#define RTE_PWM_2L_PORT HP
+#define RTE_PWM_2L_PIN 66
+#define RTE_PWM_2L_MUX 8
+#define RTE_PWM_2L_PAD 24
+#else
+#error "Invalid RTE_PWM_2L_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_PWM_2L_PORT HP
+#if (PWM_CH1_1L_LOC == 6)
+#define RTE_PWM_2L_PIN PWM_CH1_1L_PIN
+#define RTE_PWM_2L_MUX 10
+#define RTE_PWM_2L_PAD 3
+#endif
+#if (PWM_CH1_1L_LOC == 7)
+#define RTE_PWM_2L_PIN (PWM_CH1_1L_PIN + GPIO_MAX_PIN)
+#define RTE_PWM_2L_MUX 8
+#define RTE_PWM_2L_PAD 24
+#endif
+#if (PWM_CH1_1L_LOC == 8)
+#define RTE_PWM_2L_PIN (PWM_CH1_1L_PIN + GPIO_MAX_PIN)
+#define RTE_PWM_2L_MUX 12
+#define RTE_PWM_2L_PAD 26
+#endif
+//Pintool data
+#endif
+
+// PWM_3H <0=>GPIO_11 <1=>GPIO_69
+#ifndef PWM_CH2_2H_LOC
+#define RTE_PWM_3H_PORT_ID 0
+#if (RTE_PWM_3H_PORT_ID == 0)
+#define RTE_PWM_3H_PORT HP
+#define RTE_PWM_3H_PIN 11
+#define RTE_PWM_3H_MUX 10
+#define RTE_PWM_3H_PAD 6
+#else
+#error "Invalid RTE_PWM_3H_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_PWM_3H_PORT HP
+#if (PWM_CH2_2H_LOC == 9)
+#define RTE_PWM_3H_PIN PWM_CH2_2H_PIN
+#define RTE_PWM_3H_MUX 10
+#define RTE_PWM_3H_PAD 6
+#elif (PWM_CH2_2H_LOC == 10)
+#define RTE_PWM_3H_PIN (PWM_CH2_2H_PIN + GPIO_MAX_PIN)
+#define RTE_PWM_3H_MUX 8
+#define RTE_PWM_3H_PAD 27
+#endif
+//Pintool data
+#endif
+
+// PWM_3L <0=>GPIO_10 <1=>GPIO_68
+#ifndef PWM_CH2_2L_LOC
+#define RTE_PWM_3L_PORT_ID 0
+
+#if (RTE_PWM_3L_PORT_ID == 0)
+#define RTE_PWM_3L_PORT HP
+#define RTE_PWM_3L_PIN 10
+#define RTE_PWM_3L_MUX 10
+#define RTE_PWM_3L_PAD 5
+#else
+#error "Invalid RTE_PWM_3L_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_PWM_3L_PORT HP
+#if (PWM_CH2_2L_LOC == 11)
+#define RTE_PWM_3L_PIN PWM_CH2_2L_PIN
+#define RTE_PWM_3L_MUX 10
+#define RTE_PWM_3L_PAD 5
+#elif (PWM_CH2_2L_LOC == 12)
+#define RTE_PWM_3L_PIN (PWM_CH2_2L_PIN + GPIO_MAX_PIN)
+#define RTE_PWM_3L_MUX 8
+#define RTE_PWM_3L_PAD 26
+#endif
+//Pintool data
+#endif
+
+// PWM_4H <0=>GPIO_15 <1=>GPIO_71
+#ifndef PWM_CH3_3H_LOC
+#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
+#define RTE_PWM_4H_PORT_ID 1
+#else
+#define RTE_PWM_4H_PORT_ID 0
+#endif
+
+#if (RTE_PWM_4H_PORT_ID == 0)
+#define RTE_PWM_4H_PORT HP
+#define RTE_PWM_4H_PIN 15
+#define RTE_PWM_4H_MUX 10
+#define RTE_PWM_4H_PAD 8
+#elif (RTE_PWM_4H_PORT_ID == 1)
+#define RTE_PWM_4H_PORT HP
+#define RTE_PWM_4H_PIN 71
+#define RTE_PWM_4H_MUX 8
+#define RTE_PWM_4H_PAD 29
+#else
+#error "Invalid RTE_PWM_4H_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_PWM_4H_PORT HP
+#if (PWM_CH3_3H_LOC == 38)
+#define RTE_PWM_4H_PIN PWM_CH3_3H_PIN
+#define RTE_PWM_4H_MUX 10
+#define RTE_PWM_4H_PAD 8
+#elif (PWM_CH3_3H_LOC == 13)
+#define RTE_PWM_4H_PIN (PWM_CH3_3H_PIN + GPIO_MAX_PIN)
+#define RTE_PWM_4H_MUX 8
+#define RTE_PWM_4H_PAD 29
+#endif
+//Pintool data
+#endif
+
+// PWM_4H <0=>GPIO_12 <1=>GPIO_70
+#ifndef PWM_CH3_3L_LOC
+#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
+#define RTE_PWM_4L_PORT_ID 1
+#else
+#define RTE_PWM_4L_PORT_ID 0
+#endif
+
+#if (RTE_PWM_4L_PORT_ID == 0)
+#define RTE_PWM_4L_PORT HP
+#define RTE_PWM_4L_PIN 12
+#define RTE_PWM_4L_MUX 10
+#define RTE_PWM_4L_PAD 7
+#elif (RTE_PWM_4L_PORT_ID == 1)
+#define RTE_PWM_4L_PORT HP
+#define RTE_PWM_4L_PIN 70
+#define RTE_PWM_4L_MUX 8
+#define RTE_PWM_4L_PAD 28
+#else
+#error "Invalid RTE_PWM_4L_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_PWM_4L_PORT HP
+#if (PWM_CH3_3L_LOC == 14)
+#define RTE_PWM_4L_PIN PWM_CH3_3L_PIN
+#define RTE_PWM_4L_MUX 10
+#define RTE_PWM_4L_PAD 7
+#endif
+#if (PWM_CH3_3L_LOC == 15)
+#define RTE_PWM_4L_PIN (PWM_CH3_3L_PIN + GPIO_MAX_PIN)
+#define RTE_PWM_4L_MUX 8
+#define RTE_PWM_4L_PAD 28
+#endif
+//Pintool data
+#endif
+
+// PWM_FAULTA <0=>GPIO_25 <1=>GPIO_68 <1=>GPIO_73
+#ifndef PWM_FAULTA_LOC
+#define RTE_PWM_FAULTA_PORT_ID 0
+
+#if (RTE_PWM_FAULTA_PORT_ID == 0)
+#define RTE_PWM_FAULTA_PORT HP
+#define RTE_PWM_FAULTA_PIN 25
+#define RTE_PWM_FAULTA_MUX 10
+#define RTE_PWM_FAULTA_PAD 0 //no pad
+#elif (RTE_PWM_FAULTA_PORT_ID == 2)
+#define RTE_PWM_FAULTA_PORT HP
+#define RTE_PWM_FAULTA_PIN 73
+#define RTE_PWM_FAULTA_MUX 8
+#define RTE_PWM_FAULTA_PAD 31
+#else
+#error "Invalid RTE_PWM_FAULTA_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_PWM_FAULTA_PORT HP
+#if (PWM_FAULTA_LOC == 16)
+#define RTE_PWM_FAULTA_PIN PWM_FAULTA_PIN
+#define RTE_PWM_FAULTA_MUX 10
+#define RTE_PWM_FAULTA_PAD 0 //no pad
+#endif
+#if (PWM_FAULTA_LOC == 17)
+#define RTE_PWM_FAULTA_PIN (PWM_FAULTA_PIN + GPIO_MAX_PIN)
+#define RTE_PWM_FAULTA_MUX 10
+#define RTE_PWM_FAULTA_PAD 26
+#endif
+#if (PWM_FAULTA_LOC == 18)
+#define RTE_PWM_FAULTA_PIN (PWM_FAULTA_PIN + GPIO_MAX_PIN)
+#define RTE_PWM_FAULTA_MUX 8
+#define RTE_PWM_FAULTA_PAD 31
+#endif
+//Pintool data
+#endif
+
+// PWM_FAULTB <0=>GPIO_26 <1=>GPIO_69 <1=>GPIO_74
+#ifndef PWM_FAULTB_LOC
+#define RTE_PWM_FAULTB_PORT_ID 0
+
+#if (RTE_PWM_FAULTB_PORT_ID == 0)
+#define RTE_PWM_FAULTB_PORT HP
+#define RTE_PWM_FAULTB_PIN 26
+#define RTE_PWM_FAULTB_MUX 10
+#define RTE_PWM_FAULTB_PAD 0 //no pad
+#elif (RTE_PWM_FAULTB_PORT_ID == 2)
+#define RTE_PWM_FAULTB_PORT HP
+#define RTE_PWM_FAULTB_PIN 74
+#define RTE_PWM_FAULTB_MUX 8
+#define RTE_PWM_FAULTB_PAD 32
+#else
+#error "Invalid RTE_PWM_FAULTB_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_PWM_FAULTB_PORT HP
+#if (PWM_FAULTB_LOC == 19)
+#define RTE_PWM_FAULTB_PIN PWM_FAULTB_PIN
+#define RTE_PWM_FAULTB_MUX 10
+#define RTE_PWM_FAULTB_PAD 0 //no pad
+#endif
+#if (PWM_FAULTB_LOC == 20)
+#define RTE_PWM_FAULTB_PIN (PWM_FAULTB_PIN + GPIO_MAX_PIN)
+#define RTE_PWM_FAULTB_MUX 10
+#define RTE_PWM_FAULTB_PAD 27
+#endif
+#if (PWM_FAULTB_LOC == 21)
+#define RTE_PWM_FAULTB_PIN (PWM_FAULTB_PIN + GPIO_MAX_PIN)
+#define RTE_PWM_FAULTB_MUX 8
+#define RTE_PWM_FAULTB_PAD 32
+#endif
+//Pintool data
+#endif
+
+//PWM_SLP_EVENT_TRIG GPIO_72
+#ifndef PWM_EVTTRIG_LOC
+#define RTE_PWM_SLP_EVENT_TRIG_PORT HP
+#define RTE_PWM_SLP_EVENT_TRIG_PIN 72
+#else
+//Pintool data
+#define RTE_PWM_SLP_EVENT_TRIG_PORT HP
+#define RTE_PWM_SLP_EVENT_TRIG_PIN (PWM_SLEEP_EVT_TRIG_PIN + GPIO_MAX_PIN)
+//Pintool data
+#endif
+#define RTE_PWM_SLP_EVENT_TRIG_MUX 8
+#define RTE_PWM_SLP_EVENT_TRIG_PAD 30
+
+//PWM_TMR_EXT_TRIG_1 <0=>GPIO_27 <1=>GPIO_51 <2=>GPIO_70 <3=>GPIO_75
+#ifndef PWM_EXTTRIG1_LOC
+#define RTE_PWM_TMR_EXT_TRIG_1_PORT_ID 0
+
+#if (RTE_PWM_TMR_EXT_TRIG_1_PORT_ID == 0)
+#define RTE_PWM_TMR_EXT_TRIG_1_PORT HP
+#define RTE_PWM_TMR_EXT_TRIG_1_PIN 27
+#define RTE_PWM_TMR_EXT_TRIG_1_MUX 10
+#define RTE_PWM_TMR_EXT_TRIG_1_PAD 0 //no pad
+#elif (RTE_PWM_TMR_EXT_TRIG_1_PORT_ID == 1)
+#define RTE_PWM_TMR_EXT_TRIG_1_PORT HP
+#define RTE_PWM_TMR_EXT_TRIG_1_PIN 51
+#define RTE_PWM_TMR_EXT_TRIG_1_MUX 8
+#define RTE_PWM_TMR_EXT_TRIG_1_PAD 15
+#elif (RTE_PWM_TMR_EXT_TRIG_1_PORT_ID == 2)
+#define RTE_PWM_TMR_EXT_TRIG_1_PORT HP
+#define RTE_PWM_TMR_EXT_TRIG_1_PIN 70
+#define RTE_PWM_TMR_EXT_TRIG_1_MUX 10
+#define RTE_PWM_TMR_EXT_TRIG_1_PAD 28
+#elif (RTE_PWM_TMR_EXT_TRIG_1_PORT_ID == 3)
+#define RTE_PWM_TMR_EXT_TRIG_1_PORT HP
+#define RTE_PWM_TMR_EXT_TRIG_1_PIN 75
+#define RTE_PWM_TMR_EXT_TRIG_1_MUX 8
+#define RTE_PWM_TMR_EXT_TRIG_1_PAD 33
+#else
+#error "Invalid RTE_PWM_TMR_EXT_TRIG_1_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_PWM_TMR_EXT_TRIG_1_PORT HP
+#if (PWM_EXTTRIG1_LOC == 22)
+#define RTE_PWM_TMR_EXT_TRIG_1_PIN PWM_TMR_EXT_TRIG_1_PIN
+#define RTE_PWM_TMR_EXT_TRIG_1_MUX 10
+#define RTE_PWM_TMR_EXT_TRIG_1_PAD 0 //no pad
+#endif
+#if (PWM_EXTTRIG1_LOC == 23)
+#define RTE_PWM_TMR_EXT_TRIG_1_PIN PWM_TMR_EXT_TRIG_1_PIN
+#define RTE_PWM_TMR_EXT_TRIG_1_MUX 8
+#define RTE_PWM_TMR_EXT_TRIG_1_PAD 15
+#endif
+#if (PWM_EXTTRIG1_LOC == 24)
+#define RTE_PWM_TMR_EXT_TRIG_1_PIN (PWM_TMR_EXT_TRIG_1_PIN + GPIO_MAX_PIN)
+#define RTE_PWM_TMR_EXT_TRIG_1_MUX 10
+#define RTE_PWM_TMR_EXT_TRIG_1_PAD 28
+#endif
+#if (PWM_EXTTRIG1_LOC == 25)
+#define RTE_PWM_TMR_EXT_TRIG_1_PIN (PWM_TMR_EXT_TRIG_1_PIN + GPIO_MAX_PIN)
+#define RTE_PWM_TMR_EXT_TRIG_1_MUX 8
+#define RTE_PWM_TMR_EXT_TRIG_1_PAD 33
+#endif
+//Pintool data
+#endif
+
+//PWM_TMR_EXT_TRIG_2 <0=>GPIO_28 <1=>GPIO_54 <2=>GPIO_71
+#ifndef PWM_EXTTRIG2_LOC
+#define RTE_PWM_TMR_EXT_TRIG_2_PORT_ID 0
+
+#if (RTE_PWM_TMR_EXT_TRIG_2_PORT_ID == 0)
+#define RTE_PWM_TMR_EXT_TRIG_2_PORT HP
+#define RTE_PWM_TMR_EXT_TRIG_2_PIN 28
+#define RTE_PWM_TMR_EXT_TRIG_2_MUX 10
+#define RTE_PWM_TMR_EXT_TRIG_2_PAD 0 //no pad
+#elif (RTE_PWM_TMR_EXT_TRIG_2_PORT_ID == 1)
+#define RTE_PWM_TMR_EXT_TRIG_2_PORT HP
+#define RTE_PWM_TMR_EXT_TRIG_2_PIN 54
+#define RTE_PWM_TMR_EXT_TRIG_2_MUX 8
+#define RTE_PWM_TMR_EXT_TRIG_2_PAD 18
+#elif (RTE_PWM_TMR_EXT_TRIG_2_PORT_ID == 2)
+#define RTE_PWM_TMR_EXT_TRIG_2_PORT HP
+#define RTE_PWM_TMR_EXT_TRIG_2_PIN 71
+#define RTE_PWM_TMR_EXT_TRIG_2_MUX 10
+#define RTE_PWM_TMR_EXT_TRIG_2_PAD 29
+#else
+#error "Invalid RTE_PWM_TMR_EXT_TRIG_2_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_PWM_TMR_EXT_TRIG_2_PORT HP
+#if (PWM_EXTTRIG2_LOC == 26)
+#define RTE_PWM_TMR_EXT_TRIG_2_PIN PWM_TMR_EXT_TRIG_2_PIN
+#define RTE_PWM_TMR_EXT_TRIG_2_MUX 10
+#define RTE_PWM_TMR_EXT_TRIG_2_PAD 0 //no pad
+#endif
+#if (PWM_EXTTRIG2_LOC == 27)
+#define RTE_PWM_TMR_EXT_TRIG_2_PIN PWM_TMR_EXT_TRIG_2_PIN
+#define RTE_PWM_TMR_EXT_TRIG_2_MUX 8
+#define RTE_PWM_TMR_EXT_TRIG_2_PAD 18
+#endif
+#if (PWM_EXTTRIG2_LOC == 28) //Combination not available in pin mux
+#define RTE_PWM_TMR_EXT_TRIG_2_PIN (PWM_TMR_EXT_TRIG_2_PIN + GPIO_MAX_PIN)
+#define RTE_PWM_TMR_EXT_TRIG_2_MUX 10
+#define RTE_PWM_TMR_EXT_TRIG_2_PAD 29
+#endif
+#if (PWM_EXTTRIG2_LOC == 29)
+#define RTE_PWM_TMR_EXT_TRIG_2_PIN (PWM_TMR_EXT_TRIG_2_PIN + GPIO_MAX_PIN)
+#define RTE_PWM_TMR_EXT_TRIG_2_MUX 10
+#define RTE_PWM_TMR_EXT_TRIG_2_PAD 29
+#endif
+//Pintool data
+#endif
+
+//PWM_TMR_EXT_TRIG_3
+//Pintool data
+#define RTE_PWM_TMR_EXT_TRIG_3_PORT HP
+#if (PWM_EXTTRIG3_LOC == 30)
+#define RTE_PWM_TMR_EXT_TRIG_3_PIN PWM_TMR_EXT_TRIG_3_PIN
+#define RTE_PWM_TMR_EXT_TRIG_3_MUX 10
+#define RTE_PWM_TMR_EXT_TRIG_3_PAD 0 //no pad
+#endif
+#if (PWM_EXTTRIG3_LOC == 31)
+#define RTE_PWM_TMR_EXT_TRIG_3_PIN PWM_TMR_EXT_TRIG_3_PIN
+#define RTE_PWM_TMR_EXT_TRIG_3_MUX 8
+#define RTE_PWM_TMR_EXT_TRIG_3_PAD 19
+#endif
+#if (PWM_EXTTRIG3_LOC == 32)
+#define RTE_PWM_TMR_EXT_TRIG_3_PIN (PWM_TMR_EXT_TRIG_3_PIN + GPIO_MAX_PIN)
+#define RTE_PWM_TMR_EXT_TRIG_3_MUX 10
+#define RTE_PWM_TMR_EXT_TRIG_3_PAD 30
+#endif
+//Pintool data
+
+//PWM_TMR_EXT_TRIG_4
+//Pintool data
+#define RTE_PWM_TMR_EXT_TRIG_4_PORT HP
+#if (PWM_EXTTRIG4_LOC == 33)
+#define RTE_PWM_TMR_EXT_TRIG_4_PIN PWM_TMR_EXT_TRIG_4_PIN
+#define RTE_PWM_TMR_EXT_TRIG_4_MUX 10
+#define RTE_PWM_TMR_EXT_TRIG_4_PAD 0 //no pad
+#endif
+#if (PWM_EXTTRIG4_LOC == 34)
+#define RTE_PWM_TMR_EXT_TRIG_4_PIN PWM_TMR_EXT_TRIG_4_PIN
+#define RTE_PWM_TMR_EXT_TRIG_4_MUX 8
+#define RTE_PWM_TMR_EXT_TRIG_4_PAD 14
+#endif
+#if (PWM_EXTTRIG4_LOC == 35)
+#define RTE_PWM_TMR_EXT_TRIG_4_PIN (PWM_TMR_EXT_TRIG_4_PIN + GPIO_MAX_PIN)
+#define RTE_PWM_TMR_EXT_TRIG_4_MUX 10
+#define RTE_PWM_TMR_EXT_TRIG_4_PAD 31
+#endif
+//Pintool data
+
+//<> QEI (Quadrature Encode Interface)
+
+//QEI_DIR <0=>GPIO_11 <1=>GPIO_28 <2=>GPIO_49 <3=>GPIO_34 <4=>GPIO_57 <5=>GPIO_71 <6=>GPIO_75
+#ifndef QEI_DIR_LOC
+#define RTE_QEI_DIR_PORT_ID 4
+
+#if (RTE_QEI_DIR_PORT_ID == 0)
+#define RTE_QEI_DIR_PORT HP
+#define RTE_QEI_DIR_PIN 11
+#define RTE_QEI_DIR_MUX 5
+#define RTE_QEI_DIR_PAD 6
+#elif (RTE_QEI_DIR_PORT_ID == 1)
+#define RTE_QEI_DIR_PORT HP
+#define RTE_QEI_DIR_PIN 28
+#define RTE_QEI_DIR_MUX 5
+#define RTE_QEI_DIR_PAD 0
+#elif (RTE_QEI_DIR_PORT_ID == 2)
+#define RTE_QEI_DIR_PORT HP
+#define RTE_QEI_DIR_PIN 49
+#define RTE_QEI_DIR_MUX 3
+#define RTE_QEI_DIR_PAD 13
+#elif (RTE_QEI_DIR_PORT_ID == 3)
+#define RTE_QEI_DIR_PORT HP
+#define RTE_QEI_DIR_PIN 34
+#define RTE_QEI_DIR_MUX 13
+#define RTE_QEI_DIR_PAD 9
+#elif (RTE_QEI_DIR_PORT_ID == 4)
+#define RTE_QEI_DIR_PORT HP
+#define RTE_QEI_DIR_PIN 57
+#define RTE_QEI_DIR_MUX 5
+#define RTE_QEI_DIR_PAD 21
+#elif (RTE_QEI_DIR_PORT_ID == 5)
+#define RTE_QEI_DIR_PORT HP
+#define RTE_QEI_DIR_PIN 71
+#define RTE_QEI_DIR_MUX 3
+#define RTE_QEI_DIR_PAD 29
+#elif (RTE_QEI_DIR_PORT_ID == 6)
+#define RTE_QEI_DIR_PORT HP
+#define RTE_QEI_DIR_PIN 75
+#define RTE_QEI_DIR_MUX 3
+#define RTE_QEI_DIR_PAD 33
+#else
+#error "Invalid RTE_QEI_DIR_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_QEI_DIR_PORT HP
+#if (QEI_DIR_LOC == 0)
+#define RTE_QEI_DIR_PIN QEI_DIR_PIN
+#define RTE_QEI_DIR_MUX 5
+#define RTE_QEI_DIR_PAD 6
+#endif
+#if (QEI_DIR_LOC == 1)
+#define RTE_QEI_DIR_PIN QEI_DIR_PIN
+#define RTE_QEI_DIR_MUX 5
+#define RTE_QEI_DIR_PAD 0
+#endif
+#if (QEI_DIR_LOC == 2)
+#define RTE_QEI_DIR_PIN QEI_DIR_PIN
+#define RTE_QEI_DIR_MUX 3
+#define RTE_QEI_DIR_PAD 13
+#endif
+#if (QEI_DIR_LOC == 3)
+#define RTE_QEI_DIR_PIN QEI_DIR_PIN
+#define RTE_QEI_DIR_MUX 13
+#define RTE_QEI_DIR_PAD 9
+#endif
+#if (QEI_DIR_LOC == 4)
+#define RTE_QEI_DIR_PIN QEI_DIR_PIN
+#define RTE_QEI_DIR_MUX 5
+#define RTE_QEI_DIR_PAD 21
+#endif
+#if (QEI_DIR_LOC == 5)
+#define RTE_QEI_DIR_PIN (QEI_DIR_PIN + GPIO_MAX_PIN)
+#define RTE_QEI_DIR_MUX 3
+#define RTE_QEI_DIR_PAD 29
+#endif
+#if (QEI_DIR_LOC == 6)
+#define RTE_QEI_DIR_PIN (QEI_DIR_PIN + GPIO_MAX_PIN)
+#define RTE_QEI_DIR_MUX 3
+#define RTE_QEI_DIR_PAD 33
+#endif
+//Pintool data
+#endif
+
+//QEI_IDX <0=>GPIO_8 <1=>GPIO_25 <2=>GPIO_46 <3=>GPIO_31 <4=>GPIO_52 <5=>GPIO_68 <6=>GPIO_64 <7=>GPIO_72
+#ifndef QEI_IDX_LOC
+#define RTE_QEI_IDX_PORT_ID 3
+
+#if (RTE_QEI_IDX_PORT_ID == 0)
+#define RTE_QEI_IDX_PORT HP
+#define RTE_QEI_IDX_PIN 8
+#define RTE_QEI_IDX_MUX 5
+#define RTE_QEI_IDX_PAD 3
+#elif (RTE_QEI_IDX_PORT_ID == 1)
+#define RTE_QEI_IDX_PORT HP
+#define RTE_QEI_IDX_PIN 25
+#define RTE_QEI_IDX_MUX 5
+#define RTE_QEI_IDX_PAD 0
+#elif (RTE_QEI_IDX_PORT_ID == 2)
+#define RTE_QEI_IDX_PORT HP
+#define RTE_QEI_IDX_PIN 46
+#define RTE_QEI_IDX_MUX 3
+#define RTE_QEI_IDX_PAD 10
+#elif (RTE_QEI_IDX_PORT_ID == 3)
+#define RTE_QEI_IDX_PORT HP
+#define RTE_QEI_IDX_PIN 31
+#define RTE_QEI_IDX_MUX 13
+#define RTE_QEI_IDX_PAD 9
+#elif (RTE_QEI_IDX_PORT_ID == 4)
+#define RTE_QEI_IDX_PORT HP
+#define RTE_QEI_IDX_PIN 52
+#define RTE_QEI_IDX_MUX 5
+#define RTE_QEI_IDX_PAD 16
+#elif (RTE_QEI_IDX_PORT_ID == 5)
+#define RTE_QEI_IDX_PORT HP
+#define RTE_QEI_IDX_PIN 68
+#define RTE_QEI_IDX_MUX 3
+#define RTE_QEI_IDX_PAD 26
+#elif (RTE_QEI_IDX_PORT_ID == 6)
+#define RTE_QEI_IDX_PORT HP
+#define RTE_QEI_IDX_PIN 64
+#define RTE_QEI_IDX_MUX 3
+#define RTE_QEI_IDX_PAD 22
+#elif (RTE_QEI_IDX_PORT_ID == 7)
+#define RTE_QEI_IDX_PORT HP
+#define RTE_QEI_IDX_PIN 72
+#define RTE_QEI_IDX_MUX 3
+#define RTE_QEI_IDX_PAD 30
+#else
+#error "Invalid RTE_QEI_IDX_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_QEI_IDX_PORT HP
+#if (QEI_IDX_LOC == 7)
+#define RTE_QEI_IDX_PIN QEI_IDX_PIN
+#define RTE_QEI_IDX_MUX 5
+#define RTE_QEI_IDX_PAD 3
+#endif
+#if (QEI_IDX_LOC == 8)
+#define RTE_QEI_IDX_PIN QEI_IDX_PIN
+#define RTE_QEI_IDX_MUX 5
+#define RTE_QEI_IDX_PAD 0
+#endif
+#if (QEI_IDX_LOC == 9)
+#define RTE_QEI_IDX_PIN QEI_IDX_PIN
+#define RTE_QEI_IDX_MUX 3
+#define RTE_QEI_IDX_PAD 10
+#endif
+#if (QEI_IDX_LOC == 10)
+#define RTE_QEI_IDX_PIN QEI_IDX_PIN
+#define RTE_QEI_IDX_MUX 13
+#define RTE_QEI_IDX_PAD 9
+#endif
+#if (QEI_IDX_LOC == 11)
+#define RTE_QEI_IDX_PIN QEI_IDX_PIN
+#define RTE_QEI_IDX_MUX 5
+#define RTE_QEI_IDX_PAD 16
+#endif
+#if (QEI_IDX_LOC == 12)
+#define RTE_QEI_IDX_PIN (QEI_IDX_PIN + GPIO_MAX_PIN)
+#define RTE_QEI_IDX_MUX 3
+#define RTE_QEI_IDX_PAD 26
+#endif
+#if (QEI_IDX_LOC == 13)
+#define RTE_QEI_IDX_PIN (QEI_IDX_PIN + GPIO_MAX_PIN)
+#define RTE_QEI_IDX_MUX 3
+#define RTE_QEI_IDX_PAD 22
+#endif
+#if (QEI_IDX_LOC == 14)
+#define RTE_QEI_IDX_PIN (QEI_IDX_PIN + GPIO_MAX_PIN)
+#define RTE_QEI_IDX_MUX 3
+#define RTE_QEI_IDX_PAD 30
+#endif
+//Pintool data
+#endif
+
+//QEI_PHA <0=>GPIO_9 <1=>GPIO_26 <2=>GPIO_47 <3=>GPIO_32 <4=>GPIO_53 <5=>GPIO_69 <6=>GPIO_65 <7=>GPIO_73
+#ifndef QEI_PHA_LOC
+#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
+#define RTE_QEI_PHA_PORT_ID 3
+#else
+#define RTE_QEI_PHA_PORT_ID 5
+#endif
+
+#if (RTE_QEI_PHA_PORT_ID == 0)
+#define RTE_QEI_PHA_PORT HP
+#define RTE_QEI_PHA_PIN 9
+#define RTE_QEI_PHA_MUX 5
+#define RTE_QEI_PHA_PAD 4
+#elif (RTE_QEI_PHA_PORT_ID == 1)
+#define RTE_QEI_PHA_PORT HP
+#define RTE_QEI_PHA_PIN 26
+#define RTE_QEI_PHA_MUX 5
+#define RTE_QEI_PHA_PAD 0
+#elif (RTE_QEI_PHA_PORT_ID == 2)
+#define RTE_QEI_PHA_PORT HP
+#define RTE_QEI_PHA_PIN 47
+#define RTE_QEI_PHA_MUX 3
+#define RTE_QEI_PHA_PAD 11
+#elif (RTE_QEI_PHA_PORT_ID == 3)
+#define RTE_QEI_PHA_PORT HP
+#define RTE_QEI_PHA_PIN 32
+#define RTE_QEI_PHA_MUX 13
+#define RTE_QEI_PHA_PAD 9
+#elif (RTE_QEI_PHA_PORT_ID == 4)
+#define RTE_QEI_PHA_PORT HP
+#define RTE_QEI_PHA_PIN 53
+#define RTE_QEI_PHA_MUX 5
+#define RTE_QEI_PHA_PAD 17
+#elif (RTE_QEI_PHA_PORT_ID == 5)
+#define RTE_QEI_PHA_PORT HP
+#define RTE_QEI_PHA_PIN 69
+#define RTE_QEI_PHA_MUX 3
+#define RTE_QEI_PHA_PAD 27
+#elif (RTE_QEI_PHA_PORT_ID == 6)
+#define RTE_QEI_PHA_PORT HP
+#define RTE_QEI_PHA_PIN 65
+#define RTE_QEI_PHA_MUX 3
+#define RTE_QEI_PHA_PAD 23
+#elif (RTE_QEI_PHA_PORT_ID == 7)
+#define RTE_QEI_PHA_PORT HP
+#define RTE_QEI_PHA_PIN 73
+#define RTE_QEI_PHA_MUX 3
+#define RTE_QEI_PHA_PAD 31
+#else
+#error "Invalid RTE_QEI_PHA_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_QEI_PHA_PORT HP
+#if (QEI_PHA_LOC == 15)
+#define RTE_QEI_PHA_PIN QEI_PHA_PIN
+#define RTE_QEI_PHA_MUX 5
+#define RTE_QEI_PHA_PAD 4
+#endif
+#if (QEI_PHA_LOC == 16)
+#define RTE_QEI_PHA_PIN QEI_PHA_PIN
+#define RTE_QEI_PHA_MUX 5
+#define RTE_QEI_PHA_PAD 0
+#endif
+#if (QEI_PHA_LOC == 17)
+#define RTE_QEI_PHA_PIN QEI_PHA_PIN
+#define RTE_QEI_PHA_MUX 3
+#define RTE_QEI_PHA_PAD 11
+#endif
+#if (QEI_PHA_LOC == 18)
+#define RTE_QEI_PHA_PIN QEI_PHA_PIN
+#define RTE_QEI_PHA_MUX 13
+#define RTE_QEI_PHA_PAD 9
+#endif
+#if (QEI_PHA_LOC == 19)
+#define RTE_QEI_PHA_PIN QEI_PHA_PIN
+#define RTE_QEI_PHA_MUX 5
+#define RTE_QEI_PHA_PAD 17
+#endif
+#if (QEI_PHA_LOC == 20)
+#define RTE_QEI_PHA_PIN (QEI_PHA_PIN + GPIO_MAX_PIN)
+#define RTE_QEI_PHA_MUX 3
+#define RTE_QEI_PHA_PAD 27
+#endif
+#if (QEI_PHA_LOC == 21)
+#define RTE_QEI_PHA_PIN (QEI_PHA_PIN + GPIO_MAX_PIN)
+#define RTE_QEI_PHA_MUX 3
+#define RTE_QEI_PHA_PAD 23
+#endif
+#if (QEI_PHA_LOC == 22)
+#define RTE_QEI_PHA_PIN (QEI_PHA_PIN + GPIO_MAX_PIN)
+#define RTE_QEI_PHA_MUX 3
+#define RTE_QEI_PHA_PAD 31
+#endif
+//Pintool data
+#endif
+
+//QEI_PHB <0=>GPIO_10 <1=>GPIO_27 <1=>GPIO_48 <1=>GPIO_33 <1=>GPIO_56 <1=>GPIO_70 <7=>GPIO_74
+#ifndef QEI_PHB_LOC
+#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
+#define RTE_QEI_PHB_PORT_ID 5
+#else
+#define RTE_QEI_PHB_PORT_ID 4
+#endif
+
+#if (RTE_QEI_PHB_PORT_ID == 0)
+#define RTE_QEI_PHB_PORT HP
+#define RTE_QEI_PHB_PIN 10
+#define RTE_QEI_PHB_MUX 5
+#define RTE_QEI_PHB_PAD 5
+#elif (RTE_QEI_PHB_PORT_ID == 1)
+#define RTE_QEI_PHB_PORT HP
+#define RTE_QEI_PHB_PIN 27
+#define RTE_QEI_PHB_MUX 5
+#define RTE_QEI_PHB_PAD 0
+#elif (RTE_QEI_PHB_PORT_ID == 2)
+#define RTE_QEI_PHB_PORT HP
+#define RTE_QEI_PHB_PIN 48
+#define RTE_QEI_PHB_MUX 3
+#define RTE_QEI_PHB_PAD 12
+#elif (RTE_QEI_PHB_PORT_ID == 3)
+#define RTE_QEI_PHB_PORT HP
+#define RTE_QEI_PHB_PIN 33
+#define RTE_QEI_PHB_MUX 13
+#define RTE_QEI_PHB_PAD 9
+#elif (RTE_QEI_PHB_PORT_ID == 4)
+#define RTE_QEI_PHB_PORT HP
+#define RTE_QEI_PHB_PIN 56
+#define RTE_QEI_PHB_MUX 5
+#define RTE_QEI_PHB_PAD 20
+#elif (RTE_QEI_PHB_PORT_ID == 5)
+#define RTE_QEI_PHB_PORT HP
+#define RTE_QEI_PHB_PIN 70
+#define RTE_QEI_PHB_MUX 3
+#define RTE_QEI_PHB_PAD 28
+#elif (RTE_QEI_PHB_PORT_ID == 6)
+#define RTE_QEI_PHB_PORT HP
+#define RTE_QEI_PHB_PIN 74
+#define RTE_QEI_PHB_MUX 3
+#define RTE_QEI_PHB_PAD 32
+#else
+#error "Invalid RTE_QEI_PHB_PIN Pin Configuration!"
+#endif
+#else
+//Pintool data
+#define RTE_QEI_PHB_PORT HP
+#if (QEI_PHB_LOC == 23)
+#define RTE_QEI_PHB_PIN QEI_PHB_PIN
+#define RTE_QEI_PHB_MUX 5
+#define RTE_QEI_PHB_PAD 5
+#endif
+#if (QEI_PHB_LOC == 24)
+#define RTE_QEI_PHB_PIN QEI_PHB_PIN
+#define RTE_QEI_PHB_MUX 5
+#define RTE_QEI_PHB_PAD 0
+#endif
+#if (QEI_PHB_LOC == 25)
+#define RTE_QEI_PHB_PIN QEI_PHB_PIN
+#define RTE_QEI_PHB_MUX 3
+#define RTE_QEI_PHB_PAD 12
+#endif
+#if (QEI_PHB_LOC == 26)
+#define RTE_QEI_PHB_PIN QEI_PHB_PIN
+#define RTE_QEI_PHB_MUX 13
+#define RTE_QEI_PHB_PAD 9
+#endif
+#if (QEI_PHB_LOC == 27)
+#define RTE_QEI_PHB_PIN QEI_PHB_PIN
+#define RTE_QEI_PHB_MUX 5
+#define RTE_QEI_PHB_PAD 20
+#endif
+#if (QEI_PHB_LOC == 28)
+#define RTE_QEI_PHB_PIN (QEI_PHB_PIN + GPIO_MAX_PIN)
+#define RTE_QEI_PHB_MUX 3
+#define RTE_QEI_PHB_PAD 28
+#endif
+#if (QEI_PHB_LOC == 29)
+#define RTE_QEI_PHB_PIN (QEI_PHB_PIN + GPIO_MAX_PIN)
+#define RTE_QEI_PHB_MUX 3
+#define RTE_QEI_PHB_PAD 32
+#endif
+//Pintool data
+#endif
+
+#endif
+//COMPARATOR START
+
+#ifndef COMP1_P0_LOC
+#define RTE_COMP1_P0_PORT HP
+#define RTE_COMP1_P0_PIN 0
+#else
+#define RTE_COMP1_P0_PORT HP
+#define RTE_COMP1_P0_PIN COMP1_P0_PIN
+#endif
+#define RTE_COMP1_P0_MUX 0
+
+#ifndef COMP1_N0_LOC
+#define RTE_COMP1_N0_PORT HP
+#define RTE_COMP1_N0_PIN 1
+#else
+#define RTE_COMP1_N0_PORT HP
+#define RTE_COMP1_N0_PIN COMP1_N0_PIN
+#endif
+#define RTE_COMP1_N0_MUX 0
+
+#ifndef COMP1_P1_LOC
+#define RTE_COMP1_P1_PORT HP
+#define RTE_COMP1_P1_PIN 5
+#else
+#define RTE_COMP1_P1_PORT HP
+#define RTE_COMP1_P1_PIN COMP1_P1_PIN
+#endif
+#define RTE_COMP1_P1_MUX 0
+
+#ifndef COMP1_N1_LOC
+#define RTE_COMP1_N1_PORT HP
+#define RTE_COMP1_N1_PIN 4
+#else
+#define RTE_COMP1_N1_PORT HP
+#define RTE_COMP1_N1_PIN COMP1_N1_PIN
+#endif
+#define RTE_COMP1_N1_MUX 0
+
+#ifndef COMP2_P0_LOC
+#define RTE_COMP2_P0_PORT HP
+#define RTE_COMP2_P0_PIN 2
+#else
+#define RTE_COMP2_P0_PORT HP
+#define RTE_COMP2_P0_PIN COMP2_P0_PIN
+#endif
+#define RTE_COMP2_P0_MUX 0
+
+#ifndef COMP2_N0_LOC
+#define RTE_COMP2_N0_PORT HP
+#define RTE_COMP2_N0_PIN 3
+#else
+#define RTE_COMP2_N0_PORT HP
+#define RTE_COMP2_N0_PIN COMP2_N0_PIN
+#endif
+#define RTE_COMP2_N0_MUX 0
+
+#ifndef COMP2_P1_LOC
+#define RTE_COMP2_P1_PORT HP
+#define RTE_COMP2_P1_PIN 27
+#else
+#define RTE_COMP2_P1_PORT HP
+#define RTE_COMP2_P1_PIN COMP2_P1_PIN
+#endif
+#define RTE_COMP2_P1_MUX 0
+#define RTE_COMP2_P1_PAD 0
+
+#ifndef COMP2_N1_LOC
+#define RTE_COMP2_N1_PORT HP
+#define RTE_COMP2_N1_PIN 28
+#else
+#define RTE_COMP2_N1_PORT HP
+#define RTE_COMP2_N1_PIN COMP2_N1_PIN
+#endif
+#define RTE_COMP2_N1_MUX 0
+
+//COMPARATOR END
+
+#define RTE_GPIO_6_PORT HP
+#define RTE_GPIO_6_PAD 1
+#define RTE_GPIO_6_PIN 6
+#define RTE_GPIO_6_MODE 0
+
+#define RTE_GPIO_7_PORT HP
+#define RTE_GPIO_7_PAD 2
+#define RTE_GPIO_7_PIN 7
+#define RTE_GPIO_7_MODE 0
+
+#define RTE_GPIO_8_PORT HP
+#define RTE_GPIO_8_PAD 3
+#define RTE_GPIO_8_PIN 8
+#define RTE_GPIO_8_MODE 0
+
+#define RTE_GPIO_9_PORT HP
+#define RTE_GPIO_9_PAD 4
+#define RTE_GPIO_9_PIN 9
+#define RTE_GPIO_9_MODE 0
+
+#define RTE_GPIO_10_PORT HP
+#define RTE_GPIO_10_PAD 5
+#define RTE_GPIO_10_PIN 10
+#define RTE_GPIO_10_MODE 0
+
+#define RTE_GPIO_11_PORT HP
+#define RTE_GPIO_11_PAD 6
+#define RTE_GPIO_11_PIN 11
+#define RTE_GPIO_11_MODE 0
+
+#define RTE_GPIO_12_PORT HP
+#define RTE_GPIO_12_PAD 7
+#define RTE_GPIO_12_PIN 12
+#define RTE_GPIO_12_MODE 0
+
+#define RTE_GPIO_15_PORT HP
+#define RTE_GPIO_15_PAD 8
+#define RTE_GPIO_15_PIN 15
+#define RTE_GPIO_15_MODE 0
+
+#define RTE_GPIO_25_PORT HP
+#define RTE_GPIO_25_PIN 25
+#define RTE_GPIO_25_MODE 0
+
+#define RTE_GPIO_26_PORT HP
+#define RTE_GPIO_26_PIN 26
+#define RTE_GPIO_26_MODE 0
+
+#define RTE_GPIO_27_PORT HP
+#define RTE_GPIO_27_PIN 27
+#define RTE_GPIO_27_MODE 0
+
+#define RTE_GPIO_28_PORT HP
+#define RTE_GPIO_28_PIN 28
+#define RTE_GPIO_28_MODE 0
+
+#define RTE_GPIO_29_PORT HP
+#define RTE_GPIO_29_PIN 29
+#define RTE_GPIO_29_MODE 0
+
+#define RTE_GPIO_30_PORT HP
+#define RTE_GPIO_30_PIN 30
+#define RTE_GPIO_30_MODE 0
+
+#define RTE_GPIO_31_PORT HP
+#define RTE_GPIO_31_PAD 9
+#define RTE_GPIO_31_PIN 31
+#define RTE_GPIO_31_MODE 0
+
+#define RTE_GPIO_32_PORT HP
+#define RTE_GPIO_32_PAD 9
+#define RTE_GPIO_32_PIN 32
+#define RTE_GPIO_32_MODE 0
+
+#define RTE_GPIO_33_PORT HP
+#define RTE_GPIO_33_PAD 9
+#define RTE_GPIO_33_PIN 33
+#define RTE_GPIO_33_MODE 0
+
+#define RTE_GPIO_34_PORT HP
+#define RTE_GPIO_34_PAD 9
+#define RTE_GPIO_34_PIN 34
+#define RTE_GPIO_34_MODE 0
+
+#define RTE_GPIO_46_PORT HP
+#define RTE_GPIO_46_PAD 10
+#define RTE_GPIO_46_PIN 46
+#define RTE_GPIO_46_MODE 0
+
+#define RTE_GPIO_47_PORT HP
+#define RTE_GPIO_47_PAD 11
+#define RTE_GPIO_47_PIN 47
+#define RTE_GPIO_47_MODE 0
+
+#define RTE_GPIO_48_PORT HP
+#define RTE_GPIO_48_PAD 12
+#define RTE_GPIO_48_PIN 48
+#define RTE_GPIO_48_MODE 0
+
+#define RTE_GPIO_49_PORT HP
+#define RTE_GPIO_49_PAD 13
+#define RTE_GPIO_49_PIN 49
+#define RTE_GPIO_49_MODE 0
+
+#define RTE_GPIO_50_PORT HP
+#define RTE_GPIO_50_PAD 14
+#define RTE_GPIO_50_PIN 50
+#define RTE_GPIO_50_MODE 0
+
+#define RTE_GPIO_51_PORT HP
+#define RTE_GPIO_51_PAD 15
+#define RTE_GPIO_51_PIN 51
+#define RTE_GPIO_51_MODE 0
+
+#define RTE_GPIO_52_PORT HP
+#define RTE_GPIO_52_PAD 16
+#define RTE_GPIO_52_PIN 52
+#define RTE_GPIO_52_MODE 0
+
+#define RTE_GPIO_53_PORT HP
+#define RTE_GPIO_53_PAD 17
+#define RTE_GPIO_53_PIN 53
+#define RTE_GPIO_53_MODE 0
+
+#define RTE_GPIO_54_PORT HP
+#define RTE_GPIO_54_PAD 18
+#define RTE_GPIO_54_PIN 54
+#define RTE_GPIO_54_MODE 0
+
+#define RTE_GPIO_55_PORT HP
+#define RTE_GPIO_55_PAD 19
+#define RTE_GPIO_55_PIN 55
+#define RTE_GPIO_55_MODE 0
+
+#define RTE_GPIO_56_PORT HP
+#define RTE_GPIO_56_PAD 20
+#define RTE_GPIO_56_PIN 56
+#define RTE_GPIO_56_MODE 0
+
+#define RTE_GPIO_57_PORT HP
+#define RTE_GPIO_57_PAD 21
+#define RTE_GPIO_57_PIN 57
+#define RTE_GPIO_57_MODE 0
+
+#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
+#define RTE_ULP_GPIO_0_PORT_ID 1
+#else
+#define RTE_ULP_GPIO_0_PORT_ID 0
+#endif
+
+#if (RTE_ULP_GPIO_0_PORT_ID == 0)
+#define RTE_ULP_GPIO_0_PORT HP
+#define RTE_ULP_GPIO_0_PAD 22
+#define RTE_ULP_GPIO_0_PIN 64
+#define RTE_ULP_GPIO_0_MODE 0
+#elif (RTE_ULP_GPIO_0_PORT_ID == 1)
+#define RTE_ULP_GPIO_0_PORT ULP
+#define RTE_ULP_GPIO_0_PIN 0
+#define RTE_ULP_GPIO_0_MODE 0
+#else
+#error "Invalid RTE_ULP_GPIO_0_PIN Pin Configuration!"
+#endif
+
+#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
+#define RTE_ULP_GPIO_1_PORT_ID 1
+#else
+#define RTE_ULP_GPIO_1_PORT_ID 0
+#endif
+
+#if (RTE_ULP_GPIO_1_PORT_ID == 0)
+#define RTE_ULP_GPIO_1_PORT HP
+#define RTE_ULP_GPIO_1_PAD 23
+#define RTE_ULP_GPIO_1_PIN 65
+#define RTE_ULP_GPIO_1_MODE 0
+#elif (RTE_ULP_GPIO_1_PORT_ID == 1)
+#define RTE_ULP_GPIO_1_PORT ULP
+#define RTE_ULP_GPIO_1_PIN 1
+#define RTE_ULP_GPIO_1_MODE 0
+#else
+#error "Invalid RTE_ULP_GPIO_1_PIN Pin Configuration!"
+#endif
+
+#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
+#define RTE_ULP_GPIO_2_PORT_ID 1
+#else
+#define RTE_ULP_GPIO_2_PORT_ID 0
+#endif
+
+#if (RTE_ULP_GPIO_2_PORT_ID == 0)
+#define RTE_ULP_GPIO_2_PORT HP
+#define RTE_ULP_GPIO_2_PAD 24
+#define RTE_ULP_GPIO_2_PIN 66
+#define RTE_ULP_GPIO_2_MODE 0
+#elif (RTE_ULP_GPIO_2_PORT_ID == 1)
+#define RTE_ULP_GPIO_2_PORT ULP
+#define RTE_ULP_GPIO_2_PIN 2
+#define RTE_ULP_GPIO_2_MODE 0
+#else
+#error "Invalid RTE_ULP_GPIO_2_PIN Pin Configuration!"
+#endif
+
+#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
+#define RTE_ULP_GPIO_4_PORT_ID 1
+#else
+#define RTE_ULP_GPIO_4_PORT_ID 0
+#endif
+
+#if (RTE_ULP_GPIO_4_PORT_ID == 0)
+#define RTE_ULP_GPIO_4_PORT HP
+#define RTE_ULP_GPIO_4_PAD 26
+#define RTE_ULP_GPIO_4_PIN 68
+#define RTE_ULP_GPIO_4_MODE 0
+#elif (RTE_ULP_GPIO_4_PORT_ID == 1)
+#define RTE_ULP_GPIO_4_PORT ULP
+#define RTE_ULP_GPIO_4_PIN 4
+#define RTE_ULP_GPIO_4_MODE 0
+#else
+#error "Invalid RTE_ULP_GPIO_4_PIN Pin Configuration!"
+#endif
+
+#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
+#define RTE_ULP_GPIO_5_PORT_ID 1
+#else
+#define RTE_ULP_GPIO_5_PORT_ID 0
+#endif
+
+#if (RTE_ULP_GPIO_5_PORT_ID == 0)
+#define RTE_ULP_GPIO_5_PORT ULP
+#define RTE_ULP_GPIO_5_PAD 27
+#define RTE_ULP_GPIO_5_PIN 69
+#define RTE_ULP_GPIO_5_MODE 0
+#elif (RTE_ULP_GPIO_5_PORT_ID == 1)
+#define RTE_ULP_GPIO_5_PORT ULP
+#define RTE_ULP_GPIO_5_PIN 5
+#define RTE_ULP_GPIO_5_MODE 0
+#else
+#error "Invalid RTE_ULP_GPIO_5_PIN Pin Configuration!"
+#endif
+
+#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
+#define RTE_ULP_GPIO_6_PORT_ID 1
+#else
+#define RTE_ULP_GPIO_6_PORT_ID 0
+#endif
+
+#if (RTE_ULP_GPIO_6_PORT_ID == 0)
+#define RTE_ULP_GPIO_6_PORT ULP
+#define RTE_ULP_GPIO_6_PAD 28
+#define RTE_ULP_GPIO_6_PIN 70
+#define RTE_ULP_GPIO_6_MODE 0
+#elif (RTE_ULP_GPIO_6_PORT_ID == 1)
+#define RTE_ULP_GPIO_6_PORT ULP
+#define RTE_ULP_GPIO_6_PIN 6
+#define RTE_ULP_GPIO_6_MODE 0
+#else
+#error "Invalid RTE_ULP_GPIO_6_PIN Pin Configuration!"
+#endif
+
+#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
+#define RTE_ULP_GPIO_7_PORT_ID 1
+#else
+#define RTE_ULP_GPIO_7_PORT_ID 0
+#endif
+
+#if (RTE_ULP_GPIO_7_PORT_ID == 0)
+#define RTE_ULP_GPIO_7_PORT ULP
+#define RTE_ULP_GPIO_7_PAD 29
+#define RTE_ULP_GPIO_7_PIN 71
+#define RTE_ULP_GPIO_7_MODE 0
+#elif (RTE_ULP_GPIO_7_PORT_ID == 1)
+#define RTE_ULP_GPIO_7_PORT ULP
+#define RTE_ULP_GPIO_7_PIN 7
+#define RTE_ULP_GPIO_7_MODE 0
+#else
+#error "Invalid RTE_ULP_GPIO_7_PIN Pin Configuration!"
+#endif
+
+#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
+#define RTE_ULP_GPIO_8_PORT_ID 1
+#else
+#define RTE_ULP_GPIO_8_PORT_ID 0
+#endif
+
+#if (RTE_ULP_GPIO_8_PORT_ID == 0)
+#define RTE_ULP_GPIO_8_PORT ULP
+#define RTE_ULP_GPIO_8_PAD 30
+#define RTE_ULP_GPIO_8_PIN 72
+#define RTE_ULP_GPIO_8_MODE 0
+#elif (RTE_ULP_GPIO_8_PORT_ID == 1)
+#define RTE_ULP_GPIO_8_PORT ULP
+#define RTE_ULP_GPIO_8_PIN 8
+#define RTE_ULP_GPIO_8_MODE 0
+#else
+#error "Invalid RTE_ULP_GPIO_8_PIN Pin Configuration!"
+#endif
+
+#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
+#define RTE_ULP_GPIO_9_PORT_ID 1
+#else
+#define RTE_ULP_GPIO_9_PORT_ID 0
+#endif
+
+#if (RTE_ULP_GPIO_9_PORT_ID == 0)
+#define RTE_ULP_GPIO_9_PORT ULP
+#define RTE_ULP_GPIO_9_PAD 31
+#define RTE_ULP_GPIO_9_PIN 73
+#define RTE_ULP_GPIO_9_MODE 0
+#elif (RTE_ULP_GPIO_9_PORT_ID == 1)
+#define RTE_ULP_GPIO_9_PORT ULP
+#define RTE_ULP_GPIO_9_PIN 9
+#define RTE_ULP_GPIO_9_MODE 0
+#else
+#error "Invalid RTE_ULP_GPIO_9_PIN Pin Configuration!"
+#endif
+
+#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
+#define RTE_ULP_GPIO_10_PORT_ID 1
+#else
+#define RTE_ULP_GPIO_10_PORT_ID 0
+#endif
+
+#if (RTE_ULP_GPIO_10_PORT_ID == 0)
+#define RTE_ULP_GPIO_10_PORT ULP
+#define RTE_ULP_GPIO_10_PAD 32
+#define RTE_ULP_GPIO_10_PIN 74
+#define RTE_ULP_GPIO_10_MODE 0
+#elif (RTE_ULP_GPIO_10_PORT_ID == 1)
+#define RTE_ULP_GPIO_10_PORT ULP
+#define RTE_ULP_GPIO_10_PIN 10
+#define RTE_ULP_GPIO_10_MODE 0
+#else
+#error "Invalid RTE_ULP_GPIO_10_PIN Pin Configuration!"
+#endif
+
+#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
+#define RTE_ULP_GPIO_11_PORT_ID 1
+#else
+#define RTE_ULP_GPIO_11_PORT_ID 0
+#endif
+
+#if (RTE_ULP_GPIO_11_PORT_ID == 0)
+#define RTE_ULP_GPIO_11_PORT ULP
+#define RTE_ULP_GPIO_11_PAD 33
+#define RTE_ULP_GPIO_11_PIN 75
+#define RTE_ULP_GPIO_11_MODE 0
+#elif (RTE_ULP_GPIO_11_PORT_ID == 1)
+#define RTE_ULP_GPIO_11_PORT ULP
+#define RTE_ULP_GPIO_11_PIN 11
+#define RTE_ULP_GPIO_11_MODE 0
+#else
+#error "Invalid RTE_ULP_GPIO_11_PIN Pin Configuration!"
+#endif
+
+// RTE_UULP_GPIO_x_PORT refers to port for UULP GPIO pin x
+#define RTE_UULP_GPIO_0_PORT UULP_VBAT
+#define RTE_UULP_GPIO_0_PIN 0
+#define RTE_UULP_GPIO_0_MODE 0
+
+#define RTE_UULP_GPIO_1_PORT UULP_VBAT
+#define RTE_UULP_GPIO_1_PIN 1
+#define RTE_UULP_GPIO_1_MODE 0
+
+#define RTE_UULP_GPIO_2_PORT UULP_VBAT
+#define RTE_UULP_GPIO_2_PIN 2
+#define RTE_UULP_GPIO_2_MODE 0
+
+#define RTE_UULP_GPIO_3_PORT UULP_VBAT
+#define RTE_UULP_GPIO_3_PIN 3
+#define RTE_UULP_GPIO_3_MODE 0
+
+// UULP GPIO as enable pin for sensors
+#define SENSOR_ENABLE_GPIO_MAPPED_TO_UULP
+#define SENSOR_ENABLE_GPIO_PIN RTE_UULP_GPIO_1_PIN
+
+// Memlcd GPIOs
+#define RTE_MEMLCD_CS_PIN 10 // Memlcd SPI CS pin
+#define RTE_MEMLCD_CS_PORT HP // Memlcd SPI CS port
+
+#define RTE_MEMLCD_EXTCOMIN_PIN 3 // Memlcd external communication pin
+#define RTE_MEMLCD_EXTCOMIN_PORT HP // Memlcd external communication port
+
+#define RTE_MEMLCD_ENABLE_DISPLAY_PIN 0 // Memlcd display enable pin
+#define RTE_MEMLCD_ENABLE_DISPLAY_PORT HP // Memlcd display enable port
+
+// GPIO as enable pin for Mic
+#define RTE_MIC_ENABLE_PORT RTE_UULP_GPIO_0_PORT
+#define RTE_MIC_ENABLE_PIN RTE_UULP_GPIO_0_PIN
+
+// UART0_RS485_RE Pin <0=>P0_28 <1=>P0_50 <2=>P0_66 <3=>P0_70 <4=>P0_74
+#ifndef USART0_RE_LOC
+
+#define RTE_UART0_RS485_RE_PORT_ID 0
+#if (RTE_UART0_RS485_RE_PORT_ID == 0)
+#define RTE_UART0_RS485_RE_PIN 28
+#define RTE_UART0_RS485_RE_PORT 0
+#define RTE_UART0_RS485_RE_MUX 13
+#define RTE_UART0_RS485_RE_PAD 0
+#elif (RTE_UART0_RS485_RE_PORT_ID == 1)
+#define RTE_UART0_RS485_RE_PIN 50
+#define RTE_UART0_RS485_RE_PORT 0
+#define RTE_UART0_RS485_RE_MUX 2
+#define RTE_UART0_RS485_RE_PAD 14
+#elif (RTE_UART0_RS485_RE_PORT_ID == 2)
+#define RTE_UART0_RS485_RE_PIN 70
+#define RTE_UART0_RS485_RE_PORT 0
+#define RTE_UART0_RS485_RE_MUX 6
+#define RTE_UART0_RS485_RE_PAD 28
+#elif (RTE_UART0_RS485_RE_PORT_ID == 3)
+#define RTE_UART0_RS485_RE_PIN 74
+#define RTE_UART0_RS485_RE_PORT 0
+#define RTE_UART0_RS485_RE_MUX 6
+#define RTE_UART0_RS485_RE_PAD 32
+#else
+#error "Invalid UART0_RS485_RE_PIN"
+#endif
+#else
+//Pintool data
+#define RTE_UART0_RS485_RE_PORT HP
+#if (USART0_RE_LOC == 38)
+#define RTE_UART0_RS485_RE_PIN USART0_RS485_RE_PIN
+#define RTE_UART0_RS485_RE_MUX 13
+#define RTE_UART0_RS485_RE_PAD 0
+#endif
+#if (USART0_RE_LOC == 39)
+#define RTE_UART0_RS485_RE_PIN (USART0_RS485_RE_PIN)
+#define RTE_UART0_RS485_RE_MUX 2
+#define RTE_UART0_RS485_RE_PAD 14
+#endif
+#if (USART0_RE_LOC == 40)
+#define RTE_UART0_RS485_RE_PIN (USART0_RS485_RE_PIN + GPIO_MAX_PIN)
+#define RTE_UART0_RS485_RE_MUX 6
+#define RTE_UART0_RS485_RE_PAD 28
+#endif
+#if (USART0_RE_LOC == 41)
+#define RTE_UART0_RS485_RE_PIN (USART0_RS485_RE_PIN + GPIO_MAX_PIN)
+#define RTE_UART0_RS485_RE_MUX 6
+#define RTE_UART0_RS485_RE_PAD 32
+#endif
+//Pintool data
+#endif
+
+// UART0_RS485_DE Pin <0=>P0_29 <1=>P0_51 <2=>P0_67 <3=>P0_71 <4=>P0_75
+#ifndef USART0_DE_LOC
+
+#define RTE_UART0_RS485_DE_PORT_ID 1
+#if (RTE_UART0_RS485_DE_PORT_ID == 0)
+#define RTE_UART0_RS485_DE_PIN 29
+#define RTE_UART0_RS485_DE_PORT 0
+#define RTE_UART0_RS485_DE_MUX 13
+#define RTE_UART0_RS485_DE_PAD 0
+#elif (RTE_UART0_RS485_DE_PORT_ID == 1)
+#define RTE_UART0_RS485_DE_PIN 51
+#define RTE_UART0_RS485_DE_PORT 0
+#define RTE_UART0_RS485_DE_MUX 2
+#define RTE_UART0_RS485_DE_PAD 15
+#elif (RTE_UART0_RS485_DE_PORT_ID == 2)
+#define RTE_UART0_RS485_DE_PIN 71
+#define RTE_UART0_RS485_DE_PORT 0
+#define RTE_UART0_RS485_DE_MUX 6
+#define RTE_UART0_RS485_DE_PAD 29
+#elif (RTE_UART0_RS485_DE_PORT_ID == 3)
+#define RTE_UART0_RS485_DE_PIN 75
+#define RTE_UART0_RS485_DE_PORT 0
+#define RTE_UART0_RS485_DE_MUX 6
+#define RTE_UART0_RS485_DE_PAD 33
+#else
+#error "Invalid UART0_RS485_DE_PIN"
+#endif
+#else
+//Pintool data
+#define RTE_UART0_RS485_DE_PORT HP
+#if (USART0_DE_LOC == 42)
+#define RTE_UART0_RS485_DE_PIN USART0_RS485_DE_PIN
+#define RTE_UART0_RS485_DE_MUX 13
+#define RTE_UART0_RS485_DE_PAD 0
+#endif
+#if (USART0_DE_LOC == 43)
+#define RTE_UART0_RS485_DE_PIN (USART0_RS485_DE_PIN)
+#define RTE_UART0_RS485_DE_MUX 2
+#define RTE_UART0_RS485_DE_PAD 15
+#endif
+#if (USART0_DE_LOC == 44)
+#define RTE_UART0_RS485_DE_PIN (USART0_RS485_DE_PIN + GPIO_MAX_PIN)
+#define RTE_UART0_RS485_DE_MUX 6
+#define RTE_UART0_RS485_DE_PAD 29
+#endif
+#if (USART0_DE_LOC == 45)
+#define RTE_UART0_RS485_DE_PIN (USART0_RS485_DE_PIN + GPIO_MAX_PIN)
+#define RTE_UART0_RS485_DE_MUX 6
+#define RTE_UART0_RS485_DE_PAD 33
+#endif
+//Pintool data
+#endif
+
+// UART0_RS485_EN Pin <0=>P0_27 <1=>P0_49 <2=>P0_69 <3=>P0_73
+#ifndef USART0_EN_LOC
+
+#define RTE_UART0_RS485_EN_PORT_ID 0
+#if (RTE_UART0_RS485_EN_PORT_ID == 0)
+#define RTE_UART0_RS485_EN_PIN 27
+#define RTE_UART0_RS485_EN_PORT 0
+#define RTE_UART0_RS485_EN_MUX 13
+#define RTE_UART0_RS485_EN_PAD 0
+#elif (RTE_UART0_RS485_EN_PORT_ID == 1)
+#define RTE_UART0_RS485_EN_PIN 49
+#define RTE_UART0_RS485_EN_PORT 0
+#define RTE_UART0_RS485_EN_MUX 2
+#define RTE_UART0_RS485_EN_PAD 13
+#elif (RTE_UART0_RS485_EN_PORT_ID == 2)
+#define RTE_UART0_RS485_EN_PIN 69
+#define RTE_UART0_RS485_EN_PORT 0
+#define RTE_UART0_RS485_EN_MUX 6
+#define RTE_UART0_RS485_EN_PAD 27
+#elif (RTE_UART0_RS485_EN_PORT_ID == 3)
+#define RTE_UART0_RS485_EN_PIN 73
+#define RTE_UART0_RS485_EN_PORT 0
+#define RTE_UART0_RS485_EN_MUX 6
+#define RTE_UART0_RS485_EN_PAD 31
+#else
+#error "Invalid UART0_RS485_EN_PIN"
+#endif
+#else
+//Pintool data
+#define RTE_UART0_RS485_EN_PORT HP
+#if (USART0_EN_LOC == 46)
+#define RTE_UART0_RS485_EN_PIN USART0_RS485_EN_PIN
+#define RTE_UART0_RS485_EN_MUX 13
+#define RTE_UART0_RS485_EN_PAD 0
+#endif
+#if (USART0_EN_LOC == 47)
+#define RTE_UART0_RS485_EN_PIN (USART0_RS485_EN_PIN)
+#define RTE_UART0_RS485_EN_MUX 2
+#define RTE_UART0_RS485_EN_PAD 13
+#endif
+#if (USART0_EN_LOC == 48)
+#define RTE_UART0_RS485_EN_PIN (USART0_RS485_EN_PIN + GPIO_MAX_PIN)
+#define RTE_UART0_RS485_EN_MUX 6
+#define RTE_UART0_RS485_EN_PAD 27
+#endif
+#if (USART0_EN_LOC == 49)
+#define RTE_UART0_RS485_EN_PIN (USART0_RS485_EN_PIN + GPIO_MAX_PIN)
+#define RTE_UART0_RS485_EN_MUX 6
+#define RTE_UART0_RS485_EN_PAD 31
+#endif
+//Pintool data
+#endif
+
+// UART1_RS485_RE Pin <0=>P0_8 <1=>P0_65 <2=>P0_74
+#ifndef UART1_RE_LOC
+
+#define RTE_UART1_RS485_RE_PORT_ID 0
+#if (RTE_UART1_RS485_RE_PORT_ID == 0)
+#define RTE_UART1_RS485_RE_PIN 8
+#define RTE_UART1_RS485_RE_PORT 0
+#define RTE_UART1_RS485_RE_MUX 6
+#define RTE_UART1_RS485_RE_PAD 3
+#elif (RTE_UART1_RS485_RE_PORT_ID == 1)
+#define RTE_UART1_RS485_RE_PIN 65
+#define RTE_UART1_RS485_RE_PORT 0
+#define RTE_UART1_RS485_RE_MUX 6
+#define RTE_UART1_RS485_RE_PAD 23
+#elif (RTE_UART1_RS485_RE_PORT_ID == 2)
+#define RTE_UART1_RS485_RE_PIN 74
+#define RTE_UART1_RS485_RE_PORT 0
+#define RTE_UART1_RS485_RE_MUX 6
+#define RTE_UART1_RS485_RE_PAD 32
+#else
+#error "Invalid UART1_RS485_RE_PIN"
+#endif
+#else
+//Pintool data
+#define RTE_UART1_RS485_RE_PORT HP
+#if (UART1_RE_LOC == 26)
+#define RTE_UART1_RS485_RE_PIN UART1_RS485_RE_PIN
+#define RTE_UART1_RS485_RE_MUX 6
+#define RTE_UART1_RS485_RE_PAD 3
+#endif
+#if (UART1_RE_LOC == 27)
+#define RTE_UART1_RS485_RE_PIN (UART1_RS485_RE_PIN + GPIO_MAX_PIN)
+#define RTE_UART1_RS485_RE_MUX 6
+#define RTE_UART1_RS485_RE_PAD 23
+#endif
+#if (UART1_RE_LOC == 28)
+#define RTE_UART1_RS485_RE_PIN (UART1_RS485_RE_PIN + GPIO_MAX_PIN)
+#define RTE_UART1_RS485_RE_MUX 6
+#define RTE_UART1_RS485_RE_PAD 32
+#endif
+//Pintool data
+#endif
+
+// UART1_RS485_DE Pin <0=>P0_9 <1=>P0_75
+#ifndef UART1_DE_LOC
+
+#define RTE_UART1_RS485_DE_PORT_ID 0
+#if (RTE_UART1_RS485_DE_PORT_ID == 0)
+#define RTE_UART1_RS485_DE_PIN 9
+#define RTE_UART1_RS485_DE_PORT 0
+#define RTE_UART1_RS485_DE_MUX 6
+#define RTE_UART1_RS485_DE_PAD 4
+#elif (RTE_UART1_RS485_DE_PORT_ID == 1)
+#define RTE_UART1_RS485_DE_PIN 75
+#define RTE_UART1_RS485_DE_PORT 0
+#define RTE_UART1_RS485_DE_MUX 6
+#define RTE_UART1_RS485_DE_PAD 33
+#else
+#error "Invalid UART1_RS485_DE_PIN"
+#endif
+#else
+//Pintool data
+#define RTE_UART1_RS485_DE_PORT HP
+#if (UART1_DE_LOC == 29)
+#define RTE_UART1_RS485_DE_PIN UART1_RS485_DE_PIN
+#define RTE_UART1_RS485_DE_MUX 6
+#define RTE_UART1_RS485_DE_PAD 4
+#endif
+#if (UART1_DE_LOC == 30)
+#define RTE_UART1_RS485_DE_PIN (UART1_RS485_DE_PIN + GPIO_MAX_PIN)
+#define RTE_UART1_RS485_DE_MUX 6
+#define RTE_UART1_RS485_DE_PAD 33
+#endif
+//Pintool data
+#endif
+
+// UART1_RS485_EN Pin <0=>P0_12 <1=>P0_64
+#ifndef UART1_EN_LOC
+
+#define RTE_UART1_RS485_EN_PORT_ID 0
+#if (RTE_UART1_RS485_EN_PORT_ID == 0)
+#define RTE_UART1_RS485_EN_PIN 12
+#define RTE_UART1_RS485_EN_PORT 0
+#define RTE_UART1_RS485_EN_MUX 6
+#define RTE_UART1_RS485_EN_PAD 7
+#elif (RTE_UART1_RS485_EN_PORT_ID == 1)
+#define RTE_UART1_RS485_EN_PIN 64
+#define RTE_UART1_RS485_EN_PORT 0
+#define RTE_UART1_RS485_EN_MUX 6
+#define RTE_UART1_RS485_EN_PAD 22
+#else
+#error "Invalid UART1_RS485_EN_PIN"
+#endif
+#else
+//Pintool data
+#define RTE_UART1_RS485_EN_PORT HP
+#if (UART1_EN_LOC == 31)
+#define RTE_UART1_RS485_EN_PIN UART1_RS485_EN_PIN
+#define RTE_UART1_RS485_EN_MUX 6
+#define RTE_UART1_RS485_EN_PAD 7
+#endif
+#if (UART1_EN_LOC == 32)
+#define RTE_UART1_RS485_EN_PIN (UART1_RS485_EN_PIN + GPIO_MAX_PIN)
+#define RTE_UART1_RS485_EN_MUX 6
+#define RTE_UART1_RS485_EN_PAD 22
+#endif
+//Pintool data
+#endif
\ No newline at end of file
diff --git a/projects/bluetooth/sl_si91x_icm40627_3/config/pin_config.h b/projects/bluetooth/sl_si91x_icm40627_3/config/pin_config.h
new file mode 100644
index 0000000..5afb38c
--- /dev/null
+++ b/projects/bluetooth/sl_si91x_icm40627_3/config/pin_config.h
@@ -0,0 +1,219 @@
+#ifndef PIN_CONFIG_H
+#define PIN_CONFIG_H
+
+// $[USART0]
+// [USART0]$
+
+// $[UART1]
+// [UART1]$
+
+// $[ULP_UART]
+// [ULP_UART]$
+
+// $[I2C0]
+// [I2C0]$
+
+// $[I2C1]
+// [I2C1]$
+
+// $[ULP_I2C]
+// [ULP_I2C]$
+
+// $[SSI_MASTER]
+// [SSI_MASTER]$
+
+// $[SSI_SLAVE]
+// [SSI_SLAVE]$
+
+// $[ULP_SSI]
+// ULP_SSI MOSI_ on ULP_GPIO_1/GPIO_65
+#ifndef ULP_SSI_MOSI__PORT
+#define ULP_SSI_MOSI__PORT ULP
+#endif
+#ifndef ULP_SSI_MOSI__PIN
+#define ULP_SSI_MOSI__PIN 1
+#endif
+#ifndef ULP_SSI_MOSI_LOC
+#define ULP_SSI_MOSI_LOC 0
+#endif
+
+// ULP_SSI MISO_ on ULP_GPIO_2/GPIO_66
+#ifndef ULP_SSI_MISO__PORT
+#define ULP_SSI_MISO__PORT ULP
+#endif
+#ifndef ULP_SSI_MISO__PIN
+#define ULP_SSI_MISO__PIN 2
+#endif
+#ifndef ULP_SSI_MISO_LOC
+#define ULP_SSI_MISO_LOC 12
+#endif
+
+// ULP_SSI SCK_ on ULP_GPIO_8/GPIO_72
+#ifndef ULP_SSI_SCK__PORT
+#define ULP_SSI_SCK__PORT ULP
+#endif
+#ifndef ULP_SSI_SCK__PIN
+#define ULP_SSI_SCK__PIN 8
+#endif
+#ifndef ULP_SSI_SCK_LOC
+#define ULP_SSI_SCK_LOC 7
+#endif
+
+// ULP_SSI CS0_ on ULP_GPIO_10/GPIO_74
+#ifndef ULP_SSI_CS0__PORT
+#define ULP_SSI_CS0__PORT ULP
+#endif
+#ifndef ULP_SSI_CS0__PIN
+#define ULP_SSI_CS0__PIN 10
+#endif
+#ifndef ULP_SSI_CS0_LOC
+#define ULP_SSI_CS0_LOC 9
+#endif
+
+// [ULP_SSI]$
+
+// $[GSPI_MASTER]
+// [GSPI_MASTER]$
+
+// $[I2S0]
+// [I2S0]$
+
+// $[ULP_I2S]
+// [ULP_I2S]$
+
+// $[SCT]
+// [SCT]$
+
+// $[SIO]
+// [SIO]$
+
+// $[PWM]
+// [PWM]$
+
+// $[PWM_CH0]
+// [PWM_CH0]$
+
+// $[PWM_CH1]
+// [PWM_CH1]$
+
+// $[PWM_CH2]
+// [PWM_CH2]$
+
+// $[PWM_CH3]
+// [PWM_CH3]$
+
+// $[ADC_CH1]
+// [ADC_CH1]$
+
+// $[ADC_CH2]
+// [ADC_CH2]$
+
+// $[ADC_CH3]
+// [ADC_CH3]$
+
+// $[ADC_CH4]
+// [ADC_CH4]$
+
+// $[ADC_CH5]
+// [ADC_CH5]$
+
+// $[ADC_CH6]
+// [ADC_CH6]$
+
+// $[ADC_CH7]
+// [ADC_CH7]$
+
+// $[ADC_CH8]
+// [ADC_CH8]$
+
+// $[ADC_CH9]
+// [ADC_CH9]$
+
+// $[ADC_CH10]
+// [ADC_CH10]$
+
+// $[ADC_CH11]
+// [ADC_CH11]$
+
+// $[ADC_CH12]
+// [ADC_CH12]$
+
+// $[ADC_CH13]
+// [ADC_CH13]$
+
+// $[ADC_CH14]
+// [ADC_CH14]$
+
+// $[ADC_CH15]
+// [ADC_CH15]$
+
+// $[ADC_CH16]
+// [ADC_CH16]$
+
+// $[ADC_CH17]
+// [ADC_CH17]$
+
+// $[ADC_CH18]
+// [ADC_CH18]$
+
+// $[ADC_CH19]
+// [ADC_CH19]$
+
+// $[COMP1]
+// [COMP1]$
+
+// $[COMP2]
+// [COMP2]$
+
+// $[DAC0]
+// [DAC0]$
+
+// $[DAC1]
+// [DAC1]$
+
+// $[SYSRTC]
+// [SYSRTC]$
+
+// $[UULP_VBAT_GPIO]
+// [UULP_VBAT_GPIO]$
+
+// $[GPIO]
+// [GPIO]$
+
+// $[QEI]
+// [QEI]$
+
+// $[HSPI_SECONDARY]
+// [HSPI_SECONDARY]$
+
+// $[CUSTOM_PIN_NAME]
+#ifndef _PORT
+#define _PORT HP
+#endif
+#ifndef _PIN
+#define _PIN 6
+#endif
+
+// [CUSTOM_PIN_NAME]$
+
+#endif // PIN_CONFIG_H// $[SDC_CH1]
+// [SDC_CH1]$
+
+// $[SDC_CH2]
+// [SDC_CH2]$
+
+// $[SDC_CH3]
+// [SDC_CH3]$
+
+// $[SDC_CH4]
+// [SDC_CH4]$
+
+// $[OPAMP1]
+// [OPAMP1]$
+
+// $[OPAMP2]
+// [OPAMP2]$
+
+// $[OPAMP3]
+// [OPAMP3]$
+
diff --git a/projects/bluetooth/sl_si91x_icm40627_3/config/sl_board_configuration.h b/projects/bluetooth/sl_si91x_icm40627_3/config/sl_board_configuration.h
new file mode 100644
index 0000000..686f15e
--- /dev/null
+++ b/projects/bluetooth/sl_si91x_icm40627_3/config/sl_board_configuration.h
@@ -0,0 +1,23 @@
+/*******************************************************************************
+* @file sl_board_configuration.h
+* @brief
+*******************************************************************************
+* # License
+* Copyright 2023 Silicon Laboratories Inc. www.silabs.com
+*******************************************************************************
+*
+* The licensor of this software is Silicon Laboratories Inc. Your use of this
+* software is governed by the terms of Silicon Labs Master Software License
+* Agreement (MSLA) available at
+* www.silabs.com/about-us/legal/master-software-license-agreement. This
+* software is distributed to you in Source Code format and is governed by the
+* sections of the MSLA applicable to Source Code.
+*
+******************************************************************************/
+
+#pragma once
+
+#include
+
+#define DEFAULT_UART NULL
+#define DEFAULT_UART_PIN_CONFIG NULL
\ No newline at end of file
diff --git a/projects/bluetooth/sl_si91x_icm40627_3/config/sl_board_control.h b/projects/bluetooth/sl_si91x_icm40627_3/config/sl_board_control.h
new file mode 100644
index 0000000..de3850b
--- /dev/null
+++ b/projects/bluetooth/sl_si91x_icm40627_3/config/sl_board_control.h
@@ -0,0 +1,22 @@
+/*******************************************************************************
+* @file sl_board_control.h
+* @brief
+*******************************************************************************
+* # License
+* Copyright 2023 Silicon Laboratories Inc. www.silabs.com
+*******************************************************************************
+*
+* The licensor of this software is Silicon Laboratories Inc. Your use of this
+* software is governed by the terms of Silicon Labs Master Software License
+* Agreement (MSLA) available at
+* www.silabs.com/about-us/legal/master-software-license-agreement. This
+* software is distributed to you in Source Code format and is governed by the
+* sections of the MSLA applicable to Source Code.
+*
+******************************************************************************/
+
+#pragma once
+
+#include "sl_status.h"
+
+sl_status_t sl_board_enable_vcom(void);
\ No newline at end of file
diff --git a/projects/bluetooth/sl_si91x_icm40627_3/config/sl_core_config.h b/projects/bluetooth/sl_si91x_icm40627_3/config/sl_core_config.h
new file mode 100644
index 0000000..5b4725e
--- /dev/null
+++ b/projects/bluetooth/sl_si91x_icm40627_3/config/sl_core_config.h
@@ -0,0 +1,44 @@
+/***************************************************************************//**
+ * @file
+ * @brief sl_core Configuration
+ *******************************************************************************
+ * # License
+ * Copyright 2023 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef SL_CORE_CONFIG_H
+#define SL_CORE_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// Core Abstraction Configuration
+
+// Enables measurement of interrupt masking time for debugging purposes.
+// Default: 0
+#define SL_CORE_DEBUG_INTERRUPTS_MASKED_TIMING 0
+//
+
+// <<< end of configuration section >>>
+#endif // SL_CORE_CONFIG_H
\ No newline at end of file
diff --git a/projects/bluetooth/sl_si91x_icm40627_3/config/sl_gpio_board.h b/projects/bluetooth/sl_si91x_icm40627_3/config/sl_gpio_board.h
new file mode 100644
index 0000000..07191fe
--- /dev/null
+++ b/projects/bluetooth/sl_si91x_icm40627_3/config/sl_gpio_board.h
@@ -0,0 +1,409 @@
+/*******************************************************************************
+* @file sl_gpio_board.h
+* @brief sl gpio board specific configuration
+*******************************************************************************
+* # License
+* Copyright 2025 Silicon Laboratories Inc. www.silabs.com
+*******************************************************************************
+*
+* The licensor of this software is Silicon Laboratories Inc. Your use of this
+* software is governed by the terms of Silicon Labs Master Software License
+* Agreement (MSLA) available at
+* www.silabs.com/about-us/legal/master-software-license-agreement. This
+* software is distributed to you in Source Code format and is governed by the
+* sections of the MSLA applicable to Source Code.
+*
+******************************************************************************/
+
+#ifndef __SL_SI91X_GPIO_BOARD_H__
+#define __SL_SI91X_GPIO_BOARD_H__
+/**
+ * @defgroup Board_Specific_Driver Board specific drivers and support functions
+ * @{
+ */
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**
+ * @defgroup Board_Drivers BOARD: Common board components used with board drivers
+ * @{
+ */
+#include "em_device.h"
+
+#define SL_SI91X_GPIO_6_PORT RTE_GPIO_6_PORT
+#define SL_SI91X_GPIO_6_PAD RTE_GPIO_6_PAD
+#define SL_SI91X_GPIO_6_PIN RTE_GPIO_6_PIN
+#define SL_SI91X_GPIO_6_MODE RTE_GPIO_6_MODE
+
+#define SL_SI91X_GPIO_7_PORT RTE_GPIO_7_PORT
+#define SL_SI91X_GPIO_7_PAD RTE_GPIO_7_PAD
+#define SL_SI91X_GPIO_7_PIN RTE_GPIO_7_PIN
+#define SL_SI91X_GPIO_7_MODE RTE_GPIO_7_MODE
+
+#define SL_SI91X_GPIO_8_PORT RTE_GPIO_8_PORT
+#define SL_SI91X_GPIO_8_PAD RTE_GPIO_8_PAD
+#define SL_SI91X_GPIO_8_PIN RTE_GPIO_8_PIN
+#define SL_SI91X_GPIO_8_MODE RTE_GPIO_8_MODE
+
+#define SL_SI91X_GPIO_9_PORT RTE_GPIO_9_PORT
+#define SL_SI91X_GPIO_9_PAD RTE_GPIO_9_PAD
+#define SL_SI91X_GPIO_9_PIN RTE_GPIO_9_PIN
+#define SL_SI91X_GPIO_9_MODE RTE_GPIO_9_MODE
+
+#define SL_SI91X_GPIO_10_PORT RTE_GPIO_10_PORT
+#define SL_SI91X_GPIO_10_PAD RTE_GPIO_10_PAD
+#define SL_SI91X_GPIO_10_PIN RTE_GPIO_10_PIN
+#define SL_SI91X_GPIO_10_MODE RTE_GPIO_10_MODE
+
+#define SL_SI91X_GPIO_11_PORT RTE_GPIO_11_PORT
+#define SL_SI91X_GPIO_11_PAD RTE_GPIO_11_PAD
+#define SL_SI91X_GPIO_11_PIN RTE_GPIO_11_PIN
+#define SL_SI91X_GPIO_11_MODE RTE_GPIO_11_MODE
+
+#define SL_SI91X_GPIO_12_PORT RTE_GPIO_12_PORT
+#define SL_SI91X_GPIO_12_PAD RTE_GPIO_12_PAD
+#define SL_SI91X_GPIO_12_PIN RTE_GPIO_12_PIN
+#define SL_SI91X_GPIO_12_MODE RTE_GPIO_12_MODE
+
+#define SL_SI91X_GPIO_15_PORT RTE_GPIO_15_PORT
+#define SL_SI91X_GPIO_15_PAD RTE_GPIO_15_PAD
+#define SL_SI91X_GPIO_15_PIN RTE_GPIO_15_PIN
+#define SL_SI91X_GPIO_15_MODE RTE_GPIO_15_MODE
+
+#define SL_SI91X_GPIO_25_PORT RTE_GPIO_25_PORT
+#define SL_SI91X_GPIO_25_PIN RTE_GPIO_25_PIN
+#define SL_SI91X_GPIO_25_MODE RTE_GPIO_25_MODE
+
+#define SL_SI91X_GPIO_26_PORT RTE_GPIO_26_PORT
+#define SL_SI91X_GPIO_26_PIN RTE_GPIO_26_PIN
+#define SL_SI91X_GPIO_26_MODE RTE_GPIO_26_MODE
+
+#define SL_SI91X_GPIO_27_PORT RTE_GPIO_27_PORT
+#define SL_SI91X_GPIO_27_PIN RTE_GPIO_27_PIN
+#define SL_SI91X_GPIO_27_MODE RTE_GPIO_27_MODE
+
+#define SL_SI91X_GPIO_28_PORT RTE_GPIO_28_PORT
+#define SL_SI91X_GPIO_28_PIN RTE_GPIO_28_PIN
+#define SL_SI91X_GPIO_28_MODE RTE_GPIO_28_MODE
+
+#define SL_SI91X_GPIO_29_PORT RTE_GPIO_29_PORT
+#define SL_SI91X_GPIO_29_PIN RTE_GPIO_29_PIN
+#define SL_SI91X_GPIO_29_MODE RTE_GPIO_29_MODE
+
+#define SL_SI91X_GPIO_30_PORT RTE_GPIO_30_PORT
+#define SL_SI91X_GPIO_30_PIN RTE_GPIO_30_PIN
+#define SL_SI91X_GPIO_30_MODE RTE_GPIO_30_MODE
+
+#define SL_SI91X_GPIO_31_PORT RTE_GPIO_31_PORT
+#define SL_SI91X_GPIO_31_PAD RTE_GPIO_31_PAD
+#define SL_SI91X_GPIO_31_PIN RTE_GPIO_31_PIN
+#define SL_SI91X_GPIO_31_MODE RTE_GPIO_31_MODE
+
+#define SL_SI91X_GPIO_32_PORT RTE_GPIO_32_PORT
+#define SL_SI91X_GPIO_32_PAD RTE_GPIO_32_PAD
+#define SL_SI91X_GPIO_32_PIN RTE_GPIO_32_PIN
+#define SL_SI91X_GPIO_32_MODE RTE_GPIO_32_MODE
+
+#define SL_SI91X_GPIO_33_PORT RTE_GPIO_33_PORT
+#define SL_SI91X_GPIO_33_PAD RTE_GPIO_33_PAD
+#define SL_SI91X_GPIO_33_PIN RTE_GPIO_33_PIN
+#define SL_SI91X_GPIO_33_MODE RTE_GPIO_33_MODE
+
+#define SL_SI91X_GPIO_34_PORT RTE_GPIO_34_PORT
+#define SL_SI91X_GPIO_34_PAD RTE_GPIO_34_PAD
+#define SL_SI91X_GPIO_34_PIN RTE_GPIO_34_PIN
+#define SL_SI91X_GPIO_34_MODE RTE_GPIO_34_MODE
+
+#define SL_SI91X_GPIO_46_PORT RTE_GPIO_46_PORT
+#define SL_SI91X_GPIO_46_PAD RTE_GPIO_46_PAD
+#define SL_SI91X_GPIO_46_PIN RTE_GPIO_46_PIN
+#define SL_SI91X_GPIO_46_MODE RTE_GPIO_46_MODE
+
+#define SL_SI91X_GPIO_47_PORT RTE_GPIO_47_PORT
+#define SL_SI91X_GPIO_47_PAD RTE_GPIO_47_PAD
+#define SL_SI91X_GPIO_47_PIN RTE_GPIO_47_PIN
+#define SL_SI91X_GPIO_47_MODE RTE_GPIO_47_MODE
+
+#define SL_SI91X_GPIO_48_PORT RTE_GPIO_48_PORT
+#define SL_SI91X_GPIO_48_PAD RTE_GPIO_48_PAD
+#define SL_SI91X_GPIO_48_PIN RTE_GPIO_48_PIN
+#define SL_SI91X_GPIO_48_MODE RTE_GPIO_48_MODE
+
+#define SL_SI91X_GPIO_49_PORT RTE_GPIO_49_PORT
+#define SL_SI91X_GPIO_49_PAD RTE_GPIO_49_PAD
+#define SL_SI91X_GPIO_49_PIN RTE_GPIO_49_PIN
+#define SL_SI91X_GPIO_49_MODE RTE_GPIO_49_MODE
+
+#define SL_SI91X_GPIO_50_PORT RTE_GPIO_50_PORT
+#define SL_SI91X_GPIO_50_PAD RTE_GPIO_50_PAD
+#define SL_SI91X_GPIO_50_PIN RTE_GPIO_50_PIN
+#define SL_SI91X_GPIO_50_MODE RTE_GPIO_50_MODE
+
+#define SL_SI91X_GPIO_51_PORT RTE_GPIO_51_PORT
+#define SL_SI91X_GPIO_51_PAD RTE_GPIO_51_PAD
+#define SL_SI91X_GPIO_51_PIN RTE_GPIO_51_PIN
+#define SL_SI91X_GPIO_51_MODE RTE_GPIO_51_MODE
+
+#define SL_SI91X_GPIO_52_PORT RTE_GPIO_52_PORT
+#define SL_SI91X_GPIO_52_PAD RTE_GPIO_52_PAD
+#define SL_SI91X_GPIO_52_PIN RTE_GPIO_52_PIN
+#define SL_SI91X_GPIO_52_MODE RTE_GPIO_52_MODE
+
+#define SL_SI91X_GPIO_53_PORT RTE_GPIO_53_PORT
+#define SL_SI91X_GPIO_53_PAD RTE_GPIO_53_PAD
+#define SL_SI91X_GPIO_53_PIN RTE_GPIO_53_PIN
+#define SL_SI91X_GPIO_53_MODE RTE_GPIO_53_MODE
+
+#define SL_SI91X_GPIO_54_PORT RTE_GPIO_54_PORT
+#define SL_SI91X_GPIO_54_PAD RTE_GPIO_54_PAD
+#define SL_SI91X_GPIO_54_PIN RTE_GPIO_54_PIN
+#define SL_SI91X_GPIO_54_MODE RTE_GPIO_54_MODE
+
+#define SL_SI91X_GPIO_55_PORT RTE_GPIO_55_PORT
+#define SL_SI91X_GPIO_55_PAD RTE_GPIO_55_PAD
+#define SL_SI91X_GPIO_55_PIN RTE_GPIO_55_PIN
+#define SL_SI91X_GPIO_55_MODE RTE_GPIO_55_MODE
+
+#define SL_SI91X_GPIO_56_PORT RTE_GPIO_56_PORT
+#define SL_SI91X_GPIO_56_PAD RTE_GPIO_56_PAD
+#define SL_SI91X_GPIO_56_PIN RTE_GPIO_56_PIN
+#define SL_SI91X_GPIO_56_MODE RTE_GPIO_56_MODE
+
+#define SL_SI91X_GPIO_57_PORT RTE_GPIO_57_PORT
+#define SL_SI91X_GPIO_57_PAD RTE_GPIO_57_PAD
+#define SL_SI91X_GPIO_57_PIN RTE_GPIO_57_PIN
+#define SL_SI91X_GPIO_57_MODE RTE_GPIO_57_MODE
+
+#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
+#define SL_SI91X_ULP_GPIO_0_PORT_ID 1
+#else
+#define SL_SI91X_ULP_GPIO_0_PORT_ID 0
+#endif
+
+#if (SL_SI91X_ULP_GPIO_0_PORT_ID == 0)
+#define SL_SI91X_ULP_GPIO_0_PORT RTE_ULP_GPIO_0_PORT
+#define SL_SI91X_ULP_GPIO_0_PAD RTE_ULP_GPIO_0_PAD
+#define SL_SI91X_ULP_GPIO_0_PIN RTE_ULP_GPIO_0_PIN
+#define SL_SI91X_ULP_GPIO_0_MODE RTE_ULP_GPIO_0_MODE
+#elif (SL_SI91X_ULP_GPIO_0_PORT_ID == 1)
+#define SL_SI91X_ULP_GPIO_0_PORT RTE_ULP_GPIO_0_PORT
+#define SL_SI91X_ULP_GPIO_0_PIN RTE_ULP_GPIO_0_PIN
+#define SL_SI91X_ULP_GPIO_0_MODE RTE_ULP_GPIO_0_MODE
+#else
+#error "Invalid SL_SI91X_ULP_GPIO_0_PIN Pin Configuration!"
+#endif
+
+#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
+#define SL_SI91X_ULP_GPIO_1_PORT_ID 1
+#else
+#define SL_SI91X_ULP_GPIO_1_PORT_ID 0
+#endif
+
+#if (SL_SI91X_ULP_GPIO_1_PORT_ID == 0)
+#define SL_SI91X_ULP_GPIO_1_PORT RTE_ULP_GPIO_1_PORT
+#define SL_SI91X_ULP_GPIO_1_PAD RTE_ULP_GPIO_1_PAD
+#define SL_SI91X_ULP_GPIO_1_PIN RTE_ULP_GPIO_1_PIN
+#define SL_SI91X_ULP_GPIO_1_MODE RTE_ULP_GPIO_1_MODE
+#elif (SL_SI91X_ULP_GPIO_1_PORT_ID == 1)
+#define SL_SI91X_ULP_GPIO_1_PORT RTE_ULP_GPIO_1_PORT
+#define SL_SI91X_ULP_GPIO_1_PIN RTE_ULP_GPIO_1_PIN
+#define SL_SI91X_ULP_GPIO_1_MODE RTE_ULP_GPIO_1_MODE
+#else
+#error "Invalid SL_SI91X_ULP_GPIO_1_PIN Pin Configuration!"
+#endif
+
+#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
+#define SL_SI91X_ULP_GPIO_2_PORT_ID 1
+#else
+#define SL_SI91X_ULP_GPIO_2_PORT_ID 0
+#endif
+
+#if (SL_SI91X_ULP_GPIO_2_PORT_ID == 0)
+#define SL_SI91X_ULP_GPIO_2_PORT RTE_ULP_GPIO_2_PORT
+#define SL_SI91X_ULP_GPIO_2_PAD RTE_ULP_GPIO_2_PAD
+#define SL_SI91X_ULP_GPIO_2_PIN RTE_ULP_GPIO_2_PIN
+#define SL_SI91X_ULP_GPIO_2_MODE RTE_ULP_GPIO_2_MODE
+#elif (SL_SI91X_ULP_GPIO_2_PORT_ID == 1)
+#define SL_SI91X_ULP_GPIO_2_PORT RTE_ULP_GPIO_2_PORT
+#define SL_SI91X_ULP_GPIO_2_PIN RTE_ULP_GPIO_2_PIN
+#define SL_SI91X_ULP_GPIO_2_MODE RTE_ULP_GPIO_2_MODE
+#else
+#error "Invalid SL_SI91X_ULP_GPIO_2_PIN Pin Configuration!"
+#endif
+
+#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
+#define SL_SI91X_ULP_GPIO_4_PORT_ID 1
+#else
+#define SL_SI91X_ULP_GPIO_4_PORT_ID 0
+#endif
+
+#if (SL_SI91X_ULP_GPIO_4_PORT_ID == 0)
+#define SL_SI91X_ULP_GPIO_4_PORT RTE_ULP_GPIO_4_PORT
+#define SL_SI91X_ULP_GPIO_4_PAD RTE_ULP_GPIO_4_PAD
+#define SL_SI91X_ULP_GPIO_4_PIN RTE_ULP_GPIO_4_PIN
+#define SL_SI91X_ULP_GPIO_4_MODE RTE_ULP_GPIO_4_MODE
+#elif (SL_SI91X_ULP_GPIO_4_PORT_ID == 1)
+#define SL_SI91X_ULP_GPIO_4_PORT RTE_ULP_GPIO_4_PORT
+#define SL_SI91X_ULP_GPIO_4_PIN RTE_ULP_GPIO_4_PIN
+#define SL_SI91X_ULP_GPIO_4_MODE RTE_ULP_GPIO_4_MODE
+#else
+#error "Invalid SL_SI91X_ULP_GPIO_4_PIN Pin Configuration!"
+#endif
+
+#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
+#define SL_SI91X_ULP_GPIO_5_PORT_ID 1
+#else
+#define SL_SI91X_ULP_GPIO_5_PORT_ID 0
+#endif
+
+#if (SL_SI91X_ULP_GPIO_5_PORT_ID == 0)
+#define SL_SI91X_ULP_GPIO_5_PORT RTE_ULP_GPIO_5_PORT
+#define SL_SI91X_ULP_GPIO_5_PAD RTE_ULP_GPIO_5_PAD
+#define SL_SI91X_ULP_GPIO_5_PIN RTE_ULP_GPIO_5_PIN
+#define SL_SI91X_ULP_GPIO_5_MODE RTE_ULP_GPIO_5_MODE
+#elif (SL_SI91X_ULP_GPIO_5_PORT_ID == 1)
+#define SL_SI91X_ULP_GPIO_5_PORT RTE_ULP_GPIO_5_PORT
+#define SL_SI91X_ULP_GPIO_5_PIN RTE_ULP_GPIO_5_PIN
+#define SL_SI91X_ULP_GPIO_5_MODE RTE_ULP_GPIO_5_MODE
+#else
+#error "Invalid SL_SI91X_ULP_GPIO_5_PIN Pin Configuration!"
+#endif
+
+#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
+#define SL_SI91X_ULP_GPIO_6_PORT_ID 1
+#else
+#define SL_SI91X_ULP_GPIO_6_PORT_ID 0
+#endif
+
+#if (SL_SI91X_ULP_GPIO_6_PORT_ID == 0)
+#define SL_SI91X_ULP_GPIO_6_PORT RTE_ULP_GPIO_6_PORT
+#define SL_SI91X_ULP_GPIO_6_PAD RTE_ULP_GPIO_6_PAD
+#define SL_SI91X_ULP_GPIO_6_PIN RTE_ULP_GPIO_6_PIN
+#define SL_SI91X_ULP_GPIO_6_MODE RTE_ULP_GPIO_6_MODE
+#elif (SL_SI91X_ULP_GPIO_6_PORT_ID == 1)
+#define SL_SI91X_ULP_GPIO_6_PORT RTE_ULP_GPIO_6_PORT
+#define SL_SI91X_ULP_GPIO_6_PIN RTE_ULP_GPIO_6_PIN
+#define SL_SI91X_ULP_GPIO_6_MODE RTE_ULP_GPIO_6_MODE
+#else
+#error "Invalid SL_SI91X_ULP_GPIO_6_PIN Pin Configuration!"
+#endif
+
+#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
+#define SL_SI91X_ULP_GPIO_7_PORT_ID 1
+#else
+#define SL_SI91X_ULP_GPIO_7_PORT_ID 0
+#endif
+
+#if (SL_SI91X_ULP_GPIO_7_PORT_ID == 0)
+#define SL_SI91X_ULP_GPIO_7_PORT RTE_ULP_GPIO_7_PORT
+#define SL_SI91X_ULP_GPIO_7_PAD RTE_ULP_GPIO_7_PAD
+#define SL_SI91X_ULP_GPIO_7_PIN RTE_ULP_GPIO_7_PIN
+#define SL_SI91X_ULP_GPIO_7_MODE RTE_ULP_GPIO_7_MODE
+#elif (SL_SI91X_ULP_GPIO_7_PORT_ID == 1)
+#define SL_SI91X_ULP_GPIO_7_PORT RTE_ULP_GPIO_7_PORT
+#define SL_SI91X_ULP_GPIO_7_PIN RTE_ULP_GPIO_7_PIN
+#define SL_SI91X_ULP_GPIO_7_MODE RTE_ULP_GPIO_7_MODE
+#else
+#error "Invalid SL_SI91X_ULP_GPIO_7_PIN Pin Configuration!"
+#endif
+
+#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
+#define SL_SI91X_ULP_GPIO_8_PORT_ID 1
+#else
+#define SL_SI91X_ULP_GPIO_8_PORT_ID 0
+#endif
+
+#if (SL_SI91X_ULP_GPIO_8_PORT_ID == 0)
+#define SL_SI91X_ULP_GPIO_8_PORT RTE_ULP_GPIO_8_PORT
+#define SL_SI91X_ULP_GPIO_8_PAD RTE_ULP_GPIO_8_PAD
+#define SL_SI91X_ULP_GPIO_8_PIN RTE_ULP_GPIO_8_PIN
+#define SL_SI91X_ULP_GPIO_8_MODE RTE_ULP_GPIO_8_MODE
+#elif (SL_SI91X_ULP_GPIO_8_PORT_ID == 1)
+#define SL_SI91X_ULP_GPIO_8_PORT RTE_ULP_GPIO_8_PORT
+#define SL_SI91X_ULP_GPIO_8_PIN RTE_ULP_GPIO_8_PIN
+#define SL_SI91X_ULP_GPIO_8_MODE RTE_ULP_GPIO_8_MODE
+#else
+#error "Invalid SL_SI91X_ULP_GPIO_8_PIN Pin Configuration!"
+#endif
+
+#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
+#define SL_SI91X_ULP_GPIO_9_PORT_ID 1
+#else
+#define SL_SI91X_ULP_GPIO_9_PORT_ID 0
+#endif
+
+#if (SL_SI91X_ULP_GPIO_9_PORT_ID == 0)
+#define SL_SI91X_ULP_GPIO_9_PORT RTE_ULP_GPIO_9_PORT
+#define SL_SI91X_ULP_GPIO_9_PAD RTE_ULP_GPIO_9_PAD
+#define SL_SI91X_ULP_GPIO_9_PIN RTE_ULP_GPIO_9_PIN
+#define SL_SI91X_ULP_GPIO_9_MODE RTE_ULP_GPIO_9_MODE
+#elif (SL_SI91X_ULP_GPIO_9_PORT_ID == 1)
+#define SL_SI91X_ULP_GPIO_9_PORT RTE_ULP_GPIO_9_PORT
+#define SL_SI91X_ULP_GPIO_9_PIN RTE_ULP_GPIO_9_PIN
+#define SL_SI91X_ULP_GPIO_9_MODE RTE_ULP_GPIO_9_MODE
+#else
+#error "Invalid SL_SI91X_ULP_GPIO_9_PIN Pin Configuration!"
+#endif
+
+#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
+#define SL_SI91X_ULP_GPIO_10_PORT_ID 1
+#else
+#define SL_SI91X_ULP_GPIO_10_PORT_ID 0
+#endif
+
+#if (SL_SI91X_ULP_GPIO_10_PORT_ID == 0)
+#define SL_SI91X_ULP_GPIO_10_PORT RTE_ULP_GPIO_10_PORT
+#define SL_SI91X_ULP_GPIO_10_PAD RTE_ULP_GPIO_10_PAD
+#define SL_SI91X_ULP_GPIO_10_PIN RTE_ULP_GPIO_10_PIN
+#define SL_SI91X_ULP_GPIO_10_MODE RTE_ULP_GPIO_10_MODE
+#elif (SL_SI91X_ULP_GPIO_10_PORT_ID == 1)
+#define SL_SI91X_ULP_GPIO_10_PORT RTE_ULP_GPIO_10_PORT
+#define SL_SI91X_ULP_GPIO_10_PIN RTE_ULP_GPIO_10_PIN
+#define SL_SI91X_ULP_GPIO_10_MODE RTE_ULP_GPIO_10_MODE
+#else
+#error "Invalid SL_SI91X_ULP_GPIO_10_PIN Pin Configuration!"
+#endif
+
+#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
+#define SL_SI91X_ULP_GPIO_11_PORT_ID 1
+#else
+#define SL_SI91X_ULP_GPIO_11_PORT_ID 0
+#endif
+
+#if (SL_SI91X_ULP_GPIO_11_PORT_ID == 0)
+#define SL_SI91X_ULP_GPIO_11_PORT RTE_ULP_GPIO_11_PORT
+#define SL_SI91X_ULP_GPIO_11_PAD RTE_ULP_GPIO_11_PAD
+#define SL_SI91X_ULP_GPIO_11_PIN RTE_ULP_GPIO_11_PIN
+#define SL_SI91X_ULP_GPIO_11_MODE RTE_ULP_GPIO_11_MODE
+#elif (SL_SI91X_ULP_GPIO_11_PORT_ID == 1)
+#define SL_SI91X_ULP_GPIO_11_PORT RTE_ULP_GPIO_11_PORT
+#define SL_SI91X_ULP_GPIO_11_PIN RTE_ULP_GPIO_11_PIN
+#define SL_SI91X_ULP_GPIO_11_MODE RTE_ULP_GPIO_11_MODE
+#else
+#error "Invalid SL_SI91X_ULP_GPIO_11_PIN Pin Configuration!"
+#endif
+
+#define SL_SI91X_UULP_GPIO_0_PORT RTE_UULP_GPIO_0_PORT
+#define SL_SI91X_UULP_GPIO_0_PIN RTE_UULP_GPIO_0_PIN
+#define SL_SI91X_UULP_GPIO_0_MODE RTE_UULP_GPIO_0_MODE
+
+#define SL_SI91X_UULP_GPIO_1_PORT RTE_UULP_GPIO_1_PORT
+#define SL_SI91X_UULP_GPIO_1_PIN RTE_UULP_GPIO_1_PIN
+#define SL_SI91X_UULP_GPIO_1_MODE RTE_UULP_GPIO_1_MODE
+
+#define SL_SI91X_UULP_GPIO_2_PORT RTE_UULP_GPIO_2_PORT
+#define SL_SI91X_UULP_GPIO_2_PIN RTE_UULP_GPIO_2_PIN
+#define SL_SI91X_UULP_GPIO_2_MODE RTE_UULP_GPIO_2_MODE
+
+#define SL_SI91X_UULP_GPIO_3_PORT RTE_UULP_GPIO_3_PORT
+#define SL_SI91X_UULP_GPIO_3_PIN RTE_UULP_GPIO_3_PIN
+#define SL_SI91X_UULP_GPIO_3_MODE RTE_UULP_GPIO_3_MODE
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SL_SI91X_GPIO_BOARD_H__*/
+
+/* @} end of Board_Drivers */
+/* @} end of Board_Specific_Driver */
\ No newline at end of file
diff --git a/projects/bluetooth/sl_si91x_icm40627_3/config/sl_si91x_dma_config.h b/projects/bluetooth/sl_si91x_icm40627_3/config/sl_si91x_dma_config.h
new file mode 100644
index 0000000..f712c8c
--- /dev/null
+++ b/projects/bluetooth/sl_si91x_icm40627_3/config/sl_si91x_dma_config.h
@@ -0,0 +1,52 @@
+/***************************************************************************/ /**
+ * @file
+ * @brief SL USART Config.
+ *******************************************************************************
+ * # License
+ * Copyright 2023 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef SL_SI91X_DMA_CONFIG_H
+#define SL_SI91X_DMA_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// DMA instance 0 channel count <1-32>
+// Default: 32
+#define SL_DMA0_CHANNEL_COUNT 32
+
+// ULP DMA instance channel count <1-12>
+// Default: 12
+#define SL_ULP_DMA_CHANNEL_COUNT 12
+
+// <<< end of configuration section >>>
+
+#ifdef __cplusplus
+}
+#endif
+#endif //SL_SI91X_DMA_CONFIG_H
\ No newline at end of file
diff --git a/projects/bluetooth/sl_si91x_icm40627_3/config/sl_si91x_icm40627_config.h b/projects/bluetooth/sl_si91x_icm40627_3/config/sl_si91x_icm40627_config.h
new file mode 100644
index 0000000..74aab19
--- /dev/null
+++ b/projects/bluetooth/sl_si91x_icm40627_3/config/sl_si91x_icm40627_config.h
@@ -0,0 +1,106 @@
+/***************************************************************************//**
+ * @file sl_si91x_icm40627_config.h
+ * * @brief SSI Master/Slave API configuration
+ * *******************************************************************************
+ * * # License
+ * * Copyright 2023 Silicon Laboratories Inc. www.silabs.com
+ * *******************************************************************************
+ * *
+ * * SPDX-License-Identifier: Zlib
+ * *
+ * * The licensor of this software is Silicon Laboratories Inc.
+ * *
+ * * This software is provided 'as-is', without any express or implied
+ * * warranty. In no event will the authors be held liable for any damages
+ * * arising from the use of this software.
+ * *
+ * * Permission is granted to anyone to use this software for any purpose,
+ * * including commercial applications, and to alter it and redistribute it
+ * * freely, subject to the following restrictions:
+ * *
+ * * 1. The origin of this software must not be misrepresented; you must not
+ * * claim that you wrote the original software. If you use this software
+ * * in a product, an acknowledgment in the product documentation would be
+ * * appreciated but is not required.
+ * * 2. Altered source versions must be plainly marked as such, and must not be
+ * * misrepresented as being the original software.
+ * * 3. This notice may not be removed or altered from any source distribution.
+ * *
+ * ******************************************************************************/
+
+#ifndef SL_SI91X_ICM40627_CONFIG_H
+#define SL_SI91X_ICM40627_CONFIG_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+// <<< sl:start pin_tool >>>
+// SL_SI91X_ICM40627
+// $[ULP_SSI_SL_SI91X_ICM40627]
+#ifndef SL_SI91X_ICM40627_PERIPHERAL
+#define SL_SI91X_ICM40627_PERIPHERAL ULP_SSI
+#endif
+
+// ULP_SSI MOSI_ on ULP_GPIO_1/GPIO_65
+#ifndef SL_SI91X_ICM40627_MOSI__PORT
+#define SL_SI91X_ICM40627_MOSI__PORT ULP
+#endif
+#ifndef SL_SI91X_ICM40627_MOSI__PIN
+#define SL_SI91X_ICM40627_MOSI__PIN 1
+#endif
+#ifndef SL_SI91X_ICM40627_MOSI_LOC
+#define SL_SI91X_ICM40627_MOSI_LOC 0
+#endif
+
+// ULP_SSI MISO_ on ULP_GPIO_2/GPIO_66
+#ifndef SL_SI91X_ICM40627_MISO__PORT
+#define SL_SI91X_ICM40627_MISO__PORT ULP
+#endif
+#ifndef SL_SI91X_ICM40627_MISO__PIN
+#define SL_SI91X_ICM40627_MISO__PIN 2
+#endif
+#ifndef SL_SI91X_ICM40627_MISO_LOC
+#define SL_SI91X_ICM40627_MISO_LOC 12
+#endif
+
+// ULP_SSI SCK_ on ULP_GPIO_8/GPIO_72
+#ifndef SL_SI91X_ICM40627_SCK__PORT
+#define SL_SI91X_ICM40627_SCK__PORT ULP
+#endif
+#ifndef SL_SI91X_ICM40627_SCK__PIN
+#define SL_SI91X_ICM40627_SCK__PIN 8
+#endif
+#ifndef SL_SI91X_ICM40627_SCK_LOC
+#define SL_SI91X_ICM40627_SCK_LOC 7
+#endif
+
+// ULP_SSI CS0_ on ULP_GPIO_10/GPIO_74
+#ifndef SL_SI91X_ICM40627_CS0__PORT
+#define SL_SI91X_ICM40627_CS0__PORT ULP
+#endif
+#ifndef SL_SI91X_ICM40627_CS0__PIN
+#define SL_SI91X_ICM40627_CS0__PIN 10
+#endif
+#ifndef SL_SI91X_ICM40627_CS0_LOC
+#define SL_SI91X_ICM40627_CS0_LOC 9
+#endif
+// [ULP_SSI_SL_SI91X_ICM40627]$
+
+// SL_SI91X_IMU_ALS_INT
+// $[GPIO_SL_SI91X_IMU_ALS_INT]
+#ifndef SL_SI91X_IMU_ALS_INT_PORT
+#define SL_SI91X_IMU_ALS_INT_PORT UULP_VBAT
+#endif
+#ifndef SL_SI91X_IMU_ALS_INT_PIN
+#define SL_SI91X_IMU_ALS_INT_PIN 3
+#endif
+// [GPIO_SL_SI91X_IMU_ALS_INT]$
+
+// <<< sl:end pin_tool >>>
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* SL_SI91X_ICM40627_CONFIG_H */
diff --git a/projects/bluetooth/sl_si91x_icm40627_3/config/sl_si91x_ssi_ulp_primary_common_config.h b/projects/bluetooth/sl_si91x_icm40627_3/config/sl_si91x_ssi_ulp_primary_common_config.h
new file mode 100644
index 0000000..4ae52f9
--- /dev/null
+++ b/projects/bluetooth/sl_si91x_icm40627_3/config/sl_si91x_ssi_ulp_primary_common_config.h
@@ -0,0 +1,59 @@
+/***************************************************************************/ /**
+ * @file sl_si91x_ssi_ulp_primary_common_config.h
+ * @brief SL SI91X SSI ULP Primary Common Config.
+ *******************************************************************************
+ * # License
+ * Copyright 2024 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef SL_SI91X_SSI_ULP_PRIMARY_COMMON_CONFIG_H
+#define SL_SI91X_SSI_ULP_PRIMARY_COMMON_CONFIG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// <<< Use Configuration Wizard in Context Menu >>>
+// SSI ULP Primary(ULP_Master) DMA Configuration
+
+// Default: 0
+#define SL_SSI_ULP_PRIMARY_DMA_CONFIG_ENABLE 1
+
+// TX FIFO Threshold <0-15>
+// Default: 0
+#define SL_SSI_ULP_PRIMARY_TX_FIFO_THRESHOLD 0
+
+// RX FIFO Threshold <0-15>
+// Default: 0
+#define SL_SSI_ULP_PRIMARY_RX_FIFO_THRESHOLD 0
+//
+
+// <<< end of configuration section >>>
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // SL_SI91X_SSI_ULP_PRIMARY_COMMON_CONFIG_H
\ No newline at end of file
diff --git a/projects/bluetooth/sl_si91x_icm40627_3/config/sl_si91x_ssi_ulp_primary_config.h b/projects/bluetooth/sl_si91x_icm40627_3/config/sl_si91x_ssi_ulp_primary_config.h
new file mode 100644
index 0000000..6685f87
--- /dev/null
+++ b/projects/bluetooth/sl_si91x_icm40627_3/config/sl_si91x_ssi_ulp_primary_config.h
@@ -0,0 +1,79 @@
+/***************************************************************************/
+/**
+ * @file sl_si91x_ssi_ulp_primary_config.h
+ * @brief SL SI91X Ulp_Primary Config.
+ *******************************************************************************
+ * # License
+ * Copyright 2024 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef SL_SI91X_SSI_ULP_PRIMARY_CONFIG_H
+#define SL_SI91X_SSI_ULP_PRIMARY_CONFIG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "sl_si91x_ssi.h"
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// SSI ULP Primary(ULP_Master) Configuration
+// Default: 1
+#define SSI_ULP_PRIMARY_UC 1
+
+// Frame Format
+// Mode 0
+// Mode 1
+// Mode 2
+// Mode 3
+// Texas Instrument
+// National Semiconductor Microwire
+// Selection of the SSI Master Mode.
+#define SL_SSI_ULP_PRIMARY_CLOCK_MODE SL_SSI_PERIPHERAL_CPOL0_CPHA0
+
+// Bit Rate (Bits/Second) <500000-5000000>
+// Default: 5000000
+#define SL_SSI_ULP_PRIMARY_BAUD 5000000 // SSI Speed ; Max is 5000000
+
+#define SL_SSI_ULP_PRIMARY_TRANSFER_MODE 0 // SSI ULP Primary is not NA
+
+// Data Width <4-16>
+// Default: 8
+#define SL_SSI_ULP_PRIMARY_BIT_WIDTH 8
+
+#define SL_SSI_ULP_PRIMARY_DEVICE_MODE SL_SSI_ULP_PRIMARY_ACTIVE
+
+// Rx Sample Delay <0-63>
+// Default: 0
+#define SL_SSI_ULP_PRIMARY_RECEIVE_SAMPLE_DELAY 0
+
+//
+// <<< end of configuration section >>>
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
\ No newline at end of file
diff --git a/projects/bluetooth/sl_si91x_icm40627_3/config/sl_si91x_stack_size_config.h b/projects/bluetooth/sl_si91x_icm40627_3/config/sl_si91x_stack_size_config.h
new file mode 100644
index 0000000..1979a8c
--- /dev/null
+++ b/projects/bluetooth/sl_si91x_icm40627_3/config/sl_si91x_stack_size_config.h
@@ -0,0 +1,35 @@
+/*******************************************************************************
+* @file sl_si91x_stack_size_config.h
+* @brief
+*******************************************************************************
+* # License
+* Copyright 2023 Silicon Laboratories Inc. www.silabs.com
+*******************************************************************************
+*
+* The licensor of this software is Silicon Laboratories Inc. Your use of this
+* software is governed by the terms of Silicon Labs Master Software License
+* Agreement (MSLA) available at
+* www.silabs.com/about-us/legal/master-software-license-agreement. This
+* software is distributed to you in Source Code format and is governed by the
+* sections of the MSLA applicable to Source Code.
+*
+******************************************************************************/
+
+#ifndef __SL_SI91X_STACK_SIZE_CONFIG_H_
+#define __SL_SI91X_STACK_SIZE_CONFIG_H_
+
+// <<< Use Configuration Wizard in Context Menu >>>
+// Memory configuration
+
+// Stack size for the application.
+// Default: 12288
+// The stack size configured here will be used by the stack that the
+// application uses when coming out of a reset.
+#ifndef SL_STACK_SIZE
+#define SL_STACK_SIZE 12288
+#endif
+
+//
+// <<< end of configuration section >>>
+
+#endif // __SL_SI91X_STACK_SIZE_CONFIG_H_
\ No newline at end of file
diff --git a/projects/bluetooth/sl_si91x_icm40627_3/config/sl_sleeptimer_config.h b/projects/bluetooth/sl_si91x_icm40627_3/config/sl_sleeptimer_config.h
new file mode 100644
index 0000000..bba646d
--- /dev/null
+++ b/projects/bluetooth/sl_si91x_icm40627_3/config/sl_sleeptimer_config.h
@@ -0,0 +1,82 @@
+/***************************************************************************//**
+ * @file
+ * @brief Sleep Timer configuration file.
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#ifndef SL_SLEEPTIMER_CONFIG_H
+#define SL_SLEEPTIMER_CONFIG_H
+
+#define SL_SLEEPTIMER_PERIPHERAL_DEFAULT 0
+#define SL_SLEEPTIMER_PERIPHERAL_RTCC 1
+#define SL_SLEEPTIMER_PERIPHERAL_PRORTC 2
+#define SL_SLEEPTIMER_PERIPHERAL_RTC 3
+#define SL_SLEEPTIMER_PERIPHERAL_SYSRTC 4
+#define SL_SLEEPTIMER_PERIPHERAL_BURTC 5
+#define SL_SLEEPTIMER_PERIPHERAL_WTIMER 6
+#define SL_SLEEPTIMER_PERIPHERAL_TIMER 7
+
+// Timer Peripheral Used by Sleeptimer
+// Default (auto select)
+// RTCC
+// Radio internal RTC (PRORTC)
+// RTC
+// SYSRTC
+// Back-Up RTC (BURTC)
+// WTIMER
+// TIMER
+// Selection of the Timer Peripheral Used by the Sleeptimer
+#define SL_SLEEPTIMER_PERIPHERAL SL_SLEEPTIMER_PERIPHERAL_DEFAULT
+
+// TIMER/WTIMER Instance Used by Sleeptimer (not applicable for other peripherals)
+// Make sure TIMER instance size is 32bits. Check datasheet for 32bits TIMERs.
+// Default: 0
+#define SL_SLEEPTIMER_TIMER_INSTANCE 0
+
+// Enable wallclock functionality
+// Enable or disable wallclock functionalities (get_time, get_date, etc).
+// Default: 0
+#define SL_SLEEPTIMER_WALLCLOCK_CONFIG 0
+
+// Timer frequency divider (not applicable for WTIMER/TIMER)
+// WTIMER/TIMER peripherals are always prescaled to 1024.
+// Default: 1
+#define SL_SLEEPTIMER_FREQ_DIVIDER 1
+
+// If Radio internal RTC (PRORTC) HAL is used, determines if it owns the IRQ handler. Enable, if no wireless stack is used.
+// Default: 0
+#define SL_SLEEPTIMER_PRORTC_HAL_OWNS_IRQ_HANDLER 0
+
+// Enable DEBUGRUN functionality on hardware RTC.
+// Default: 0
+#define SL_SLEEPTIMER_DEBUGRUN 0
+
+#endif /* SLEEPTIMER_CONFIG_H */
+
+// <<< end of configuration section >>>
\ No newline at end of file
diff --git a/projects/bluetooth/sl_si91x_icm40627_3/icm40627_example.c b/projects/bluetooth/sl_si91x_icm40627_3/icm40627_example.c
new file mode 100644
index 0000000..75f2ce2
--- /dev/null
+++ b/projects/bluetooth/sl_si91x_icm40627_3/icm40627_example.c
@@ -0,0 +1,208 @@
+/***************************************************************************/ /**
+ * @file icm40627_example.c
+ * @brief ICM40627 example APIs
+ *******************************************************************************
+ * # License
+ * Copyright 2024 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * The licensor of this software is Silicon Laboratories Inc. Your use of this
+ * software is governed by the terms of Silicon Labs Master Software License
+ * Agreement (MSLA) available at
+ * www.silabs.com/about-us/legal/master-software-license-agreement. This
+ * software is distributed to you in Source Code format and is governed by the
+ * sections of the MSLA applicable to Source Code.
+ *
+ ******************************************************************************/
+#include "rsi_debug.h"
+#include "sl_si91x_icm40627.h"
+#include "icm40627_example.h"
+#include "sl_sleeptimer.h"
+#include "sl_si91x_ssi.h"
+#include "rsi_rom_clks.h"
+#include "sl_status.h"
+#include "sl_si91x_driver_gpio.h"
+
+/*******************************************************************************
+ *************************** Defines / Macros ********************************
+ ******************************************************************************/
+#define DELAY_PERIODIC_MS1 2000 //sleeptimer1 periodic timeout in ms
+
+/*******************************************************************************
+ ****************************** Data Types ***********************************
+ ******************************************************************************/
+/*******************************************************************************
+ *************************** LOCAL VARIABLES *******************************
+ ******************************************************************************/
+sl_sleeptimer_timer_handle_t timer1; //sleeptimer1 handle
+boolean_t delay_timeout; //Indicates sleeptimer1 timeout
+// Remove static keyword
+sl_ssi_handle_t ssi_driver_handle = NULL;
+static uint32_t ssi_slave_number = SSI_SLAVE_0;
+/*******************************************************************************
+ ********************** Local Function prototypes ***************************
+ ******************************************************************************/
+static void on_timeout_timer1(sl_sleeptimer_timer_handle_t *handle, void *data);
+static sl_status_t enable_icm40627(bool connect);
+/*******************************************************************************
+ ************************** GLOBAL FUNCTIONS *******************************
+ ******************************************************************************/
+/*******************************************************************************
+ * RHT example initialization function
+ ******************************************************************************/
+void icm40627_example_init(void)
+{
+ sl_status_t sl_status;
+ uint8_t dev_id;
+
+ do {
+ // Enable the sensor
+ sl_status = enable_icm40627(true);
+ if (sl_status != SL_STATUS_OK) {
+ DEBUGOUT("ICM40627 enable failed, Error Code: 0x%ld \n", sl_status);
+ break;
+ } else {
+ DEBUGOUT("ICM40627 enable successful\n");
+ }
+
+ // SSI interface init moved to driver API
+ sl_status = sl_si91x_icm40627_ssi_interface_init(&ssi_driver_handle, ssi_slave_number);
+ if (sl_status != SL_STATUS_OK) {
+ DEBUGOUT("ICM40627 SSI interface init failed, Error Code: 0x%ld \n", sl_status);
+ break;
+ } else {
+ DEBUGOUT("ICM40627 SSI interface init successful\n");
+ }
+
+ //Start 2000 ms periodic timer
+ sl_sleeptimer_start_periodic_timer_ms(&timer1,
+ DELAY_PERIODIC_MS1,
+ on_timeout_timer1,
+ NULL,
+ 0,
+ SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG);
+ // reset the sensor
+ sl_status = sl_si91x_icm40627_software_reset(ssi_driver_handle);
+ if (sl_status != SL_STATUS_OK) {
+ DEBUGOUT("ICM40627 software reset un-successful, Error Code: 0x%ld \n", sl_status);
+ break;
+ } else {
+ DEBUGOUT("ICM40627 software reset successful\n");
+ }
+
+ // Read Who am I register, should get ICM40627_DEVICE_ID
+ sl_status = sl_si91x_icm40627_get_device_id(ssi_driver_handle, &dev_id);
+ if ((sl_status == SL_STATUS_OK) && (dev_id == ICM40627_DEVICE_ID)) {
+ DEBUGOUT("ICM40627 device ID verification successful \n");
+ } else {
+ DEBUGOUT("ICM40627 device ID verification failed\n");
+ break;
+ }
+
+ // Initializes sensor and reads electronic ID 1st byte
+ sl_status = sl_si91x_icm40627_init(ssi_driver_handle);
+ if (sl_status != SL_STATUS_OK) {
+ DEBUGOUT("ICM40627 initialization failed, Error Code: 0x%ld \n", sl_status);
+ break;
+ } else {
+ DEBUGOUT("ICM40627 initialization successful\n");
+ }
+ } while (false);
+}
+
+/*******************************************************************************
+ * Function will run continuously in while loop and reads relative humidity and
+ * temperature from sensor
+ ******************************************************************************/
+void icm40627_example_process_action(void)
+{
+ sl_status_t status;
+ float temperature = 0;
+ float sensor_data[3];
+ if (delay_timeout == true) {
+ delay_timeout = false;
+
+ //Reads temperature data from sensor
+ status = sl_si91x_icm40627_get_temperature_data(ssi_driver_handle, &temperature);
+ if (status != SL_STATUS_OK) {
+ DEBUGOUT("Temperature read failed, Error Code: 0x%ld \n", status);
+ } else {
+ DEBUGOUT("Temperature: %0.2lf\n", temperature);
+ }
+
+ //Reads accelerometer data from sensor
+ status = sl_si91x_icm40627_get_accel_data(ssi_driver_handle, sensor_data);
+ if (status != SL_STATUS_OK) {
+ DEBUGOUT("Acceleration read failed, Error Code: 0x%ld \n", status);
+ } else {
+ DEBUGOUT("Acceleration: { ");
+ for (int i = 0; i < 3; i++) {
+ DEBUGOUT("%0.2f ", sensor_data[i]);
+ }
+ DEBUGOUT("}\n");
+ }
+
+ //Reads gyro data from sensor
+ status = sl_si91x_icm40627_get_gyro_data(ssi_driver_handle, sensor_data);
+ if (status != SL_STATUS_OK) {
+ DEBUGOUT("Gyro read failed, Error Code: 0x%ld \n", status);
+ } else {
+ DEBUGOUT("Gyro: { ");
+ for (int i = 0; i < 3; i++) {
+ DEBUGOUT("%0.2f ", sensor_data[i]);
+ }
+ DEBUGOUT("}\n\n");
+ }
+ }
+}
+
+/***************************************************************************/ /**
+ * Sleeptimer timeout callback.
+ ******************************************************************************/
+static void on_timeout_timer1(sl_sleeptimer_timer_handle_t *handle, void *data)
+{
+ (void)&handle;
+ (void)&data;
+ delay_timeout = true;
+}
+
+/*******************************************************************************
+ * Function to connect ICM40627 Sensor
+ ******************************************************************************/
+static sl_status_t enable_icm40627(bool connect)
+{
+ sl_status_t status;
+ if (sl_si91x_gpio_driver_get_uulp_npss_pin(SENSOR_ENABLE_GPIO_PIN) != 1) {
+ // Enable GPIO ULP_CLK
+ status = sl_si91x_gpio_driver_enable_clock((sl_si91x_gpio_select_clock_t)ULPCLK_GPIO);
+ if (status != SL_STATUS_OK) {
+ return status;
+ }
+
+ if (connect) {
+ // Set NPSS GPIO pin MUX
+ status = sl_si91x_gpio_driver_set_uulp_npss_pin_mux(SENSOR_ENABLE_GPIO_PIN, NPSS_GPIO_PIN_MUX_MODE1);
+ if (status != SL_STATUS_OK) {
+ return status;
+ }
+ // Set NPSS GPIO pin direction
+ status =
+ sl_si91x_gpio_driver_set_uulp_npss_direction(SENSOR_ENABLE_GPIO_PIN, (sl_si91x_gpio_direction_t)GPIO_OUTPUT);
+ if (status != SL_STATUS_OK) {
+ return status;
+ }
+ // Set UULP GPIO pin
+ status = sl_si91x_gpio_driver_set_uulp_npss_pin_value(SENSOR_ENABLE_GPIO_PIN, SET);
+ if (status != SL_STATUS_OK) {
+ return status;
+ }
+ } else {
+ // Disable the sensor
+ status = sl_si91x_gpio_driver_set_uulp_npss_pin_value(SENSOR_ENABLE_GPIO_PIN, CLR);
+ if (status != SL_STATUS_OK) {
+ return status;
+ }
+ }
+ }
+ return SL_STATUS_OK;
+}
diff --git a/projects/bluetooth/sl_si91x_icm40627_3/icm40627_example.h b/projects/bluetooth/sl_si91x_icm40627_3/icm40627_example.h
new file mode 100644
index 0000000..7545f56
--- /dev/null
+++ b/projects/bluetooth/sl_si91x_icm40627_3/icm40627_example.h
@@ -0,0 +1,43 @@
+/***************************************************************************/ /**
+ * @file icm40627_example.h
+ * @brief ICM40627 example
+ *******************************************************************************
+ * # License
+ * Copyright 2023 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * The licensor of this software is Silicon Laboratories Inc. Your use of this
+ * software is governed by the terms of Silicon Labs Master Software License
+ * Agreement (MSLA) available at
+ * www.silabs.com/about-us/legal/master-software-license-agreement. This
+ * software is distributed to you in Source Code format and is governed by the
+ * sections of the MSLA applicable to Source Code.
+ *
+ ******************************************************************************/
+#include "sl_si91x_icm40627.h"
+#ifndef ICM40627_EXAMPLE_H_
+#define ICM40627_EXAMPLE_H_
+
+extern sl_ssi_handle_t ssi_driver_handle;
+/*******************************************************************************
+ ******************************** ENUMS ************************************
+ ******************************************************************************/
+
+// -----------------------------------------------------------------------------
+// Prototypes
+/***************************************************************************/ /**
+ * RHT example initialization function.
+ * @param none
+ * @return none
+ ******************************************************************************/
+void icm40627_example_init(void);
+
+/***************************************************************************/ /**
+ * Function will run continuously in while loop and reads relative humidity and
+ * temperature from sensor
+ * @param none
+ * @return none
+ ******************************************************************************/
+void icm40627_example_process_action(void);
+
+#endif /* ICM40627_EXAMPLE_H_ */
diff --git a/projects/bluetooth/sl_si91x_icm40627_3/main.c b/projects/bluetooth/sl_si91x_icm40627_3/main.c
new file mode 100644
index 0000000..0e4ba12
--- /dev/null
+++ b/projects/bluetooth/sl_si91x_icm40627_3/main.c
@@ -0,0 +1,27 @@
+#include "sl_component_catalog.h"
+#include "sl_main_init.h"
+#if defined(SL_CATALOG_POWER_MANAGER_PRESENT)
+#include "sl_power_manager.h"
+#endif
+#if defined(SL_CATALOG_KERNEL_PRESENT)
+#include "sl_main_kernel.h"
+#else // SL_CATALOG_KERNEL_PRESENT
+#include "sl_main_process_action.h"
+#endif // SL_CATALOG_KERNEL_PRESENT
+
+int main(void)
+{
+ sl_main_init();
+#if defined(SL_CATALOG_KERNEL_PRESENT)
+ sl_main_kernel_start();
+#else
+ app_init();
+ while (1) {
+ sl_main_process_action();
+ app_process_action();
+#if defined(SL_CATALOG_POWER_MANAGER_PRESENT)
+ sl_power_manager_sleep();
+#endif
+ }
+#endif
+}
diff --git a/projects/bluetooth/sl_si91x_icm40627_3/readme.md b/projects/bluetooth/sl_si91x_icm40627_3/readme.md
new file mode 100644
index 0000000..e0b934c
--- /dev/null
+++ b/projects/bluetooth/sl_si91x_icm40627_3/readme.md
@@ -0,0 +1,73 @@
+# SL ICM40627
+
+## Table of Contents
+
+- [SL ICM40627](#sl-icm40627)
+ - [Table of Contents](#table-of-contents)
+ - [Purpose/Scope](#purposescope)
+ - [About Example Code](#about-example-code)
+ - [Prerequisites/Setup Requirements](#prerequisitessetup-requirements)
+ - [Hardware Requirements](#hardware-requirements)
+ - [Software Requirements](#software-requirements)
+ - [Setup Diagram](#setup-diagram)
+ - [Getting Started](#getting-started)
+ - [Application Build Environment](#application-build-environment)
+ - [Test the Application](#test-the-application)
+
+## Purpose/Scope
+
+This application demonstrates the 6-axis inertial sensor (ICM-40627), which measures the motion parameters and temperature every 2 seconds.
+
+## About Example Code
+
+This example demonstrates the measurement of acceleration in 3 axes, gyroscope in 3 axes, and temperature every 2 seconds. It also shows how to use various APIs available via the SPI interface.
+
+## Prerequisites/Setup Requirements
+
+### Hardware Requirements
+
+- Windows PC
+- Silicon Labs SiWx917 Development Kit [ BRD2605A ]
+
+### Software Requirements
+
+- Simplicity Studio
+- Serial console setup
+ - The serial console setup instructions are provided in the
+ [Console Input and Output](https://docs.silabs.com/wiseconnect/latest/wiseconnect-developers-guide-developing-for-silabs-hosts/#console-input-and-output) section of the *WiSeConnect Developer's Guide*.
+
+### Setup Diagram
+
+
+
+## Getting Started
+
+Refer to the instructions [here](https://docs.silabs.com/wiseconnect/latest/wiseconnect-getting-started/) to:
+
+- [Install Simplicity Studio](https://docs.silabs.com/wiseconnect/latest/wiseconnect-developers-guide-developing-for-silabs-hosts/#install-simplicity-studio)
+- [Install WiSeConnect 3 extension](https://docs.silabs.com/wiseconnect/latest/wiseconnect-developers-guide-developing-for-silabs-hosts/#install-the-wi-se-connect-3-extension)
+- [Connect your device to the computer](https://docs.silabs.com/wiseconnect/latest/wiseconnect-developers-guide-developing-for-silabs-hosts/#connect-si-wx91x-to-computer)
+- [Upgrade your connectivity firmware](https://docs.silabs.com/wiseconnect/latest/wiseconnect-developers-guide-developing-for-silabs-hosts/#update-si-wx91x-connectivity-firmware)
+- [Create a Studio project](https://docs.silabs.com/wiseconnect/latest/wiseconnect-developers-guide-developing-for-silabs-hosts/#create-a-project)
+
+## Application Build Environment
+
+- Configure the following macros in the [`icm40627_example.c`](https://github.com/SiliconLabs/wiseconnect/blob/master/examples/si91x_soc/peripheral/sl_si91x_icm40627/icm40627_example.c) file and update/modify following macros, if required.
+
+- `DELAY_PERIODIC_MS1`: Select the delay for data display. By default, the delay is kept as 2 seconds.
+
+ ```C
+ #define DELAY_PERIODIC_MS1 2000 //sleeptimer1 periodic timeout in ms
+ ```
+
+> **Note**: For recommended settings, see the [recommendations guide](https://docs.silabs.com/wiseconnect/latest/wiseconnect-developers-guide-prog-recommended-settings/).
+
+## Test the Application
+
+Refer to the instructions [here](https://docs.silabs.com/wiseconnect/latest/wiseconnect-getting-started/) to:
+
+1. Compile and run the application.
+2. When the application runs, it measures accelerometer, gyroscope and temperature data for every 2 seconds.
+3. After successful program execution the prints in serial console looks as shown below.
+
+ 
diff --git a/projects/bluetooth/sl_si91x_icm40627_3/resources/readme/output1.png b/projects/bluetooth/sl_si91x_icm40627_3/resources/readme/output1.png
new file mode 100644
index 0000000..fc922c0
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diff --git a/projects/bluetooth/sl_si91x_icm40627_3/resources/readme/setupdiagram.png b/projects/bluetooth/sl_si91x_icm40627_3/resources/readme/setupdiagram.png
new file mode 100644
index 0000000..783cd6b
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diff --git a/projects/bluetooth/sl_si91x_icm40627_3/sl_si91x_icm40627_3.pintool b/projects/bluetooth/sl_si91x_icm40627_3/sl_si91x_icm40627_3.pintool
new file mode 100644
index 0000000..b71fc53
--- /dev/null
+++ b/projects/bluetooth/sl_si91x_icm40627_3/sl_si91x_icm40627_3.pintool
@@ -0,0 +1,10 @@
+
+
+
+
+
+
+
+
+
+
diff --git a/projects/bluetooth/sl_si91x_icm40627_3/sl_si91x_icm40627_3.slcp b/projects/bluetooth/sl_si91x_icm40627_3/sl_si91x_icm40627_3.slcp
new file mode 100644
index 0000000..e688567
--- /dev/null
+++ b/projects/bluetooth/sl_si91x_icm40627_3/sl_si91x_icm40627_3.slcp
@@ -0,0 +1,53 @@
+# Silicon Labs Project Configuration Tools: slcp, v0, Component selection file.
+project_name: sl_si91x_icm40627_3
+label: sl_si91x_icm40627_3
+description: "This application demonstrates how to configure and use the ICM40627\
+ \ motion sensor, a 6-axis sensor that combines a 3-axis accelerometer and a 3-axis\
+ \ gyroscope. \nThe example covers how to initialize the sensor, configure its settings\
+ \ for various motion detection tasks, and retrieve sensor data for further processing,\
+ \ enabling motion-based applications.\n"
+category: example|peripheral
+package: platform
+quality: production
+readme:
+- {path: readme.md}
+- {path: readme.md}
+source:
+- {path: app.c}
+- {path: icm40627_example.c}
+include:
+- path: .
+ file_list:
+ - {path: app.h}
+ - {path: icm40627_example.h}
+sdk: {id: simplicity_sdk, version: 2025.6.2}
+toolchain_settings:
+- {value: -Wall -Werror, option: gcc_compiler_option}
+component:
+- {from: wiseconnect3_sdk, id: SIWG917M111MGTBA}
+- {from: wiseconnect3_sdk, id: brd2605a}
+- {from: wiseconnect3_sdk, id: si91x_memory_default_config}
+- {from: wiseconnect3_sdk, id: sl_icm40627}
+- {from: wiseconnect3_sdk, id: sl_ssi}
+- instance: [ulp_primary]
+ from: wiseconnect3_sdk
+ id: sl_ssi_instance
+- {from: wiseconnect3_sdk, id: ssi_ulp_component}
+- {from: wiseconnect3_sdk, id: syscalls}
+- {id: sl_main}
+- {id: sleeptimer}
+other_file:
+- {path: resources/readme/setupdiagram.png}
+- {path: resources/readme/output1.png}
+configuration:
+- {name: SL_SSI_DEVICE_MODE, value: SL_SSI_ULP_MASTER_ACTIVE}
+- {name: SL_SPI_BAUD, value: '5000000'}
+- {name: SL_ULP_TIMER_DIRECTION, value: '1'}
+ui_hints:
+ highlight:
+ - {path: readme.md, focus: true}
+sdk_extension:
+- {id: wiseconnect3_sdk, version: 3.5.2}
+post_build:
+- {path: sl_si91x_icm40627_3.slpb}
+
diff --git a/projects/bluetooth/sl_si91x_icm40627_3/sl_si91x_icm40627_3.slpb b/projects/bluetooth/sl_si91x_icm40627_3/sl_si91x_icm40627_3.slpb
new file mode 100644
index 0000000..287a2c0
--- /dev/null
+++ b/projects/bluetooth/sl_si91x_icm40627_3/sl_si91x_icm40627_3.slpb
@@ -0,0 +1,21 @@
+---
+parameters:
+- name: "build_dir"
+constants:
+- name: "project_name"
+ value: "sl_si91x_icm40627_3"
+steps:
+- task: "create_rps"
+ output: "{{build_dir}}/{{project_name}}.rps"
+ input: "{{build_dir}}/{{project_name}}.out"
+ map: "{{build_dir}}/{{project_name}}.map"
+ app-version: "1"
+- task: "convert"
+ output: "{{build_dir}}/{{project_name}}.hex"
+ input: "{{build_dir}}/{{project_name}}.rps"
+- task: "convert"
+ output: "{{build_dir}}/{{project_name}}.s37"
+ input: "{{build_dir}}/{{project_name}}.rps"
+- task: "convert"
+ output: "{{build_dir}}/{{project_name}}_isp.bin"
+ input: "{{build_dir}}/{{project_name}}.rps"
diff --git a/projects/bluetooth/sl_si91x_icm40627_3/sl_si91x_icm40627_3.slps b/projects/bluetooth/sl_si91x_icm40627_3/sl_si91x_icm40627_3.slps
new file mode 100644
index 0000000..a0ea4f4
--- /dev/null
+++ b/projects/bluetooth/sl_si91x_icm40627_3/sl_si91x_icm40627_3.slps
@@ -0,0 +1,17 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file