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66 | 66 |
|
67 | 67 | #include <Arduino.h> |
68 | 68 | #include "debug.h" |
| 69 | +#include "stdint.h" |
69 | 70 |
|
70 | 71 | #if ENABLE_OCPP |
71 | 72 | #include <MicroOcpp/Model/ConnectorBase/Notification.h> |
|
88 | 89 | #define PIN_SSR2 27 |
89 | 90 | #define PIN_LCD_LED 14 |
90 | 91 | #define PIN_LEDB 12 |
91 | | -#define PIN_RCM_FAULT 13 |
| 92 | +#define PIN_RCM_FAULT 13 //TODO ok for v4? |
92 | 93 |
|
93 | 94 | // Pin definitions right side ESP32 |
94 | 95 | #define PIN_RS485_RX 23 |
|
106 | 107 | #define PIN_LEDR 2 |
107 | 108 | #define PIN_CPOFF 15 |
108 | 109 |
|
| 110 | +#if SMARTEVSE_VERSION == 3 |
109 | 111 | #define SPI_MOSI 33 // SPI connections to LCD |
110 | 112 | #define SPI_MISO -1 |
111 | 113 | #define SPI_SCK 26 |
112 | 114 | #define SPI_SS -1 |
| 115 | +#endif //SMARTEVSE_VERSION |
113 | 116 |
|
114 | 117 | #define CP_CHANNEL 0 |
115 | 118 | #define RED_CHANNEL 2 // PWM channel 2 (0 and 1 are used by CP signal) |
|
201 | 204 | #define STATE_ACTSTART 8 // I Activation mode in progress |
202 | 205 | #define STATE_B1 9 // J Vehicle connected / EVSE not ready to deliver energy: no PWM signal |
203 | 206 | #define STATE_C1 10 // K Vehicle charging / EVSE not ready to deliver energy: no PWM signal (temp state when stopping charge from EVSE) |
| 207 | +//#if SMARTEVSE_VERSION == 3 TODO |
204 | 208 | #define STATE_MODEM_REQUEST 11 // L Vehicle connected / requesting ISO15118 communication, 0% duty |
205 | 209 | #define STATE_MODEM_WAIT 12 // M Vehicle connected / requesting ISO15118 communication, 5% duty |
206 | 210 | #define STATE_MODEM_DONE 13 // Modem communication succesful, SoCs extracted. Here, re-plug vehicle |
207 | 211 | #define STATE_MODEM_DENIED 14 // Modem access denied based on EVCCID, re-plug vehicle and try again |
| 212 | +//#else |
| 213 | +//#define STATE_E 11 // disconnected pilot / powered down |
| 214 | +//#define STATE_F 12 // -12V Fault condition |
| 215 | +//#endif |
208 | 216 |
|
209 | 217 | #define NOSTATE 255 |
210 | 218 |
|
|
252 | 260 | #define ACTUATOR_UNLOCK { _LOG_A("Unlocking Actuator.\n"); digitalWrite(PIN_ACTB, LOW); digitalWrite(PIN_ACTA, HIGH); } |
253 | 261 | #define ACTUATOR_OFF { digitalWrite(PIN_ACTB, HIGH); digitalWrite(PIN_ACTA, HIGH); } |
254 | 262 |
|
255 | | -#define RCMFAULT digitalRead(PIN_RCM_FAULT) |
| 263 | +#define RCMFAULT digitalRead(PIN_RCM_FAULT) //TODO ok for v4? |
256 | 264 |
|
257 | 265 | #define MODBUS_INVALID 0 |
258 | 266 | #define MODBUS_OK 1 |
@@ -365,7 +373,6 @@ typedef enum mb_datatype { |
365 | 373 | MB_DATATYPE_MAX, |
366 | 374 | } MBDataType; |
367 | 375 |
|
368 | | - |
369 | 376 | extern portMUX_TYPE rtc_spinlock; //TODO: Will be placed in the appropriate position after the rtc module is finished. |
370 | 377 |
|
371 | 378 | #define RTC_ENTER_CRITICAL() portENTER_CRITICAL(&rtc_spinlock) |
@@ -538,4 +545,180 @@ MicroOcpp::TxNotification ocppGetTxNotification(); |
538 | 545 | bool ocppLockingTxDefined(); |
539 | 546 | #endif //ENABLE_OCPP |
540 | 547 |
|
| 548 | +#if SMARTEVSE_VERSION == 4 |
| 549 | +// Pin definitions |
| 550 | +#define PIN_QCA700X_INT 9 // SPI connections to QCA7000X |
| 551 | +#define PIN_QCA700X_CS 11 // on ESP-S3 with OCTAL flash/PSRAM, GPIO pins 33-37 can not be used! |
| 552 | +#define SPI_MOSI 13 |
| 553 | +#define SPI_MISO 12 |
| 554 | +#define SPI_SCK 10 |
| 555 | +#define PIN_QCA700X_RESETN 45 |
| 556 | + |
| 557 | +#define USART_TX 43 // comm bus to mainboard |
| 558 | +#define USART_RX 44 |
| 559 | + |
| 560 | +#define BUTTON1 0 // Navigation buttons |
| 561 | +//#define BUTTON2 1 // renamed from prototype! |
| 562 | +#define BUTTON3 2 |
| 563 | + |
| 564 | +#define RTC_SDA 6 // RTC interface |
| 565 | +#define RTC_SCL 7 |
| 566 | +#define RTC_INT 16 |
| 567 | + |
| 568 | +// New top board |
| 569 | +#define WCH_NRST 8 // microcontroller program interface |
| 570 | +#define WCH_SWDIO 17 // unconnected!!! pin on 16pin connector is used for LCD power |
| 571 | +#define WCH_SWCLK 18 |
| 572 | + |
| 573 | +// Old prototype top board |
| 574 | +//#define WCH_NRST 18 // microcontroller program interface |
| 575 | +//#define WCH_SWDIO 8 |
| 576 | +//#define WCH_SWCLK 17 |
| 577 | + |
| 578 | +#define LCD_SDA 38 // LCD interface |
| 579 | +#define LCD_SCK 39 |
| 580 | +#define LCD_A0_B2 40 |
| 581 | +#define LCD_LED 41 |
| 582 | +#define LCD_RST 42 |
| 583 | +#define LCD_CS 1 |
| 584 | + |
| 585 | +#define LCD_CHANNEL 5 // PWM channel |
| 586 | + |
| 587 | +#define LCD_RST_0 digitalWrite(LCD_RST, LOW); |
| 588 | +#define LCD_RST_1 digitalWrite(LCD_RST, HIGH); |
| 589 | +#define LCD_A0_0 digitalWrite(LCD_A0_B2, LOW); |
| 590 | +#define LCD_A0_1 digitalWrite(LCD_A0_B2, HIGH); |
| 591 | + |
| 592 | + |
| 593 | +// RTC power sources |
| 594 | +#define BATTERY 0x0C // Trickle charger (TCE) disabled, Level Switching Mode (LSM) enabled. |
| 595 | +#define SUPERCAP 0x24 // Trickle charger (TCE) enabled, Direct Switching Mode (DSM) enabled. |
| 596 | + |
| 597 | + |
| 598 | + |
| 599 | + |
| 600 | +// ESP-WCH Communication States |
| 601 | +#define COMM_OFF 0 |
| 602 | +#define COMM_VER_REQ 1 // Version Reqest ESP -> WCH |
| 603 | +#define COMM_VER_RSP 2 // Version Response ESP <- WCH |
| 604 | +#define COMM_CONFIG_SET 3 // Configuration Set ESP -> WCH |
| 605 | +#define COMM_CONFIG_CNF 4 // Configuration confirm. ESP <- WCH |
| 606 | +#define COMM_STATUS_REQ 5 // Status Request |
| 607 | +#define COMM_STATUS_RSP 6 // Status Response |
| 608 | + |
| 609 | +/*====================================================================* |
| 610 | + * SPI registers QCA700X |
| 611 | + *--------------------------------------------------------------------*/ |
| 612 | + |
| 613 | +#define QCA7K_SPI_READ (1 << 15) // MSB(15) of each command (16 bits) is the read(1) or write(0) bit. |
| 614 | +#define QCA7K_SPI_WRITE (0 << 15) |
| 615 | +#define QCA7K_SPI_INTERNAL (1 << 14) // MSB(14) sets the Internal Registers(1) or Data Buffer(0) |
| 616 | +#define QCA7K_SPI_EXTERNAL (0 << 14) |
| 617 | + |
| 618 | +#define SPI_REG_BFR_SIZE 0x0100 |
| 619 | +#define SPI_REG_WRBUF_SPC_AVA 0x0200 |
| 620 | +#define SPI_REG_RDBUF_BYTE_AVA 0x0300 |
| 621 | +#define SPI_REG_SPI_CONFIG 0x0400 |
| 622 | +#define SPI_REG_INTR_CAUSE 0x0C00 |
| 623 | +#define SPI_REG_INTR_ENABLE 0x0D00 |
| 624 | +#define SPI_REG_RDBUF_WATERMARK 0x1200 |
| 625 | +#define SPI_REG_WRBUF_WATERMARK 0x1300 |
| 626 | +#define SPI_REG_SIGNATURE 0x1A00 |
| 627 | +#define SPI_REG_ACTION_CTRL 0x1B00 |
| 628 | + |
| 629 | +#define QCASPI_GOOD_SIGNATURE 0xAA55 |
| 630 | +#define QCA7K_BUFFER_SIZE 3163 |
| 631 | + |
| 632 | +#define SPI_INT_WRBUF_BELOW_WM (1 << 10) |
| 633 | +#define SPI_INT_CPU_ON (1 << 6) |
| 634 | +#define SPI_INT_ADDR_ERR (1 << 3) |
| 635 | +#define SPI_INT_WRBUF_ERR (1 << 2) |
| 636 | +#define SPI_INT_RDBUF_ERR (1 << 1) |
| 637 | +#define SPI_INT_PKT_AVLBL (1 << 0) |
| 638 | + |
| 639 | +/*====================================================================* |
| 640 | + * Modem States |
| 641 | + *--------------------------------------------------------------------*/ |
| 642 | + |
| 643 | +#define MODEM_POWERUP 0 |
| 644 | +#define MODEM_WRITESPACE 1 |
| 645 | +#define MODEM_CM_SET_KEY_REQ 2 |
| 646 | +#define MODEM_CM_SET_KEY_CNF 3 |
| 647 | +#define MODEM_CONFIGURED 10 |
| 648 | +#define SLAC_PARAM_REQ 20 |
| 649 | +#define SLAC_PARAM_CNF 30 |
| 650 | +#define MNBC_SOUND 40 |
| 651 | +#define ATTEN_CHAR_IND 50 |
| 652 | +#define ATTEN_CHAR_RSP 60 |
| 653 | +#define SLAC_MATCH_REQ 70 |
| 654 | + |
| 655 | +#define MODEM_LINK_STATUS 80 |
| 656 | +#define MODEM_WAIT_LINK 90 |
| 657 | +#define MODEM_GET_SW_REQ 100 |
| 658 | +#define MODEM_WAIT_SW 110 |
| 659 | +#define MODEM_LINK_READY 120 |
| 660 | + |
| 661 | + |
| 662 | +/*====================================================================* |
| 663 | + * SLAC commands |
| 664 | + *--------------------------------------------------------------------*/ |
| 665 | + |
| 666 | +#define CM_SET_KEY 0x6008 |
| 667 | +#define CM_GET_KEY 0x600C |
| 668 | +#define CM_SC_JOIN 0x6010 |
| 669 | +#define CM_CHAN_EST 0x6014 |
| 670 | +#define CM_TM_UPDATE 0x6018 |
| 671 | +#define CM_AMP_MAP 0x601C |
| 672 | +#define CM_BRG_INFO 0x6020 |
| 673 | +#define CM_CONN_NEW 0x6024 |
| 674 | +#define CM_CONN_REL 0x6028 |
| 675 | +#define CM_CONN_MOD 0x602C |
| 676 | +#define CM_CONN_INFO 0x6030 |
| 677 | +#define CM_STA_CAP 0x6034 |
| 678 | +#define CM_NW_INFO 0x6038 |
| 679 | +#define CM_GET_BEACON 0x603C |
| 680 | +#define CM_HFID 0x6040 |
| 681 | +#define CM_MME_ERROR 0x6044 |
| 682 | +#define CM_NW_STATS 0x6048 |
| 683 | +#define CM_SLAC_PARAM 0x6064 |
| 684 | +#define CM_START_ATTEN_CHAR 0x6068 |
| 685 | +#define CM_ATTEN_CHAR 0x606C |
| 686 | +#define CM_PKCS_CERT 0x6070 |
| 687 | +#define CM_MNBC_SOUND 0x6074 |
| 688 | +#define CM_VALIDATE 0x6078 |
| 689 | +#define CM_SLAC_MATCH 0x607C |
| 690 | +#define CM_SLAC_USER_DATA 0x6080 |
| 691 | +#define CM_ATTEN_PROFILE 0x6084 |
| 692 | +#define CM_GET_SW 0xA000 |
| 693 | +#define CM_LINK_STATUS 0xA0B8 |
| 694 | + |
| 695 | +#define MMTYPE_REQ 0x0000 // request |
| 696 | +#define MMTYPE_CNF 0x0001 // confirmation = +1 |
| 697 | +#define MMTYPE_IND 0x0002 |
| 698 | +#define MMTYPE_RSP 0x0003 |
| 699 | + |
| 700 | +// Frametypes |
| 701 | + |
| 702 | +#define FRAME_IPV6 0x86DD |
| 703 | +#define FRAME_HOMEPLUG 0x88E1 |
| 704 | + |
| 705 | +/* V2GTP */ |
| 706 | +#define V2GTP_HEADER_SIZE 8 /* header has 8 bytes */ |
| 707 | + |
| 708 | +extern struct tm timeinfo; |
| 709 | + |
| 710 | +#include <stdint.h> |
| 711 | +#include "debug.h" |
| 712 | + |
| 713 | +struct rtcTime { |
| 714 | + uint8_t Status; |
| 715 | + uint8_t Hour; |
| 716 | + uint8_t Minute; |
| 717 | + uint8_t Second; |
| 718 | + uint8_t Date; |
| 719 | + uint8_t Month; |
| 720 | + uint16_t Year; |
| 721 | +} ; |
| 722 | + |
| 723 | +#endif //SMARTEVSE_VERSION |
541 | 724 | #endif |
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