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Josua-SRJosua-SR
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uboot: fix cn9132-cex7 spi flash access, shrink size, fix sd-cd
1 parent 62b7b58 commit 522599a

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-0
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3 files changed

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‎configs/u-boot/cn913x_additions.config‎

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Original file line numberDiff line numberDiff line change
@@ -25,3 +25,12 @@ CONFIG_CMD_WDT=y
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# CONFIG_CMD_NAND is not set
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# CONFIG_MTD_RAW_NAND is not set
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# CONFIG_NAND_PXA3XX is not set
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# CONFIG_CMD_EXT4_WRITE is not set
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# CONFIG_EXT4_WRITE is not set
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# CONFIG_SPI_FLASH_MACRONIX is not set
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# CONFIG_SPI_FLASH_SPANSION is not set
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# CONFIG_SPI_FLASH_STMICRO is not set
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# CONFIG_SPI_FLASH_SST is not set
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CONFIG_SPI_FLASH_WINBOND=y
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# CONFIG_ENV_SPI_MAX_HZ is not set
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# CONFIG_MMC_BROKEN_CD is not set

‎patches/u-boot/0023-spi-kirkwood-add-quirk-for-cn9132-cex7-miso-sample-d.patch‎

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@@ -0,0 +1,108 @@
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From a89f6202fb0cdca043a7864cdc469b7ffd63b825 Mon Sep 17 00:00:00 2001
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From: Josua Mayer <josua@solid-run.com>
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Date: Thu, 11 Sep 2025 15:25:47 +0200
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Subject: [PATCH 23/24] spi: kirkwood: add quirk for cn9132 cex7: miso sample
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delay
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Set miso sample delay to 3 core-clk cycles to avoid bit errros that are
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consistent with 1 cycle delay and sporadic with 2 cycles.
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At 3 cycles access is stable.
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Signed-off-by: Josua Mayer <josua@solid-run.com>
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---
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arch/arm/include/asm/arch-mvebu/spi.h | 1 +
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drivers/spi/kirkwood_spi.c | 43 ++++++++++++++++++++++-----
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2 files changed, 36 insertions(+), 8 deletions(-)
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diff --git a/arch/arm/include/asm/arch-mvebu/spi.h b/arch/arm/include/asm/arch-mvebu/spi.h
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index 58b6c32c4d..7bfee7343e 100644
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--- a/arch/arm/include/asm/arch-mvebu/spi.h
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+++ b/arch/arm/include/asm/arch-mvebu/spi.h
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@@ -50,6 +50,7 @@ struct kwspi_registers {
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#define KW_SPI_TMISO_SAMPLE_MASK (0x3 << KW_SPI_TMISO_SAMPLE_OFFSET)
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#define KW_SPI_TMISO_SAMPLE_1 (1 << KW_SPI_TMISO_SAMPLE_OFFSET)
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#define KW_SPI_TMISO_SAMPLE_2 (2 << KW_SPI_TMISO_SAMPLE_OFFSET)
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+#define KW_SPI_TMISO_SAMPLE_3 (3 << KW_SPI_TMISO_SAMPLE_OFFSET)
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#define KWSPI_IRQUNMASK 1 /* unmask SPI interrupt */
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#define KWSPI_IRQMASK 0 /* mask SPI interrupt */
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diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c
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index bc5da0a1e6..3fb9dde34e 100644
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--- a/drivers/spi/kirkwood_spi.c
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+++ b/drivers/spi/kirkwood_spi.c
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@@ -182,12 +182,39 @@ static int mvebu_spi_set_speed(struct udevice *bus, uint hz)
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return 0;
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}
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-static void mvebu_spi_50mhz_ac_timing_erratum(struct udevice *bus, uint mode)
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+/* configure extra miso sample delay */
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+static int mvebu_spi_set_miso_sample_delay(struct udevice *bus, const uint8_t cycles)
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{
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struct mvebu_spi_plat *plat = dev_get_plat(bus);
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struct kwspi_registers *reg = plat->spireg;
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u32 data;
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+ data = readl(&reg->timing1);
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+ data &= ~KW_SPI_TMISO_SAMPLE_MASK;
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+
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+ switch (cycles) {
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+ case 0:
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+ break;
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+ case 1:
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+ data |= KW_SPI_TMISO_SAMPLE_1;
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+ break;
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+ case 2:
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+ data |= KW_SPI_TMISO_SAMPLE_2;
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+ break;
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+ case 3:
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+ data |= KW_SPI_TMISO_SAMPLE_3;
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+ break;
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+ default:
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+ return -EINVAL;
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+ }
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+
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+ writel(data, &reg->timing1);
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+
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+ return 0;
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+}
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+
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+static void mvebu_spi_50mhz_ac_timing_erratum(struct udevice *bus, uint mode)
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+{
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/*
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* Erratum description: (Erratum NO. FE-9144572) The device
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* SPI interface supports frequencies of up to 50 MHz.
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@@ -202,17 +229,12 @@ static void mvebu_spi_50mhz_ac_timing_erratum(struct udevice *bus, uint mode)
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* 2. Set TMISO_SAMPLE value to 0x2 in "SPI Timing Parameters 1
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* Register" before setting the interface.
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*/
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- data = readl(&reg->timing1);
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- data &= ~KW_SPI_TMISO_SAMPLE_MASK;
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-
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if (CONFIG_SYS_TCLK == 250000000 &&
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mode & SPI_CPOL &&
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mode & SPI_CPHA)
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- data |= KW_SPI_TMISO_SAMPLE_2;
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+ mvebu_spi_set_miso_sample_delay(bus, 2);
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else
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- data |= KW_SPI_TMISO_SAMPLE_1;
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-
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- writel(data, &reg->timing1);
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+ mvebu_spi_set_miso_sample_delay(bus, 1);
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}
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static int mvebu_spi_set_mode(struct udevice *bus, uint mode)
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@@ -235,6 +257,11 @@ static int mvebu_spi_set_mode(struct udevice *bus, uint mode)
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if (plat->is_errata_50mhz_ac)
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mvebu_spi_50mhz_ac_timing_erratum(bus, mode);
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+ /* CN9132 CEX-7 requires 3 cycles delay before sampling miso to avoid bit errors */
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+ if (of_machine_is_compatible("solidrun,cn9132-sr-cex7") &&
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+ ofnode_to_offset(dev_ofnode(bus)) == ofnode_to_offset(ofnode_path("/cp0/config-space/spi@700680")))
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+ mvebu_spi_set_miso_sample_delay(bus, 3);
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+
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return 0;
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}
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--
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2.51.0
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‎patches/u-boot/0024-arch-arm-dts-cn9130-sr-cex7-enable-fast-read-for-spi.patch‎

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,29 @@
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From c8d8fc41fc4c3c2f2f2dc9efbdbf723fcbe6e896 Mon Sep 17 00:00:00 2001
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From: Josua Mayer <josua@solid-run.com>
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Date: Thu, 11 Sep 2025 15:31:54 +0200
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Subject: [PATCH 24/24] arch: arm: dts: cn9130-sr-cex7: enable fast-read for
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spi flash
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The spi flash on cex7 module supports fast read command, enable in
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device-tree.
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Signed-off-by: Josua Mayer <josua@solid-run.com>
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---
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arch/arm/dts/cn9132-sr-cex7.dtsi | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/arch/arm/dts/cn9132-sr-cex7.dtsi b/arch/arm/dts/cn9132-sr-cex7.dtsi
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index c4723bb96a..c0c3083e86 100644
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--- a/arch/arm/dts/cn9132-sr-cex7.dtsi
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+++ b/arch/arm/dts/cn9132-sr-cex7.dtsi
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@@ -254,6 +254,7 @@
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reg = <0>;
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/* read command supports max. 50MHz */
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spi-max-frequency = <50000000>;
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+ m25p,fast-read;
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};
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};
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--
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2.51.0
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